National Electronics Manufacturing Initiative (NEMI) initiated six projects in late 2001 and 2002 addressing key
issues identified by the industry. These cover the areas of Fiber Management,Signal Integrity,Splicing,Selective
Soldering,Adhesives and Substrates. The objectives of the groups included structuring the key issues,collecting
data and presenting them in a form useful to members and to the IPC and other optoelectronics standards initiatives.
An update on the progress of each of these projects will be given.

High speed systems operating at speeds of 2GHz and above are placing increasing demands on the
specifications of substrates and packaging of
components used within these systems. BPA has
reviewed those systems that are driving technology
developments
These are:
• High end router
• Enterprise server – high end and blade
• Wireless base station
• Military and Aerospace control and
communication

We have organized in JPCA a committee for the standardization of optoelectronic assembly technology in
collaboration with JIEP (Japan Institute of Electronics Packaging) with cooperation of JEITA (Japan Electronics and
Information Technology Association),OITDA (Optoelectronic Industry and Technology Development Association
– Japan) and ACET (Association of Super-Advanced Electronics Technologies). We consider that our effort is to
compliment the similar effort to prepare IPC0040,the basic document in this area,and necessary specific
specifications. We are in contact with the IPC 5-25 Committee. The available information/documents we generate
may be shared with IPC and JPCA.
We will concentrate our effort to specify interface technology of packages and boards that may constitute the
standardization item 318,stated in IPC0040,“Methods for optoelectronic component attachment and alignment”,
including 1) Optical printed board (include optical Interface in the board) 2) Connector of board edge (Include
optical interface) and 3) Optical package (Include optical interface). The very details of the contents are to be
finalized,however,our schedule is to prepare relevant drafts within a half year time. This presentation is a status
summary prepared for IPC APEX 2003.

The OEM desires identified in the 2002 – 2003
roadmap clearly identify,through their emulators,the
present and future needs of the products that the
emulators represent. There are a total of eight
emulators. Each emulator is broken down into the
technical drivers that help identify the OEM needs
for the different time frames established for this
Technology Roadmap. The emulator technical driver
information is organized into four major areas. These
are:
• Design Issues
• Printed Board Technology Issues
• Board Assembly Technology Issues
• Printed Board Purchasing Issues
The emulator attributes in design include such drivers
as on-chip rise time,minimum voltages,thermal
dissipation factors,reliability issues,and maximum
board temperature requirements. Printed board
technology attributes deal with materials,board size,
layer count,etc.; board assembly technology
attributes consider number of components,number of
solder joints,and type of assembly; purchasing issues
deal with the cost per interconnect and if assembly is
recyclable.
The emulators represent a quantitative summary of
the expected changes in board,component,and
assembly technology from 2002 to 2012. These
changes are addressed in two different product
categories: Revenue Center of Gravity (RCG) and
State of the Art (SoA). Revenue center of gravity
products represent the bulk of revenue and are
considered to be conventional technology; state of the
art technology is in production by only a few
manufacturers. SoA technology represents less than
5% of the world’s production. Table 1 is the Mid Size
System emulator for this new roadmap.

Tin whiskers found in electroplated deposits are known to be single crystals which spontaneously grow. Thus
whisker growth can be regarded as a grain growth phenomenon. In this paper we examine whisker grain growth in
the context of the well-developed principles of recrystallization process as applied to bulk metals that have
undergone deformation and annealing. As a grain grows in whisker form,recrystallization process must take place
as tin atoms rearrange in to the lattice structure of the elongating grain. Peculiarities of tin deposit structure that may
cause whisker growth are discussed. Frank-Read source of dislocations is proposed as a possible mechanism for
whisker formation. The effect of various factors on whiskering is analyzed.
Recrystallization theory postulates that shear strain introduced by plastic deformation is stored in the metal in the
form of dislocations (lattice defects). In bulk metals,produced metallurgically from the molten phase,these lattice
defects usually are not present in noticeable quantity unless the material is subjected to cold work (plastic
deformation at temperatures significantly below melting point). In electroplated tin,however,the metal is formed at
the temperatures much below melting point. During plating,energy is stored in the deposit in the form of crystal
defects such as vacancies and dislocations. This causes the crystal structure of metal deposits to resemble the
structure of cold worked metals,and thus forms the starting point for application of recrystallization principles.
The second important factor that justifies the application of recrystallization/grain growth principles to whisker
formation is related to the low recrystallization temperature of tin. Recrystallization temperature is defined as the
temperature at which a particular metal with particular amount of cold deformation will completely recrystallize
within one hour. Typically,it can be estimated as between 0.4 and 0.7 Tm (where Tm is the melting temperature). It
is a well-known fact that in most metals,recrystallization occurs at elevated temperatures. For tin,however,the
recrystallization temperature is approximately 30°C,which means that recrystallization will spontaneously occur
around room temperature (above and below 30°C),reforming a strain-free structure.1
These two factors – strain stored in the deposits in the form of dislocations and recrystallization at room
temperature,substantiate the application of recrystallization process principles to whisker formation. But before we
elaborate on this hypothesis,let us briefly summarize the principles of recrystallization process.

Over the past years there has been consistent growth in the use of electroless nickel/immersion gold (ENIG) as a
final finish. The finish is now frequently being used for PBGA,CSP,QFP and COB and more recently gathered
considerable interest as a low cost under-bump metallization for flip chip bumping application.
One of the largest users for this finish has been the telecommunication industry,were millions of square meters
of PCBs with ENIG have been successfully used.
The nickel layer offers advantages such as multiple soldering cycles and hand reworks without copper
dissolution being a factor. The nickel also acts as a reinforcement to improve through-hole and blind micro via
thermal integrity. In addition the nickel layer offers advantages such as co-planarity,Al-wire bondability and the
use as contact surface for keypads or contact switching. Especially those pads,which are not covered by solder
need a protective coating in corrosive environment – such as high humidity or pollutant gas.
This paper describes the influence of co-deposited Phosphorus within the Nickel layer,regarding the influence
to the ENIG process itself (especially the corrosive attack of the immersion gold reaction) and the survivability
of PCBs in corrosive atmosphere.
Within this paper,different test methods are described and discussed to check the protective performance of a
high Phosphorus ENIG layer.

The wetting of alternative PCB surface finishes,including immersion silver (I-Ag) and immersion tin (I-Sn),by
Sn/Ag/Cu solder and Sn/Pb solder,was studied in this work,along with electroless nickel/immersion gold (Ni/Au)
and organic solderability preservative (OSP) finishes for comparison. Evaluation of wetting was carried out with
fresh boards and boards subjected to different pre-conditioning treatments which simulated the effects of aging,
storage and multiple reflow cycles. Selected conditions consisted of high temperature aging at 155°C for up to 6 and
12 hours,temperature-moisture exposure at 85°C/85%RH for 6,12 and 24 hours,and reflow treatments between 2
and 4 reflow cycles. Wetting was studied based on the IPC-TM-650 2.4.45 standard,by a wetting bar test,and by a
wave soldering test.
The results show that when the boards are fresh,the wetting of the I-Sn finish is excellent and comparable to that of
the Ni/Au finish,and the wetting of I-Ag is slightly better than that of the OSP finish. However,after the preconditioning
treatments,the wetting of the I-Sn finish degrades the fastest,whereas the wetting of the I-Ag and OSP
finishes decrease almost at the same rate after different pre-conditioning treatments,while the wetting of the Ni/Au
finish remains excellent through all the pre-conditionings treatments. In all cases,the wetting of surfaces is better by
the Sn/Pb solder than by the lead-free solder.

Lead-free soldering technology is still in its infancy with technical and cost issues posing major challenges for the
industry. It is expected that soldering in a nitrogen atmosphere might overcome some of the technical barriers and
provide soldered products comparable to those using conventional lead-containing materials processed in air. But
quantitative data regarding the soldering behaviour of lead-free solders under various atmospheres are sparse. As
part of an ongoing study on the effects of inerting on the solderability of lead-free alloys an examination has been
made of the solderability,as measured in a wetting balance,of three common board finishes using a 95.5/3.8/0.7
SnAgCu solder. The board finishes used were ENIG,HASL,immersion silver and a copper OSP. To simulate
typical lead-free soldering cycles the samples were subjected to multiple temperature cycles in a convection reflow
oven before solderability testing using a Multicore MUST II tester. A peak reflow temperature of 250°C and an R
flux was used for the ENIG and Ag finishes. The OSP finish performed poorly under these conditions and OSP
testing was done using a 235°C peak temperature and a 0.5% activated R flux. During testing the atmospheres were
controlled at levels of oxygen of 21% (air),10,000,1000 and 100ppm. Although inerting improved the solderability
of all three finishes,there were differences between the individual alloys. Aging by multiple reflow cycles adversely
affected the solderability of all finishes but the effects were less for ENIG than the other finishes.

The impact cooling rates exert on the reflow process is identified. The trends in shear strength and the
microstructural evolution of the solder joints are described. Lead free (Sn/3.5Ag/0.7Cu) and tin lead (63Sn/37Pb)
assemblies on copper organic solder preservative (Cu-OSP),electroless nickel-immersion gold (ENIG),and
immersion tin (Imm Sn) surface finishes were considered in this experiment. A Differential Scanning Calorimeter
(DSC) was used to simulate the heating and the cooling cycles undergo by solder in the reflow process. The strength
values and the analysis of microstructure were documented using an Instron Machine and Scanning Electron
Microscope (SEM):
• Slower cooling rates result in the increased formation of the Ag3Sn and Cu6Sn5 intermetallics. These will form
both in the bulk solder as well as at the pad – solder interface. Faster cooling rates inhibit the growth of these
intermetallics.
• Aging results in joint fatigue thus reducing the shear strength of the joint. This is the result of solder migration
and increased intermetallic thickness at the solder – pad interface.
• Time above Liquidus impacts the intermetallic thickness at the solder – pad interface.
• Faster cooling rates result in stronger joints as observed in those samples with a Cu-OSP board finish. The
opposite trend is observed for samples assembled on Imm Sn and ENIG board finishes.
• Failure modes for the shear test depended on board finish. Imm Sn samples failed by pad lifting while ENIG
and Cu-OSP failed by cracking in the bulk solder.
• Profile type influences joint quality but is greatly dependent upon all reflow process parameters,especially flux
– profile compatibility.

Flux management methods for reflow soldering have been debated for years. Current data suggests that multi-stage
filtration systems offer many benefits,particularly in dealing with the byproducts of new solder/flux paste
formulations. High system efficiencies result from targeting all areas of the oven,using multiple scrubbing units and
developing filtration units to capture volatiles released during the reflow process. These systems are also energy
efficient,require minimal facility resources and virtually operate maintenance-free by incorporating self-cleaning
cycles. This paper discusses these advantages in detail and shows the low cost of ownership that multi-stage flux
filtration systems can provide. The presented data is based on actual production performance within a mediumtohigh
volume reflow operation.