The popularity of low voltage technologies has grown significantly over the last decade as semiconductor device
manufacturers have moved to satisfy market demands for more powerful products,smaller packaging,and longer battery life.
By shrinking the size of the features they etch into semiconductor dice,IC manufacturers achieve lower costs,while
improving speed and building in more functionality. However,this move toward smaller features has lead to lower
breakdown voltages and increased opportunities for component overstress and false failures during in-circuit test.
The chief reason is that testers designed for boards that traditionally operated with a power supply voltage of 5V are still
being used on new generation ICs,which operate on 2.5V,1.5V,or even 0.8V. These traditional in-circuit testers often do
not have the accuracy,safety,and reliability features that are required to test low voltage technologies.
This paper discusses the challenges of performing powered-up vector testing of low voltage technologies on traditional incircuit
testers and describes the safeguards that are necessary to ensure that test vectors do not violate the increasingly tight
specifications of low voltage parts.
It also describes the in-circuit test features that are most important for testing low voltage technologies: independently
programmable,high accuracy driver/sensors; real time dynamic backdrive current measurement,programmable backdrive
control,specialized digital controller; and multiple level digital isolation.

Evaluation of printed wiring boards (PWBs) for thermal reliability during assembly and rework operations by Thermal
Mechanical Analyzer (TMA) “T-260” testing has been an accepted practice for many years. Test procedures are specified in
IPC-TM-650-2.4.24. It is common to see finished PWB T-260 requirements of 2 minutes or greater. In general PWBs
produced using FR4 substrates pass this requirement. Recently,however,T-260 results from PWBs of thickness greater than
8mm,produced with high Tg FR4 substrates,using industry standard TMAs supplied by two manufacturers have
delaminated in less than 2 minutes. Samples 4mm thickness or less produced with the same substrate materials consistently
survive. Significant variation of the measured glass transition temperature (Tg) has also been observed. Tgs measured by
TMA for the very thick PWBs are significantly lower than those measured for thinner PWBs.
When T-260 samples are examined following the testing,the delamination is always observed to be on the top few layers of
the PWB. This is true even for thin samples. The sample is significantly degraded at the top surface with the resin bubbled
and charred while the bottom of the PWB resting on the sample stage is not significantly different from the pre-tested sample
(Figure 1). These results suggest that the thickness of the sample and instrument used are influencing the T-260 time to
delamination. To better understand the influence of the sample thickness and instrument set-up on T-260 and Tg results
several studies were performed.

Non-destructive testing during the manufacture of printed wiring boards (PWBs) has become ever more important for
checking product quality without compromising productivity. Using x-ray inspection,not only provides a non-destructive test
but also allows investigation within optically hidden areas,such as the quality of post solder reflow of area array devices (e.g.
BGAs,CSPs and flip chips). As the size of components continues to diminish,today’s x-ray inspection systems must provide
increased magnification,as well as better quality x-ray images to provide the necessary analytical information. This has led to
a number of x-ray manufacturers offering digital x-ray inspection systems,either as standard or as an option,to satisfy these
needs. This paper will review the capabilities that these digital x-ray systems offer compared to their analogue counterparts.
There is also a discussion of the various types of digital x-ray systems that are available and how the use of different digital
detectors influences the operational capabilities that such systems provide.

The behavior of BGA solder joints under dynamic loads has become more significant in recent years. This work explored test
methodologies for solder joint failure evaluation under dynamic loads. The objectives of this study were
• To evaluate the behavior of solder joints under a variety of strain rates as seen during both 4 point bend testing and
mechanical shock
• To try to quantify the shock levels present at solder joint failure to support ongoing solder joint reliability modeling
efforts
A test coupon and fixture developed for the four point bend test setup is reviewed. Testing was performed under different
strain rates and the results showed clearly that the solder joint failure is strongly strain rate dependent under mechanical
bending load on boards. This implies that the practice of low strain rate (quasi-static) test with dynamic amplification factor
for solder joint failures,such as the four point bend test,is not sufficient for dynamic prediction due to over-estimation of the
joint strength at low strain rate range. The finite element analysis revealed that the strain rate dependent material properties of
the solder play the key role of solder joint failure threshold.
Comparison of strain rates between the four point bend test and a more traditional mechanical shock test were made on a
desktop motherboard. These tests showed that the strain rate is much higher during the mechanical shock test than that seen
during the bend testing. A variable mass shock test and an incremental shock test procedure were developed to evaluate BGA
solder joint shock failures. In-situ solder joint continuity was monitored during the shock events. The results of these tests
give a good estimate of motherboard BGA solder joint robustness.
In addition,a shock test fixture and a test vehicle were developed similar to those used in the four point bend test. By using
the incremental shock test procedure outlined above,the acceleration level (G-level) at solder joint failure was obtained. This
information was input to the finite element dynamic analysis,the overall behavior of the test coupon during shock was
simulated and the solder joint failure force obtained. Failure analysis of the shocked boards revealed that PCB pad/FR4
disbond was the dominant failure mode for the tested eutectic solder joints. In addition,fracture at IMC between pad and
solder on the package side was observed.
In summary,a set of test and modeling methodology for solder joint reliability evaluation under dynamic load was developed
and validated and some recommendations are made as to the applicability of these test methods.

Industry cost control pressures and technology drivers demand more powerful 3D AOI machines for control of solder paste
printing. Here is an inside look at the factors potential purchasers of these systems should take into consideration.

The electronic industry trend of smaller component packages and tighter spacing has put greater demands on manufacturing
for process control and product verification. Defects must be caught earlier in the process to provide feedback to the process.
Large quantities of manual rework on components that can barely be seen or handled put too much strain on rework
operators. Manual inspection as a means of process control has become less effective by these factors causing fatigue,
missing defects,and reduced thru-put. In-circuit test as a means of product verification also has issues because it requires
space on the printed circuit board for test pads. Automated Optical Inspection (AOI) is an increasing popular method to
address process control and product verification. Faster processors with higher density memory devices have enabled image
capture and processing to become a viable alternative. This paper will detail the methodology used to select and evaluate AOI
systems as an alternative process control and product verification tool.

Conductive adhesives (CAs) have been an important problem-solving class of assembly materials for decades,but primarily
as die attaches products,ever since they replaced metallurgical systems. Renewed and intensified interest in lead-free (L-F)
electronic assembly has moved CAs back into the spotlight. Although lead-free solders,both new and very old,have been
studied for several years,they are a partial solution at best. One may conclude that: (1) lead-free alloys do work,(2) there is
no drop-in replacement,and (3) their higher processing temperatures are detrimental.
The expected increase in soldering temperatures is cause for concern over potential damage to laminates,packages and some
semiconductors. New alloys will also require modifications to some soldering equipment. High temperature L-F processing
could bring significant and costly “collateral damage”. BGAs could require pre-bakes,PWBs may degrade and optoelectronic
components could fail or suffer reduced lifetimes. The next -generation sub-micron CPUs,with evolving low k dielectric
layers,may not tolerate excessive soldering temperatures. These problems may be "fixed",but not truly solved. Cost-adding
work-around strategies include higher performance laminates,upgraded molding compounds and in-process cooling,but
considerable time and money will be needed to re-engineer,re-test and re-qualify.
Polymer Solders (Conductive Adhesives) have provided a good alternative for temperature-limited assembly for decades.
These well-tested joining materials process like solder on the same equipment. Fluxing or cleaning is never required. And
they run at more than 100 degrees lower than solder. Both reflow and batch ovens can be set at 110oC to 150oC to quickly
harden these polymer systems. Adhesives are used to assemble SMTs to a variety of systems including medical devices,
memory modules,and computers. Chances are that LEDs in your business phone and ink jet printer are assembled with
conductive adhesives. Perhaps the flip chips driving your flat panel display are adhesively bonded.
This paper will compare Polymer Solders to L-F alloys to show limitations and advantages for the technology. There are
important restrictions,especially lower mechanical strength revealed in the drop test. But adhesives research has been
energized after years of simple incremental improvements and fresh new approaches will be summarized that include
intrinsically conductive polymers (ICP) and Nanomaterials.

Quantifying SMT adhesive dispensing performance has typically been attribute analysis via a microscope. Individual
adhesive deposits were inspected for strings or tails,extra dots,missing dots and dot diameter. These attributes were typically
measured with an eyepiece reticule and a light microscope. This tedious and subjective method has been replaced by a highly
quantitative,extremely quick automated method using the vision engine of a real time X-ray. The details of this method are
discussed as well as practical applications for glue benchmarking and dispense parameter fine-tuning. The output of this
method includes dot diameter,spherocity and area. Adhesive deposit consistency of both dispensing and printing are
compared using this novel measurement method.

Higher I/O Ball Grid Arrays (BGAs) are high speed,high pin count,and high performance array packages. These BGAs are
also more complex in structure than “standard” BGAs and are generally targeted toward network and server class products.
Higher I/O BGAs follow an industry trend identified on multiple industry roadmaps and vendor data sheets. Today,
component manufacturers are introducing higher I/O BGAs into the market.
Along with the speed and performance benefits,these higher I/O BGAs also incorporate additional manufacturing and
reliability challenges. For example,these larger sized BGAs are considered more susceptible to component warping and large
temperature deltas during reflow because of their large size. This paper will discuss overcoming these challenges in regards
to one new type of high I/O BGA: a 2577 I/O,1.0mm ball pitch,52.5 x 52.5mm body size,PTFE carrier,Flip Chip BGA
(FCBGA).
The main objective of this study is to describe and discuss the component characterization,test vehicle design,assembly,
rework,and accelerated temperature cycling testing that were done with the 2577 I/O Hyper BGATM. Component warpage,
overcoming large temperature deltas during reflow,reworking techniques,and analysis of the accelerated temperature
cycling will be discussed.
Another objective of this study is to discuss process considerations for assembling and reworking the 2577 I/O Hyper
BGA.™

With the function of today’s electronic devices become more and more complicate,the high I/O flip chip ball grid array
package (FCBGA) is used more popularly in recent years. The FCBGA package is always subjected to thermal loading when
in use. For accelerating the reliability access,the thermal effects is often checked by using bend tests instead of the time
consuming thermal cycling tests. However,most of the bend tests are performed at room temperature. But in reality,the load
is applied at the state of elevated temperature. The study will investigate the thermal reliability issue by bend test with
consideration of temperature effects.
In the study,the reliability of FCBGA is explored by a four-point bend test executed at different controlled temperature. The
test vehicle is put in a heated chamber and the resulting daisy chain resistance and strains are monitored to check its failure.
Both the monotonic and cyclic tests are used. However,during the monotonic bend test,the failure mode is found to be the
delamination of the heat spreader instead of the solder balls cracking. It is then conducted with room temperature only by
checking the failure mode of heat spreader delamination. The cyclic bend test was done with various temperature loading
conditions. Based on the results from the monotonic test,it is then reduced the loading so that the heat spreader failure won’t
occur prior to the solder ball fatigue failure is observed. The strain gages are mounted near the component corner to get the
strains of the test board when under bending. A data logger records the daisy chain resistance simultaneously during the test.
The component failure is detected with a self-written program by judging when the failure resistance of the daisy chain is
large than 20% of its initial resistance.
The test results at various temperature showed that the component life cycle is reduced with the increase of the temperature
during the cyclic bend test when under a fixed maximum deflection setting. If tested at room temperature by varying the
maximum deflection,the component life cycle is also reduced with the increase of the maximum deflection in the cyclic bend
test. Through the fitted curve of all these test data,it is then possible to get relating equations among the variables of
temperature,deflection,and life cycle. An extra test is conducted to verify these deduced equations with an error of six
percent approximately. The methodology can be used to predict the component life cycle at elevated temperatures based on
the test results at room temperature.