Solder is used in polyimide-based flexible circuits for interconnect applications. But it cannot be used with polyester
and epoxy based substrates because of the low temperature tolerance of these substrates. Conductive adhesives offer
the best alternative for this application because they can be processed at lower temperature. Other advantages
provided by conductive adhesives are lead-free,no flux/no cleaning,and fine pitch application. There are two types
of conductive adhesives in the market. Type I is the traditional conductive adhesive used predominately with
expensive components on ceramic substrates. These high cost components are terminated with noble metals such as
Au,Pd or Pt that offer no corrosion concern under 85°C/85%RH. To reduce the cost of components,eutectic solder
or high tin solder is used as termination metal. Unfortunately,these non-noble metals are subject to corrosion that
causes unstable electrical performance when the type I conductive adhesives are used as the interconnect. This
shortcoming triggered the development of type II "solder alternative" conductive adhesives that exhibit stable
contact resistance with Sn/Pb-terminated components under various environments including 85°C/85%RH. This
case study focuses on the development of an advanced type II conductive adhesive and its use as an interconnect on
polyester-based flexible circuits. Adhesives are applied by high-speed stencil printing followed by low temperature
cure for a short time. Stable electrical performance and adhesion performance with Sn/Pb terminated components
are demonstrated under several environmental conditions. The effects of application and processing conditions on
adhesive performance are typically overlooked while making adhesive selection. This study includes the results of
the electrical and mechanical performances under various curing profiles and various stages of stencil printing.

Adhesiveless copper on polyimide substrates are used extensively for high density,flexible circuit applications. A
typical construction includes the polyimide substrate,a thin vacuum deposited metal tiecoat,a copper seedcoat,and
an electrodeposited copper layer. One or both sides of the polyimide may be metallized,and very thin copper can be
provided in order to facilitate formation of fine-line features. Since metal layers are direct deposited,not laminated,
the copper profile and bond treatment typically associated with copper foils are not present between metal and
dielectric. Adhesion between metallization and dielectric is achieved by performing plasma pretreatment prior to
metallization,and by the selection of a suitable tiecoat metal. Tiecoat metal is especially important to minimize
adhesion losses associated with circuit processing and subsequent environmental exposures. In this work,
characteristics of copper on polyimide substrates with nickel-chromium tiecoat are investigated. Adhesion,before
and after exposure to elevated temperature,pressure cooker conditions,and gold plating,is determined as a function
of tiecoat thickness. Additional characteristics,including etching performance and a practical example of using the
material to manufacture a high-density circuit,are discussed.

Failure analyses of the leadfree and SnPb solder joints of high-density packages such as the PBGA (plastic ball grid
array) and the CCGA (ceramic column grid array) soldered on SnCu HASL (hot-air solder leveling) ENIG
(electroless nickel-immersion gold) or NiAu,and OSP (organic solderability preservative) Enteek PCBs (printed
circuit boards) are presented. Emphasis is placed on determining the failure locations,failure mode,and IMC
(intermetallic compound) of these high-density packages’ solder joints after they have been through 7500 cycles of
temperature cycling. The present results will be compared with those obtained from temperature cycling and finite
element analysis.

Temperature cycling test and statistical analysis of various high-density packages on PCBs with SnCu HASL,NiAu,
and OSP finishes are investigated in this study. Emphasis is placed on the determination of the life distribution and
reliability of the lead-free solder joints of these high-density package assemblies while they are subjected to
temperature conditions. A data acquisition system,failure criterion,and data extraction method will be presented
and examined. The life test data is best fitted to the Weibull distribution. Also,the sample mean,population mean,
sample characteristic life,true characteristic life,sample Weibull slope,and true Weibull slope for some of the highdensity
packages are provided and discussed. Furthermore,the relationship between the reliability and the
confidence for a life distribution is established. Finally,the confidences for comparing the quality (mean life) of
lead-free solder joints of high-density packages are determined.

The lead-free solder-joint reliability of the high-density packages,256-pin PBGA (plastic ball grid array),388-pin
PBGA,and 1657-pin CCGA (ceramic column grid array),on PCB (printed circuit board) subjected to temperature
cycling is investigated. Emphasis is placed on the determination of the creep responses (e.g.,stress,strain,and strain
energy density) of the lead-free solder joints of these packages. The lead-free solder is assumed to obey the
Garofalo-Arrhenius creep constitutive law. The results presented herein should be useful for a better understanding
of the thermal-mechanical behaviors of the lead-free solder joints in these high-density package assemblies.

The High Density Packaging Users Group (HDPUG) has conducted a substantial study of solder joint reliability of
high-density packages using lead-free solder. The design,material,and assembly process aspects of the project are
addressed in this paper. The details on the design are addressed from the aspect of the considerations taken in the
design process,and not just the design details. The components studied include many SMT (surface mount
technology) package types,various lead and PCB (printed circuit board) finishes and paste-in-hole assembly. The
assembly process addresses lead-free assembly process,inspection and analysis of these boards and packages. Leadfree
transition issues are also discussed.

With the advent of hard die coated microelectronic assemblies; the ability to perform visual inspections for quality control
and failure analysis has been seriously hindered. Analysts have had to utilize X-ray inspection,cross sections,and chemical
decapsulation to discover what defects are hidden under the hard die coat. X-ray analysis cannot see aluminum bond wires or
areas of delamination on and under the electronic components and substrates. Cross sections and chemical decapsulation
techniques are destructive and will alter the physical condition and electrical operation of the assembly.
Using an acoustic microscope,recent analytical work has been able to identify individual components involved in high
voltage electrical overstress events,evaluate silver epoxy die attach dispense patterns,inspect epoxy bleed out for shorting
between components,detect wire sweep in aluminum bond wires,and locate fused copper traces within the top three layers of
a printed wire board assembly.
This presentation will discuss the imaging requirements through hard die coated assemblies,the physical process variations
and failure mechanisms which may be present,and the acoustic microscopy techniques which can be used to see through the
hard die coat and successfully document them.

During the last years Flip Chip Technology has been widely accepted as a means for maximum miniaturization of
microelectronic assemblies. As an example the use of Flip Chips in advanced products as cellular phones,GPS
devices and in medical applications for pacemakers can be named.
These Flip Chip assemblies have proven to yield at least comparable reliability as standard SMT packages with a
reduced package or product volume resp.. To achieve this reliability it is necessary to carefully select the materials
and the process parameters.
At Fraunhofer IZM previous investigations on processibility and reliability have been updated using state of the art
Flip Chip Underfillers. Motivation for the investigations is,that for industrial use it is necessary to have defined
encapsulation process parameters that guarantee a robust process without internal flaws. As these flaws often result
from non-optimized material parameters an easy way to detect critical material combinations or assembly geometry
was investigated. The investigations performed correlate calculated flow rates to results from in situ flow
measurements. Here the direct flow visualization using video equipment (e.g. flow front fingering) was combined
with acousto-microscopic visualization of material inhomogeneities (e.g. comet-like filler agglomerations).
Furthermore the influence of different substrate base materials,solder mask types and geometries on five different
underfill materials is considered and related to material flow and filler agglomerations as detected and visualized by
acoustic microscopy. For further material evaluation concerning the reliability of the selected material systems
accelerated aging tests are performed. During process setup and accelerated ageing tests the use of Acoustic
Microscopy allowed the precise detection of material imperfections as variations in filler distribution or voiding. As
these internal flaws are critical to Flip Chip reliability it is crucial to avoid such effects.
Derived from these investigations a material ranking of the underfillers used was done and material systems suited
for the assembly of reliable Flip Chip packages have been identified.

The Information and Electronic Warfare Systems
business of BAE SYSTEMS Information and
Electronic Systems Integration,Inc. (“BAE
SYSTEMS IEWS”),a subsidiary of BAE SYSTEMS
North America,is involved in the manufacture of a
wide range of military products for the government.
One of the manufacturing focus factories within the
IEWS group deals strictly with the production of
Circuit Card Assemblies (CCA). The CCA focus
factory performs the hardware build for programs
internal to the company and supports a contract
manufacturing organization that seeks work from
outside the company as well. To that end,the CCA
Focus factory is best characterized as a low volume,
high mix manufacturing environment. Given the type
of business in which the CCA focus factory is
engaged,areas of improvement are continually being
identified. One such area pertains to the management
of Moisture Sensitive Devices (MSD). With the help
of Cogiscan Inc. of Quebec,Canada,a solution to
this industry wide problem of effectively managing
MSDs has been addressed.

All areas of manufacturing worldwide are impacted
by the lead free initiative; none more than the reflow
process. The higher melt temperatures and soak
duration of leadless solder formulas require a change
in the way reflow management is handled. Time
above liquidous,grain structure,and board exit
temperatures all require tight definition within a
shrinking process window. Also,until all components
and boards are 100% lead-free,we will be working in
mixed territory. Lead-free solders combined with
components and/or boards that have lead bearing
finishes will definitely impact the reflow formula in
contradictory ways. Since every board configuration
is different and there are many lead free solder
formulas to choose from,this means every assembly
could be completely unique. Because of this,there is
no magical panacea; no standard simple profile that
will fit all assemblies and all leadless solder
formulas. You will have to basically “know your
stuff” and only good use of statistical process control
(SPC) will allow you to do this. Hopefully,the
information in this presentation will help you
understand the why and wherefore of SPC in lead
free SMT reflow; and introduce you to
methodologies,new tools and software that will
make a tight SPC reflow program relatively fast and
simple to both understand and implement.