Results from a National Electronics Manufacturing Initiative (NEMI) project,formed to improve aspects of fiber optic fusion
splicing,are reported. The focus of this paper is ultra low loss splicing for telecommunications product assembly,with
typical loss of <0.05 dB per splice for standard SMF-SMF. A detailed review and gap analysis of available industry
standards,relevant to splice loss acceptance criteria and loss test procedures,revealed the standards are generally inadequate
for low loss splicing. Various project participants using different equipment and procedures performed fiber preparation,
splicing,splicer loss estimation,and actual loss measurements. Sets of data spanning three loss ranges,obtained with three
measurement methods were compared using an industry standard gage repeatability and reproducibility (GR&R) analysis. A
subsequent comparison of loss measurement set-ups based on a cut-back method for dissimilar fiber (SMF-EDF) splices
showed significant directionality in some cases,and root cause was identified using a round robin approach. A future activity
of this project will be to draft a new loss measurement standard for dissimilar fiber splices,to address an important gap in the
current standards.

When we think of optoelectronics in the USA,we automatically think of telecom applications. These fueled huge growth at
the turn of the millennium,and even after the bubble burst in 2001-2,telecom represented a significant business and the
future of telecommunications. Meanwhile,a number of consumer,medical,automotive,and other applications have
developed rapidly,ranging from imaging,displays,biological analysis,and video gaming to lighting. Worldwide nontelecom
optoelectronics is now more than 50% of the optoelectronics market. Many issues being tackled by organizations,
such as NEMI,are relevant to this area where low-cost packaging has critical technical demands. This paper reviews these
applications,the packaging and assembly challenges they present,and the standardization opportunities worldwide.

A cyclic board-bending technique has been developed to ensure a reproducible multiaxial stress state at the Chip
Size Package (CSP) solder fillet. Mechanically stressing the package serves as a valuable tool to quickly determine
and provide feedback on design and assembly weaknesses,20-30 times faster than less comprehensive data can be
obtained using temperature cycling.
The bending technique allows controlled strain application rate,peak strain,and dwell time as experienced by a
population of ten components per each of ten board positions. Board surface strain for each of these positions is
characterized using strain gages. The plastic,transition,and elastic regions of the PCB are determined
experimentally according to peak strain and correlated with failure mechanism. Two main failure modes are made
manifest through Weibull techniques: board-level failures (plastic board response region),and solder joint failures
(elastic board response region). Cyclic bending results compare different CSP architectures thus demonstrating the
utility of the test technique.

The miniaturization trend in electronics has proliferated the use of Chip Scale Packages (CSPs) in electronics assembly. CSPs
used in portable devices are subjected to harsh mechanical and thermal conditions and underfill provides a dramatic
improvement in their thermo-mechanical reliability. This paper provides a comparison of thermo-mechanical reliability
performance of CSPs underfilled using different methods such as capillary underfill and corner-fill. The evaluation is based
on drop test,liquid-to-liquid thermal shock (LLTS) and air-to-air thermal cycling (AATC).

Chip scale packages (CSPs) are widely used in portable electronic products where there is also a growing trend to lead free
assembly. Many CSP designs will meet the thermal cycle or thermal shock requirements for these applications. However,
mechanical shock and bending requirements often necessitate the use of underfills to increase the mechanical strength of the
CSP-to-board connection. Three underfill options compatible with lead free assembly have been evaluated: capillary
underfill,fluxing underfill and corner bond underfill. CSPs with eutectic Sn/Pb solder were used for control samples. Without
underfill,lead free and Sn/Pb eutectic drop test results were comparable.
Capillary flow underfills,dispensed and cured after reflow,are commonly used in CSP assembly with eutectic Sn/Pb solder.
With capillary flow underfill,the drop test results were significantly better with lead free solder assembly than with Sn/Pb
eutectic.
Fluxing underfill is dispensed at the CSP site prior to CSP placement. No solder paste is printed at the site. The CSP is placed
and reflowed in a standard reflow cycle. A new fluxing underfill developed for compatibility with the higher lead free solder
reflow profiles was investigated. The fluxing underfill with lead free solder yielded the best drop test results.
Corner bond underfill is dispensed as four dots corresponding to the four corners of the CSP after solder paste print,but
before CSP placement. The corner bond material cures during the reflow cycle. It is a simpler process compared to capillary
or fluxing underfill. The drop test results with corner bond were intermediate between no underfill and capillary underfill and
similar for both lead free and Sn/Pb eutectic solder assembly.
The effect of aging on the drop test results with lead free solder and either no underfill or corner bond underfill was studied.
This test was to simulate drop performance after the product has been placed in service for some period of time. There was
degradation in the drop test results in both cases after 100 and 250 hours of storage at 125oC prior to the drop test.
The assembly processes,drop test results and failure analysis are presented.

The ever-increasing use of high frequency in high density interconnect (HDI) assemblies,combined with the worldwide
move toward lead-free manufacturing,has initiated a closer scrutiny towards effective flux removal processes. Since
adequate climatic operating conditions cannot always be assumed,system signal integrity maybe vulnerable to failure
through induced capacitive effects of hygroscopic activator residues. Furthermore,such contamination,particularly with the
new lead-free solder paste formulations,is no longer-detectable by ion-equivalent measurement alone.
Most failures of electronic components in humid environments are caused by electrochemical migration and corrosion
induced leakage currents. In this paper,the origins and effects of such failure mechanisms are examined. In addition,the
influence of alloy types,with particular reference to lead free formulations,is also discussed. The critical importance of
contamination free surfaces in high frequency circuits is outlined. Finally,different methods to determine climatic reliability
are discussed,in which a new and innovative test method is described.

Lead-free alloys under consideration have physical properties,which may directly impact industry standard electronic assembly
cleaning processes. The purpose of this study is to evaluate how the use of nitrogen versus non-nitrogen reflow atmospheres affect the
cleanability of flux residue from RMA,synthetic and water-soluble surface mount solder paste residues.
The designed experiment evaluated commercially available lead-free solder paste products and industry standard cleaning materials.
The cleaning evaluations were conducted in a controlled application lab while using thermally profiled reflow conditions and
cleaning equipment. The response variables used will be qualitative visual inspection of white residue and solder bump appearance.

Conductive Anodic Filamentation is a subsurface failure mode for woven glass reinforced laminates (FR4) materials,where a
copper salt filament allows bridging between via walls or other copper conductors. In this study FR4 laminates,in the form of
high via density multi-layer test circuits,are exposed to different manufacturing conditions and assessed for resistance to
Conductive Anodic Filamentation (CAF). CAF performance was assessed using high temperature and humidity conditions to
promote failures,with a voltage applied across adjacent vias. By application of a range of voltages and via geometries a
performance map for laminates can be obtained to compare materials for performance. The changes due to exposure of
laminate to lead-free temperatures and other processing steps are then examined using the technique.

Various test methods are used to characterize the PCB plated-thru-hole reliability. One such method is the Interconnect Stress
Test (IST). The results from this test are often used to qualify PCB materials and/or fabricators. This paper will discuss how
certain statistical analysis techniques may be used to decipher the results,and predict capabilities of PCB materials and/or
processes.

The selection and use of solder joint modification configurations for printed wiring assemblies has traditionally been a design
specific activity. The implementation and use of a standardized set of solder joint modification configurations on an industrywide
basis would be cost effective and promote industry consistent modification practices. A set of 14 commonly used IPC
Class 3 modification configurations were selected for investigation. Thermal cycle testing was chosen to evaluate the solder
joint thermal cycle fatigue reliability of the configuration set. A total of 1,972 thermal cycles using a -55ºC to +125ºC recipe
in accordance with the IPC-9701 guidelines were completed. Failure analysis and photo-documentation were conducted
characterizing modification configuration solder joint geometries and wetting angles. The investigation
results/recommendations were disseminated to the IPC-A-610 and IPC-7711/7722 specification committees for potential use.