Teradyne,Inc. has been involved with Conductor Analysis Technologies,Inc. (CAT Inc.) for over 4 years and the
IPC D-36 Subcommittee for over 2 years. This paper describes the initial motivation for selecting "CAT" test
vehicles and testing and the project involvement. We relate some of the findings from the latest test project and
discuss some of what we have learned. This paper shows a few of the ways that CAT/IPC D-36 testing has been
used to determine supplier process capabilities,technology readiness,and design feature parameters. We provide an
overview of how supplier management utilizes the test results to evaluate existing and potential suppliers; to drive
for quality improvements; and to align parts to suppliers. Last we comment on the strengths and weaknesses of the
current state of the program from Teradyne's perspective.

Benchmarking of industry fabrication capability,feature tolerances and material property variation is essential to
aligning product requirements and industry capability. Statistical based characterization of feature tolerances and
material properties are being used to optimize system and silicon designs. Assessment of industry capability is used
to validate process improvements and ensure alignment with product.

New component packaging formats create the need for greater production process stability,reproducibility and
precision. This leads to a growing demand for process control solutions.
As manufacturers set zero-defect goals,process control solutions have been developed,which are going beyond
defect detection towards defect prevention. In order to reach those zero-defect goals it is necessary to develop a
comprehensive quality assurance (QA) strategy. Part of this strategy must be,to observe and continually correct the
different processes,which build the SMT process. The use of AOI (Automated Optical Inspection) systems plays a
central role in most of those strategies.

Dramatic changes are underway in the computer,telecommunication,automotive,and consumer electronics
industries. Changes that demand common and pervasive requirements for active assemblies such as: (1) ultra-low
cost,(2) thin,light,and portable,(3) high performance,and (4) diverse functionality. The biggest bottleneck to
achieving these is typically not the ICs but rather the electronic packaging. System in Packaging (SIP) is a
packaging solution that provides the high performance and high flexibility package architectures that meets the
system demands.
System in packaging provides a unique packaging solution allowing designers to tailor high density and high
performance electronic systems into application specific packages at costs far less than custom,system on a chip
solutions. Depending on their application environment,SIPs provide for high levels of integration between
interconnect levels,passive elements,optoelectronic,digital,and RF functions. To achieve this,the predominant
chip to package interconnect strategies are die attach with wire bonds and flip chip interconnects on multi-functional
high density interconnect substrates. Of particular interest are flip chip solutions as the need for high I/O’s,high
performance and high speed has moved to the forefront in customer requirements. Flip chips provide increased I/O
counts,improved electrical performance,reduced cost,and smaller size.
In this paper flip chip interconnect technology is reviewed with particular emphasis on design for manufacturing for
system in packages to insure high yield production. Factors such as substrate design guidelines,bump design
guidelines,under bump metallization selection,interconnect materials selection,and underfill selection are
discussed. In addition,reliability requirements and test methods are also reviewed. A case study on flip chip blue
tooth module processing is presented.

To successfully navigate the transition from an entrenched Pb-based electronics manufacturing model to a fully integrated Pb-free manufacturing operation will require significant and coordinated modifications to many elements of currently operating electronics manufacturing organizations. Starting with the fact that no “drop-in” replacement for eutectic tin (Sn) - lead (Pb) solder exists,the demands of Pb-free production will alter most facets of the manufacturing organization,from higher temperature processing with more expensive Pb-free alloys,to specifying component and laminate requirements able to tolerate the new constraints,to formulating new approaches for testing,inspection and quality control,to understanding the unknown reliability of Pb-free products. The elimination of Pb from electronic products will impact companies across the entire organization,not just at the manufacturing level. This will include product designers,component engineers,purchasing and quality assurance departments,
sales and marketing groups,material vendors,assembly equipment suppliers,original equipment and contract manufacturers,and recyclers. Clearly there is no shortage of work that needs to be done to place our understanding of Pb-free electronics production on the same level as the Pb-based counterpart. This paper discusses the comprehensive experimental approach that Cookson Electronics Division has taken to address the conversion to an integrated Pb-free manufacturing operation. The initial focus has been on materials compatibility for Pb-free processing using statistically based experimental designs. The study investigates compatibility between several Pb-free alloys,board and lead finishes,and flux types for both wave and paste/reflow soldering,including extensive reliability testing of the Pb-free assemblies. The statistical methodology and the results from the study will provide guidance for the implementation of successful and reliable Pb-free processing and serves as a model for how to establish a dedicated Pb-free electronics manufacturing operation.

Optical connectors are used to connect optical devices to other optical devices or systems. The presence of these optical connectors makes it possible to switch conveniently from one device or system to another. However,each connection introduces a certain amount of insertion and return loss that can impact performance. Such losses are particularly critical at high-speed transmission. Many applications can only tolerate less than 0.1dB loss for a connection. This paper will examine the challenges that manufacturers and users face as they manufacture and/or use fiber optic connectors. This paper will also discuss the factors that influence the optical performance (insertion loss,return loss,etc.) of fiber optic connectors. The losses due to process problem,contamination,and the type of adapters used for connection will be considered.

Two new electrolytically plated lead-free surface finishes,satin bright tin on nickel and palladium-cobalt on nickel followed by gold flash coating,are evaluated for their wettability,bond strength,and voiding performance,and are compared with electrolytic nickel gold and OSP. Results indicate that Ni-Sn,although being sensitive to aging,and
reflow atmosphere,solder alloy type,and variation in flux chemistry,it is the highest in wettability,one of the highest in lap shear strength,and the lowest in voiding. It performs better under long profile. The high sensitivity may be attributed to the relatively high reactivity of tin. Under most instances,the soldering performance is comparable with or better than the references OSP and Ni-Au. Ni-PdCo-Au is poor in wettability,fairly low in lap shear strength,and high in voiding. However,it is fairly stable,and its soldering performance is not sensitive to profile length,reflow atmosphere,aging treatment,and flux chemistry. It does seem to be sensitive to Bi-containing alloy in terms of voiding and lap shear strength. OSP is the poorest in wettability,but one of the best in lap shear strength. It performs best under long profile. It is not sensitive to reflow atmosphere,slightly sensitive to alloy type,but is very sensitive to aging and flux chemistry. Ni-Au is good in wettability and voiding,medium in lap shear strength. It is not sensitive to aging,flux chemistry,reflow atmosphere,slightly sensitive to alloy type and profile length.

Lead-free soldering technology is still in its infancy with technical and cost issues posing major challenges for the industry. It is expected that soldering in a nitrogen atmosphere might overcome some of the technical barriers and provide soldered products comparable to those using conventional lead-containing materials processed in air. But quantitative data regarding the soldering behaviour of lead-free solders under various atmospheres are sparse. Hence this work was undertaken to build on the previous studies of the solderability of SnAgCu alloys under a range of residual oxygen levels between 10 ppm and 21%. The current work extends the study to other lead-free solders,SnCu,SnZn and SnAgBi,in atmospheres containing as little as 10 ppm oxygen
at superheats from 20 to 60 degrees. The results clearly demonstrate the benefit of inerting for these solders. Apart from widening the process window,it can reduce oxidation and improve solderability of lead-free systems to a level close to that of SnPb. In many cases the addition of an inert atmosphere during lead-free soldering can
allow a ~30ºC reduction in soldering temperature AND give the same solderability as using SnPb in air. Inerting is especially beneficial at low soldering temperatures or for challenging assemblies such as multi-layer boards. Whilst in the case of soldering with SnZn alloy inerting to < 100 ppm was essential,for SnCn and SnAgBi solders inerting only to <5,000 ppm oxygen offered significant benefits in wetting. For many of the challenging conditions and poor solderability associated with lead-free solders,nitrogen offers an attractive alternative to stronger fluxes and higher processing temperatures.

Conductive anodic filament (CAF) formation is a failure mode associated with electronic circuits which operate at high voltage gradients and which are stored under high humidity conditions. Certain soldering fluxes and hot air solder leveling (HASL) fluids enhance this failure mechanism. Research was conducted to examine the effect of three different conformal coatings in reducing the incidence of CAF associated with a variety of water-soluble flux formulations. The fluxes chosen contained a water-soluble vehicle as 20 wt% in isopropanol. Some formulations contained 2wt% HCl,HBr,and/or monoethanolamine. The conformal coatings tested were acrylic (Humiseal 1B73),silicone (Humiseal 1C55) and parylene C. IPC B-24 test boards were coated with the flux,reflowed to create the thermal cycle,and then cleaned. Some boards were conformally coated and others were not. All test boards were exposed to SIR testing at 85oC,85% RH and 100V bias for 28 days. This paper will report on the electrical results,as well as the number of CAF observed with and without conformal coating. It will also discuss visual observations of dendrites on boards with/without conformal coating.

The formation of underfill voids is an area of concern in the low cost,high throughput,or “no-flow” flip chip assembly process. This assembly process involves placement of a flip chip device directly onto the substrate pad site covered with pre-dispensed no-flow underfill. The forced motion of chip placement causes a convex flow front to
pass over pad and solder mask-opening features promoting void capture. This paper determines the effects of substrate design on the phenomena of underfill voiding using the no-flow process. A full-factorial design experiment analyzes several empirically determined factors that can affect void capture in no-flow processing. The substrate design parameters included pad height,solder mask opening height,pad/solder mask opening separation,and pad pitch. The process parameters include chip placement velocity and underfill viscosity. The process robustness is measured in terms of the number of voids created during chip placement,and is further analyzed for the location and any visible modes of void formation. The goal of the work is to determine improved substrate designs to minimize voiding in flip chip processing using no flow underfills.