Efforts to reduce high frequency signal losses associated with dielectric materials have driven development and
commercialization of more cost effective low loss laminate materials. These developments have been facilitated by the use of
a variety of standardized dielectric test methods.
As dielectric losses are reduced,the relative contribution of conductor materials to overall loss increases. In order to better
understand the implications of conductor material and surface finish choices,efforts have been made to quantify the impacts
of these factors on loss.
While conductor material and surface finish influences may be directly measured using printed wiring board test structures,
interpretation of the results are complicated by the influence of both the laminate material and the particular geometry
selected for the test structure (microstrip versus stripline versus differential pair). The results of such measurements
accurately reflect the specific test geometry examined,but are difficult to extrapolate to different systems.
An alternative test approach has been identified which provides a measure of conductor performance,decoupled from both
system geometry and the influence of laminate material.
The basic test method described in IPC TM-650 2.5.5.5.1. (Stripline Test for Complex Relative Permittivity of Circuit Board
Materials to 14 GHz) has been modified by comparing the results obtained using ideal smooth copper conductors and with
those obtained with samples of alternative conductor materials,while maintaining a constant dielectric material. Changes in
the resonator loss factor between the two tests allow calculation of the relative performance of the alternative material versus
the ideal conductor.
Using this test method,the performance of a number of surface finishes,PWB foil treatments and inner-layer adhesionpromotion
processes relative to a control smooth copper surface are reported.

A common industry practice is to confirm the characteristic impedance of critical PCB traces meet specified performance
tolerances before any components are attached. A popular technique is to use a time domain reflectometery (TDR) to derive
the characteristic impedance from reflections of a pulse injected into the designated “test” trace. One problem with the TDR
method is that interconnect anomalies located closer to the TDR launch location can impact the “apparent” impedance of
interconnect geometries following the anomaly. For example,through and stub via effects,trombone delay lines,and skin
depth losses can easily cause the computed TDR impedance to falsely indicate an out-of-tolerance condition,when in fact the
PCB is properly constructed. This paper describes what measures can be taken during the PCB layout to ensure that
subsequent TDR measurements of critical impedance-controlled traces will accurately represent the true characteristic
impedance.

This paper will discuss how R/flex® 3000 LCP materials from Rogers Corporation are "pushing the envelope" for high -
frequency & flex designs by examining:
1. How the material set has now been characterized out to 110 GHz,and why this can open the door for "ground-up”
liquid crystalline polymer (LCP) designs-ins.
2. What combinations of very thin film laminates and bond plys are now available,and how their electricals are
virtually unaffected by environmental conditions.
3. Which foils are available on the laminates with suggestions on their application,including test results with resistive
foils.
4. Where we see opportunities for producing tomorrow's circuit designs today.

Numerous technical articles have dealt with machine parameters,and their effect on wave soldering of Printed Circuit Boards
in the range of 40-93 mils and the typical 6 to 8 layers. This research concentrates on identifying the key process parameters
that affect wave soldering with 63Sn/37Pb solder on a 15 layer (9 signals and 6 power and grounds) board that is 104 mils
thick. A detailed Designed Experiment was developed and executed in multiple stages to identify the full impact of all the
factors considered. Key response variables that would impact yield and reliability of the product were considered. The results
were analyzed using the ANalysis Of VAriance or ANOVA approach. The aim of the research effort was to find a global
solution that would work well for 60 to 200 mils thick boards. The study was also aimed at finding more specific solutions
for other products based on board thickness. To date,this process had been successfully implemented on 135 mil thick 26
layer boards and 187 mil thick 16 layer boards.

Surface mount assembly has dominated its through-hole predecessor since the early 1990s. The higher density and lower
ultimate cost of SMT makes it a preferred assembly technology. However,the mechanical strength of through-hole
connections continues to make through-hole the technology of choice in assembling connectors. This presentation will
describe the primary methods currently used for through-hole connector assembly: 1) selective wave solder,2) pin-in-paste
(PIP),1 reflow,3) hand soldering and 4) solder preforms. We will show how solder preforms are an excellent alternative when
PIP provides insufficient solder.
The wave solder method requires specialized equipment and processes to solder connectors. Pin-in-paste reflow evolved as a
way to accomplish through-hole assembly without additional equipment or process steps. In the PIP method,the additional
solder required to fill the though-hole barrel is deposited by overprinting the pad in the area of each connector pin,using
standard SMT equipment. During reflow,the solder wicks to each pin forming the solder fillet.
This paper explains why pin-through-paste reflow methods based on overprinting solder paste have become more challenging
due to an increasing use of Organic Solderability Preservative (OSP),fine-feature devices (e.g. fine pitch connectors) and
densely populated PCB layout designs that conflict with requirements for successful use of step-stencils. This paper also
shows an example where solder preforms were used to provide extra solder volume for each pin. This work demonstrates
how solder preforms provide a viable manufacturing solution to ensure complete through-hole solder joints.

Solder preforms are precise shapes of metal,produced by the high-speed stamping or forming of solder wire or ribbon.
Preforms provide a highly repeatable volume of solder,with 100% metal content by volume. They are commonly used in
conjunction with solder paste to incrementally increase the volume of solder joints,which increases reliability in connections
subject to mechanical fatigue,and increases signal-to-noise ratios in interconnections delivering high frequency signals.
Dozens of OEM and contract assembly houses have realized that the use of solder preforms can solve issues related to
inadequate solder volume in SMT processes. As with the adaptation of any new technology,issues arise and are resolved as
the technology evolves into mainstream,high-volume production. Over the past two years of process evolution,the most
common issues related to the implementation of perform assembly have been associated with high speed placement.
Although the preforms are placed in a similar fashion to chip components,they have suffered higher pick error rates than chip
components .
A series of studies were undertaken to understand the factors that influence pick error rates. This paper reviews the
experiments that studied standard shapes,unique “super flat” geometries,component orientations,and machine feeder and
nozzle selection. It also discusses the effect of preform shape and size tolerances,and compares the geometric specifications
to those of chip components.

Environmental regulations are forcing the elimination of lead (Pb) from electronic equipment. Solders containing lead have
been the standard in printed circuit assembly processes. Lead-free solders currently being used and developed for printed
circuit assembly require higher processing temperatures that can degrade the base materials commonly used in printed
circuits,resulting in decreased long-term reliability. Following a brief discussion of the regulations and lead-free materials
and processes,this paper will discuss several base material properties and present test data that highlights the importance of
specific properties that should be considered when selecting materials for lead-free applications.

A new set of constitutive equations for a class of lead-free solder alloys,Sn(3.5-3.9)wt%Ag(0.5-0.8)wt%Cu is proposed in
this investigation. These equations are applied to a 256PBGA (plastic ball grid array) package assembly. The creep results in
the PBGA solder joints are compared against those with other constitutive equations reported in the literature.

Applications using flip chips in high temperature and high current designs have increased in recent years,and this trend is
expected to continue. Markets utilizing these designs include high performance ASIC,high frequency/RF,and mid I/O
products. The migration of flip chip use into these designs can be attributed in part to the improved solder bump thermal
fatigue life which has been realized with the use of underfills,as well as to smaller final metal pad/passivation openings
being used by IC manufacturers. The need to use flip chips under harsher operating conditions has prompted work to address
reliability concerns with several diffusion related failure mechanisms. These concerns have surfaced in response to results of
high temperature storage (HTS) and high temperature operating life (HTOL) tests. In HTS tests,UBM (Under Bump
Metallurgy) consumption has been observed. In HTOL tests,UBM consumption as well as solder and UBM electromigration
have been observed. On flip chips with a bump structure utilizing eutectic 63Sn37Pb over a sputtered thin film Al-NiV-Cu
UBM,the HTS and HTOL reliability is a function of the UBM thickness – increasing the UBM thickness can have a positive
effect on reliability. However,in general a thin film UBM provides better bump thermal fatigue life,excellent protection to
the underlying aluminum,and is less likely to cause silicon cratering or passivation cracking.
A new approach to increasing the UBM thickness and thereby improving flip chip reliability regarding diffusion related
failures (while maintaining thin film characteristics),is to use an enhanced eutectic SnPbCu solder bump containing a small
amount of Cu in the 1% - 3% range. During bump reflow,the Cu in the enhanced eutectic SnPbCu solder bump has been
shown to precipitate out along the UBM/Solder interface,effectively forming a thicker UBM. This effectively thicker UBM
has been shown to extend the performance life of the structure in HTS and HTOL testing as compared to 63Sn37Pb while
maintaining equal performance in thermal fatigue life as evidenced by thermal cycle (TC) testing. This paper presents data
showing the increased reliability performance of the enhanced eutectic SnPbCu bump structure as compared to 63Sn37Pb.
Assembly and manufacturing characterization data demonstrating the excellent quality and manufacturability of the SnPbCu
bumps is also presented.
The liquidus temperature of SnPbCu alloys increases with increasing Cu %. Increasing Cu % beyond a certain level would
necessitate increased process reflow temperatures. Tests indicate that for purposes of wafer bump and circuit board assembly
reflows,enhanced eutectic SnPbCu alloys in the range of 1% - 3% Cu can be processed using standard eutectic 63Sn37Pb
reflow profiles. Data is presented showing that alloys within this composition range provide significant reliability benefits.

Electroplated pure tin and tin alloys such as Sn99.3Cu0.7%,Sn98%Bi2% and Sn96.5%Ag3.5% have been identified as
viable drop-in replacements to tin-lead solder. High melting point tin alloys such as Pb97%Sn3% and Au80%Sn20% are also
required by the electronics industry for flip chip applications. Capabilities of the commercial pure tin bumping chemistries
will be discussed and demonstrated.
However,commercially feasible plating systems for lead-free tin alloys have yet to be developed. The major difficulty in
plating tin alloys comes from the large difference in standard deposition potential of tin and the alloying metals that result in
poor alloy control and immersion of alloying metals on tin parts and anodes. Enthone Inc. has developed new processes that
allow robust and reliable electroplating of these alloys. We also studied the effect of plating parameters (current density,
agitation,temperature,etc.) and alloy composition on the materials properties of deposited alloys such as voiding,bump
height uniformity across a wafer,reflowability,phase composition,structure,hardness and melting temperature. A few defect
types specific to bump plating and ways to overcome them will be discussed. Recommendation will be made on utilization of
specific finishes for different electronic applications.