The multiple die chip-scale package technology (identified as the ?Z™) is a truly innovative,folded-flex stacked packaging technology. The concept has already been proven in a collaborative development effort between Tessera and two customer companies. A two-die package,developed for a leading medical electronics company,has been qualified and is currently in limited production. The three and five-die package developed for a leading IC manufacturer was targeted for the new generations of wireless electronics. The folded-flex stacked die package meets the lower height target defined by many OEM customers (a significantly lower height than many of the two die stacked wire-bond solutions available today). Implementations are now being requested by the industry that requires the inclusion of different types of silicon technologies (including memory and logic) into a single package footprint resulting in a solution that is in essence a system-in-package. However,due to differing wafer-level yield rates,multiple silicon sources and testing methodology,the packaging yield and logistics issues can be very difficult to resolve (at both the technical and the business levels). In order to meet this growing demand for further integration,an innovative solution is required that brings all of the benefits of more conventional chipscale packaging,including size,performance and reliability,while addressing testing,yield and logistics issues. This paper examines several alternative multiple-die package solutions that solve many of the problems identified above while delivering the expected benefits. The package technology adapts one and two metal layer,flexible substrate materials,allowing two,three,four or more die in a single die BGA outline. Most of the multi-die packages developed for memory applications use classic CSP processes for die interconnect,though,other conventional interface techniques can be employed as well. The enabling technology for this “fold-over” approach allows the different sub-structures to be electrically connected while still maintaining a small footprint. The individual die included in the stack can be packaged,tested,and marketed as individual sub-structures,allowing each die to be sourced separately by each silicon vendor. This “layered” approach to packaging is designed to improve yield,resolve test concerns and overcome the business issues hindering the wide-scale adoption of multi-die solutions.

With the advent of more flexible versions of pulse-reverse plating technologies,and with the ability to program more of the waveform parameters,comes an increased number of options facing the user. An impediment to the rapid determination of the optimum programming parameters in any via-plating system is the very large numbers of test runs this can generate,and the very time-consuming cross-section evaluations needed to assure that valid decisions are made. Similarly,this “cross-section proliferation” problem faces platers contemplating any other plating process options (eductor placement,vibration equipment,agitation changes,chemical changes,etc.) Building on an idea put forward by Yair Assaf at AESF SurFin 2002,this paper reports on experimentation using a test unit to allow programs to be pre-screened without cross-section verification,in comparison with conventional cross-section evaluation. The test unit is designed to be used by itself,or to accompany parts through the plating cycle,and consists of a tapered-gap,with a removable copper tape as plating substrate. All this is to permit better/faster/less burdensome realization of the benefits of complex wave form pulse reverse systems in via formation. It is our hope that others in the industry will expand on this idea to the point that it can be developed into a useful,reliable tool.

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Laser-drilled microvias are being added to the list of approved technologies for printed wiring boards destined for use in a rapidly increasing number of application types and environments. Microvias are frequently used on boards targeted for communication,test and measurement,and RF/microwave applications. The testing and results presented herein demonstrate that laser-drilled microvias are reliable for use in the aggressive environments experienced by avionics products. Failure-free performance through 2000 temperature cycles is a Rockwell Collins guideline for printed circuit boards and assemblies intended for avionics applications. Reliability exceeding this requirement is established using temperature cycling as a test method,with results from plated through holes as a baseline. The test plan was comprehensive in scope,and independent variables included surface finish,hole aspect ratio,buried microvias and buried plated through holes,and ‘microvia in pad’ structures. Special consideration is given to evaluation of dielectric spacing less than the “3.5 mils minimum” typically required for avionics products.

Despite the strong increase in demand for high-density circuit boards,very few manufacturers are offering microvia architectures in high volume. Current microvia technologies require significant changes in multilayer manufacturing methods as well as new materials and new chemistries. The electroless plating chemistries most commonly used are costly and difficult to maintain,and the dimpled morphology of the resulting microvias is problematic. Transient liquid-phase-sintered (TLPS) paste-filled microvias are solid,planarize during processing and will alloy to all conventional circuit finishes during standard lamination cycles. Although TLPS microvias,like most other microvia technologies,do require laser-drilling capabilities,no other significant change to standard multilayer PCB fabrication is needed. Use of advanced laminates/prepregs or resin-coated-foil is optional. The TLPS microvia technology was proven in cutting-edge multilayerflex IC packages. It has since been adapted for use in multilayer PCB applications and can cost-effectively enable any multilayer board shop to offer HDI products.

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The evolution of interconnection systems for Printed Circuit Boards has been extremely interesting. The first connections were those generated in a copper foil on the surface of a single sided insulating substrate. The first method providing connectivity between circuit patterns on both sides of an insulating layer was the use of rivets. When crimped correctly,these units allowed the development of multi-layered circuit patterns. The introduction of electroless copper systems allowed this interconnection to be made chemically,and resulted in much more reliable electrical interconnects. The number of layers could be increased until the point was reached where reliability became a critical quality issue. It was not unusual to see finished product with 20,30,40,or more layers. The problem inherent in the use of through hole technology is that a large portion of the ‘real estate’ of the circuit planes was used for connectivity requirements,thus reducing the density potential for the product. Within the past decade,a new concept of interconnectivity has been introduced. The technology is called “Microvia Formation”. By IPC definition in document IPC/JPCA-2315,microvias are those interconnection vias less than 150??(0.006”) in diameter. This paper relates to problems inherent in the formation of microvias

The need for the high density provided by Build-up PWB installed in the mobile communication products requires the general trend towards a gradually smaller hole diameter. For the micro via drilling,it has been categorized by the process as shown in Figure 1 so far,and due to the technology development,further smaller holes are processed. This paper presents these up-dated technologies.

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For faster,smaller,and high performance integrated circuits the new concept of buried bump interconnect substrates is required. We have developed B2itTM (buried bump interconnection technology) for this technical trend. The fine phase of this interconnection technology carries out the build up of the fine wiring layer of Cu/BCB on all buried bump interconnection technology wiring boards for high-density and high performance. This paper reports the results that focus on the fine wiring layer formation process technology and the high frequency transmission characteristic of the fine phase as a result of a fine wiring formation process' adopting BCB as dielectric material and the sputter semi additives method. The limitation of the minimum pitch was 10µm (L/S=6 /4). Filled via process was possible for a 20µm via diameter. Electromagnetic simulation was performed to research the dependence of the signal transmission characteristic on the pitch of fine lines. When the pitch becomes small at 10µm or less,it turns out that transmission loss becomes large due to the influence of contiguity wiring. As high frequency correspondence aptitude,a result of the S parameter with micro strip line structure,it was –3dB in 16GHz. From this,as a design rule for fine wiring layers,a pitch of 15µm (L/S=7.5/ 7.5),and 20µm for filled via diameters are optimal designs. The fine wiring technology was developed and designed for a high density and high-speed substrate,utilizing this buried bump interconnection technology.