Controlled Surface Etching Process for Fine Line/Space Circuits

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The design rule of PWBs and substrates for plastic packages is moving towards higher density as semiconductor
chip design evolves into increasingly finer lines. First,it was studied how fine the conventional subtractive process
could build line and found that line/space of that process is limited to around 40/40,even if using some new
technologies. The next challenge was to find a process that can build line/space and get rid of some issues of the
additive or semi additive process. It was confirmed that the improved pattern plating process used with CSE
(Controlled Surface Etching) process is capable of making finer line/space circuits like around 25/25 microns. The
CSE process is characterized by a uniform etching of the base copper with an improved soft etching solution.

Author(s)
Ken-ichi Shimizu,Katsuji Komatsu,Yasuo Tanaka,Morio Gaku
Resource Type
Technical Paper
Event
IPC Printed Circuits Expo 2002

Conductive Anodic Filament Resistant FR-4 Substrates

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As the trend to increased interconnection density continues,conductive printed circuit board features become closer and closer together. It is now common to see 3 mil lines and spaces on local areas of circuit boards,and via spacing of less than 10 mils. As the feature spacing gets smaller the probability for Conductive Anodic Filament (CAF) growth becomes significant. Many PWB designs now require the use of CAF resistant substrates to reduce the opportunity for CAF failures. Early solutions to CAF required use of Non FR-4 substrates such as Bismaleimide Triazine based materials. To meet the increasing requirements for CAF resistance and use the current PWB fabrication process,new FR-4 materials are needed. CAF is the growth of a subsurface filament from an anode to cathode. This is the result of an electrochemical corrosion process that causes deposits of corrosion byproducts along the fiberglass filaments to form. The current model of CAF formation and growth involves two steps,the physical degradation of the fiber/epoxy bond followed by an electrochemical reaction responsible for conductive deposits to form. There are many factors that can contribute to CAF formation. These are summarized in Figure 1. Efforts to develop FR-4 substrates more resistant to CAF growth have focused on both improving the Epoxy -Filament bond and reducing the probability of the electro-chemical reaction occurring by modifying the FR-4 resin chemistry and the nature of the silane finish on the fiberglass reinforcement. New more CAF resistant FR-4 products have been developed and are now available. The development of these imp roved FR-4 substrates demonstrates that epoxy based FR4 materials can be capable of meeting the requirements for CAF resistant high-density PWB designs. CAF test data comparing traditional FR-4 materials to new FR-4 products developed by Polyclad Laminates will be presented. These new materials have been shown to greatly improve CAF resistance.

Author(s)
William D. Varnell,Helen M. Enzien,R. Hornsby
Resource Type
Technical Paper
Event
IPC Printed Circuits Expo 2002

Conductive Anodic Filament Growth Failure

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With increasing focus on reliability and miniaturized designs,Conductive Anodic Filament (CAF) as failure
mechanism is gaining a lot of attention. Smaller geometries make the printed circuit board (PCB) susceptible to
conductive anodic filament growth. Isola has carried out work to characterize the CAF susceptibility of various resin
systems under different process and design conditions. Tests were carried out to determine the effect of various
factors such as resin systems,glass finishes,voltage bias and hole and line spacings on the CAF resistance.
This work was intended to provide information to the user on the suitability of various grades for specific end use
applications. The focus of the work at Isola is to find the right combination of process and design conditions for
improved CAF resistant products.

Author(s)
Tarun Amla
Resource Type
Technical Paper
Event
IPC Printed Circuits Expo 2002

Component Damage from Printed Circuit Board Loading

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Electronic components are being used in increasingly more severe shock environments. This combined with an
industry trend of increased component reliability to help reduce electronic system downtime has created an
increasing demand for understanding the loads imparted through a printed circuit board (PCB) to an individual
component on the board. Local stiffening of the circuit board can limit the component loads,however stiffening
devices can be costly to design and implement. They are also bulky,taking up valuable space on already crowded
PCBs. Both experimentation and analytical tools were used here to investigate how loads are transmitted through a
circuit board to an individual component.
Two case histories are presented that investigate how specific loads applied to a circuit board may damage
individual components. In the first case history,failures of surface mounted capacitors were occurring at some point
during the PCB assembly process. In order to isolate the specific step in the assembly process that was causing the
damage,miniature strain gages were adhered in several locations adjacent to the subject capacitors. The strains were
monitored as the instrumented PCB was put through its normal assembly process. The measured strains at the gage
locations were compared to the reported strength of the capacitors.
In the second case history,a PCB carrying a single ceramic column grid array (CCGA) package was subjected to
static and shock loading. Strain gages were adhered to the CCGA and the PCB near the CCGA to measure the level
and duration of static and shock strains imparted during typical PCB handling,and insertion into,and removal from,
a multiple board chassis. The highest magnitude shock loads resulted from PCB bending,and occurred as the printed
circuit board connecter contacted its mate on the chassis.
A finite element analysis of the circuit board and CCGA was conducted to infer from strains measured near the
CCGA the individual solder column loads that might result from the PCB insertion and removal. It is these pins that
sometimes fail during use. It is suspected that high pin loads from PCB shock loads significantly lower the lifetime
of a CCGA. CCGA pin loads are determined from the finite element analysis for a given PCB load,and compared to
the ultimate tensile strength of the subject material.

Author(s)
D. H. Duffner,R. W. Klopp,A. Wagner-Jauregg,R. A. Sire,E. M. Webster
Resource Type
Technical Paper
Event
IPC Printed Circuits Expo 2002

Breaking the Information Bottleneck in Printed Circuit Board Engineering Teams: The Promise of New Software Innovation

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This paper addresses the challenges of pre-production engineering,why the engineering department is viewed as a
bottleneck in many PCB companies,and how a dedicated software system breaks the information bottleneck and
permits true collaborative engineering. There is now software technology that integrates and automates standard and
customized engineering processes to streamline workflow and collaboration,improve quality,reduce errors,and
reduce pre-production costs. With it,the productivity of an engineering department can increase dramatically,
reducing time-to-production and increasing customer order fulfillment rates. The need for rules,an extensible data
structure,and an open architecture in an intelligent,collaborative system is explained. The key characteristics of the
features and functionality are outlined. The benefits of such a system are described and how value is added to the
engineering function,the company,and customers.

Author(s)
Miten Shah
Resource Type
Technical Paper
Event
IPC Printed Circuits Expo 2002

Board Finishes for the EMS Provider

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Some new alternative PWB surface finishes have been entering the industry over the past few years. In order for any
new board surface finish to be accepted for general use,it must be approved by the OEM as well as the EMS
provider. This approval process begins with the chemical suppliers performing their own initial trials and tests. The
supplier must approach potential EMS and OEM users to determine their interest in the finish. The EMS providers
must run some trials to determine the advantages and disadvantages of the finish,compared to existing finishes. The
OEM must determine if the finish is suitable for and compatible with any particular product application. This
assessment must consider such items as whether the product requires: single reflow or multiple reflow assembly
processes,precious metal contact,EMI shielding,press fit connection to a particular metallurgy,operation in a
particular environment,etc. The board finish must be able to provide the EMS provider with a consistent assembly
process that has a very high assembly yield. The resulting interconnections must provide a long term,reliable
product for the OEM and end customer.

Author(s)
Bruce Houghton
Resource Type
Technical Paper
Event
IPC Printed Circuits Expo 2002

Beyond Periodic Pulse Reverse

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According to Michael Shernerof of Scientific American (Jan. 2002) technology has advanced more in the past one century than in the previous one hundred centuries. Yet it seems from a technical perspective that many of these advances yield distinct paths and isolationist positions,where each “technology island” meets only a part of our needs. Not until a technology is fully evolved,can we apply it to our entire spectrum of problems. Some practical examples may help define “technology islands”. As the electronic typewriter evolved into a PC application such as MS Word,those who needed to utilize data adopted data base programs such as Excel,others who dealt primarily with presentations standardized on Power Point. Users were grouped or isolated into different applications based on their primary need. Yet each category of users did not have 100% of their needs met by their one primary application. Using two or three applications still limited them or at best reduced productivity. The evolution of this technology led to the Microsoft Office application allowing the seamless use of all three programs. This can be viewed as less choice; one program vs. three but yielding improved capability. “The evolution of technology is not about increasing choices,but about it’s ability to meet our spectrum of needs effectively”. Other examples include the DVD race. Currently there are three formats; one which is common and low cost,a second which is feature rich and a third which holds more data but is expensive. The evolution of this technology will be an a fordable feature rich product that holds large amounts of video data. Most of us have a home telephone number,a cellular telephone number,an e-mail address and some of us also have a personal pager number. Many choices,but not the most effective means of tracking a person down. This technology will eventually evolve to optimally meet our needs when a single personal identifier serves for all our voice and data communication,independent of our location. Yet another technological advancement,which has led us into “technology islands” is the use of plating waveforms; Direct Current (DC),Periodic Pulse (PP) and Periodic Pulse Reverse (PR). Each provides unique capability but is exclusive and limits us to that specific benefit. This paper will deal with these waveforms and introduce a bridge between today’s single waveform choice and tomorrow’s evolved product,introducing a practical method (tool) for increasing quality,capability and profitability for electroplating advanced electronic devices such as PWBs,wafers and semiconductors packaging. How is it we evolved into “electroplating technology islands”: DC,PP & PR? The short answer is that unique technologies evolve as a result of multiple companies independently advancing technology. The historic lack of cooperative effort between system integrators,chemical and power supply manufactures creates independent standards (plating methods),each driven by that individual company’s desire and competency to generate revenue.

Author(s)
Enrique Gutierrez Jr.
Resource Type
Technical Paper
Event
IPC Printed Circuits Expo 2002

The Advanced NiAu-Process for Second Image Technology

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Designs of new electronic products show a significant drive for smaller and more complex PWBs. This continuing trend of miniaturization affects components in the same way as for the connecting pads on a printed circuit board. Driving force on the one hand is the telecommunication industry,in particular mobile phones and hand held devices and on the other hand by developments in networking and server applications. The effect of this is a transition in assembly technologies from through hole technology in the past,to surface mount,up to latest technologies with BGAs,CSPs,MCM or Flip Chip. With continuing changes in assembly technologies,the demands of the final finish of a PWB increases,where HASL as final surface was first choice for through hole assembly and for the beginning of SMT. With an increase of the interconnect density combined with an increase of fine pitch,HASL reached its technical limits. Features of HASL are variations in tin/lead thickness distribution – from 1µm up to 50µm and high thermal stress to the PCB while processing / dipping into a molten solder alloy. This kind of processing is leading to warpage. Features like these implemented the move to alternative coatings; HASL could not fulfil all technical requirements for assembly anymore. Due to technical demands,new surface finishes were required. First choice for multiple reflow was electroless nickel immersion gold - ENIG. This finish has world wide a high acceptance on the market,with benefits unique to ENIG. These days other finishes are moving into the market with the same advantage of planar surfaces for multiple reflow cycling,as there are electroless palladium,immersion tin and immersion silver. All these HASL alternatives combine low thermal operating temperatures during processing and planar surfaces for assembly.

Author(s)
Sven Lamprecht
Resource Type
Technical Paper
Event
IPC Printed Circuits Expo 2002

Advanced Laminate and Prepreg for PWBs with Embedded Components

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The technology for embedding components in PWBs will change the process how PWB are fabricated over the next
few years. At the present time,polymer thick film is the most frequently used material to embed “passives” in
PWBs. However,these do not meet the stringent tolerances that will be needed in the future and will be replaced by
new materials based on ceramic,thin film or even with silicon. The coefficient of thermal expansion (CTE) of such
new technology embedded components is,in most cases,lower compared to the CTE of standard glass-reinforced
materials used today. In addition,the distance between the component lead and the PWB connection will be shorter
and will thus absorb less stress. For the effective use of embedded components,the dielectric thickness between the
conductive layers will be reduced. High dielectric strength,CAF resistance and low migration are required,while
resin recession cannot be accepted on plated inner via holes. This paper explains the impact of CTE imbalances
caused by the different materials used in a PWB. It also provides guidance on how PWB manufacturing process can
be modified to accommodate the new requirements from the PWB fabricators,assemblers and OEMs. These
requirements are for high dimensional stability of the laminate and prepreg to improve manufacturing yields during
bare PWB fabrication,during assembly and during the life cycle of the electronic device in the field. The paper also
explains the risks of metal migration and conductive anodic filaments (CAF) in PWBs and the need for lower
dielectric constant (Dk). The new materials are processable in standard PWB fabrication lines and can accommodate
the needs engendered by halogen-free resin systems.

Author(s)
Michael Weinhold
Resource Type
Technical Paper
Event
IPC Printed Circuits Expo 2002

Accelerating Plating Cycles and Reducing Costs: Improving the Plating of High Aspect Ratio Holes & Blind Vias

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This paper describes a new technology for speeding the initiation and uniformity of electroplating deposits that does
not depend on modifying the chemistry or physical environment of the plating bath. Rather,it involves the treatment
of conductive surfaces outside of the plating environment and is therefore not dependant on any particular type of
bath,the pH of the bath,or the chemical agents contained in the bath. Process improvements include a more rapid
initiation of plating; an increase in "throwing power" into low current density areas; and improved metal-to-metal
bonding such that very thin deposits exhibit unusual resistance to corrosive testing environments.

Author(s)
James Taylor
Resource Type
Technical Paper
Event
IPC Printed Circuits Expo 2002