The last 10 years have seen the rise of lasers used in the interconnect industry to a point where their use is almost becoming ‘main stream’. As line width and spacing requirements become smaller,lasers will play an ever increasing role in the manufacture of interconnect devices. There is currently a gap between lithography processes on the small side and ‘traditional’ etch/mechanical methods on the large side which lasers fill quite nicely. Within these bounds,lasers are poised to be the dominant manufacturing technology for many processes.

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As CPUs increase in performance,the number of passive components on the surface of the boards are increasing dramatically. To reduce the number of components,as well as improve the electrical performance (i.e. reduce inductance),designers are increasingly embedding capacitive layers in the PCB. The majority of the products in use today utilize reinforced epoxy laminates. These products are relatively easy to handle,but the thickness and Dk limit the effectiveness of the layer to perform as a capacitor. Other materials are being developed that are thinner (and thus increase capacitance),but either have problems with dielectric breakdown strength,handling or only marginal improvement over the existing material. This paper will describe new non-reinforced substrates for use as embedded capacitance layers that address these issues. The material selection process,substrate processing and electrical performance will be reviewed.

Increasing component density and the requirements of higher performance electronic devices are driving the development of embedded passive devices in the printed circuit board (PCB). The benefits of embedded passives are that they free surface space for active devices,improve performance and signal quality by lowering inductance and reduce overall system cost. Embedded passives also yield a more reliable printed circuit board by reducing the number of solder joints. A resistor is an important passive device in an electric circuit. To enable high performance devices,an embedded resistor must achieve a tolerance that allows the PCB design to meet electrical timing and circuit signal quality requirements. The tolerance of embedded resistors is not only determined by the uniformity of the resistor material but also by the PCB manufacturing process which forms them,especially when the sizes of the embedded resistors are small. The stability of the material when subjected to typical printed circuit board processes will also affect the final tolerance of embedded resistors. Gould has developed a thin-film NiCr alloy resistive layer sputtered onto rolls of copper foil for embedded resistor applications. Nickel-chromium alloys possess high electrical resistivity,good electric performance and high thermal stability. The thin film is very uniform,and is capable of forming resistors with tolerances that meet the requirements of high performance PCBs. Merix Corporation is involved in the NIST Advanced Embedded Passives Technology (AEPT) consortium,and has built test vehicles for the consortium and customer prototypes using Gould's thin-film alloy resistor foil. This paper reviews data from the material manufacturer on the effects of specific processing factors on the overall tolerance of the resistor,and describes the board fabricator's process development for reducing resistor variation and improving yields.

The current technology includes transmission of between optical units (typically modulated laser sender and receiver units) and fiber optic cables or flexible kapton fiber optic cables with which we are all relatively familiar. Methods for forming and connecting fiber optic systems are well developed. The primary new developments in this area may be in modulation and multiplexing techniques and connection methods. At present the optical and digital devices may be mounted on opposite sides of the PCB for optimum design and all connections are on the surface of the PCB. The limitations for this technology for on board transmission of signals are size,surface space requirements,and limited channels available. As can be seen in Figure 1,no decided advantage may be realized in the inclusion of embedded passives in this type of architecture beyond those advantages seen in any multilayer structure.

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Several factors are driving the need for buried passive components in printed circuit boards and chip carriers. Increasing frequency increases the difficulty in quieting noise by the use of surface mounted discrete capacitors and resistors. Decreasing voltage makes transmission lines more sensitive and signal integrity more difficult to maintain. Increasing power consumption by silicon devices drives the need for lower inductance,and higher capacitance power distribution in close proximity to the to the silicon device. A larger number of active silicon devices per unit of surface area decrease available space for passives.

The increased need for smaller,faster,and cheaper electronics has led the microelectronics industry to explore a number of new enabling technologies. Embedding passive components into multi-layer printed circuit boards offers the potential to deliver a number of benefits,including saving valuable board surface area,increasing performance,reducing manufacturing costs,improving reliability,and providing opportunities for less expensive substrate materials. As PCB manufacturers embrace this technology,and as requirements for tighter tolerances become more necessary,laser trimming for these components will also become necessary,prompting manufacturers to add embedded passives trimming equipment to their current manufacturing process. Technology for trimming embedded resistors has been recently demonstrated for production applications1,and the industry is beginning to look more closely at cost models. Cost models are currently available,2,3 presenting a general overview of the costs,and allowing for comparisons to alternative surface mount technologies. This paper will discuss the process of laser trimming embedded resistors in a production environment,and will investigate the process cost of ownership.

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