IPC APEX EXPO 2023 Offers New Courses, New Instructors, and IPC E-Textiles

New this year, IPC E-Textiles co-located with IPC APEX EXPO

Registration is now open for IPC APEX EXPO 2023, the largest event for electronics manufacturing in North America. IPC APEX EXPO will be held at the San Diego Convention Center in San Diego, Calif. from January 21-26, 2023. New to the IPC APEX EXPO 2023 lineup will be the co-located IPC E-Textiles conference on Monday, January 23, 2023.

The theme for IPC APEX EXPO 2023, “Advance in a New Era,” is reflected in the technical conference and professional development courses covering new, unpublished results, techniques, processes, and trends facing the $2 trillion global electronics manufacturing industry. Featuring four technical conference tracks and 36 professional development courses, international subject matter experts from all aspects of electronics manufacturing will be represented. Covering topics from PCB fabrication troubleshooting and defect analysis to cybersecurity, design, substrates, and advanced packaging, attendees can choose from a wide array of papers and courses that go beyond theory to address real-world problems and provide practical solutions that can be implemented immediately for real-world success.

“We have made significant efforts to offer improved educational offerings and new topics that will indeed advance the industry into a new era. Technical conference and professional development content, including the latest original research, will set the stage for the electronics industry innovation that will turn our industry toward the future,” said Julia Gumminger, IPC professional development and events manager. “Our educational program features a wide variety of learning opportunities where attendees can access the latest research and development in the industry and learn more about trending materials, applications, and processes. Attendees can bring their new knowledge, skills, and contacts back to their daily work.”

IPC APEX EXPO 2023 will also feature free activities, including poster presentations, an opening keynote from Emily Callandrelli, mechanical and aerospace engineer and the host and co-producer of Emily’s Wonder Lab on Netflix, a PCB design competition, and a STEM event for San Diego-area high school students. For the first time, additional keynotes from John Mitchell, IPC president and CEO, and Shawn DuBravac, IPC chief economist, will take place during Monday and Wednesday luncheons. Networking events on the show floor will be featured along with the industry’s largest gathering of leading equipment manufacturers, supplies and innovators.

One of the most invaluable features of attending IPC APEX EXPO is the exposure to new products and services,” said Alicia Balonek, IPC senior director of trade shows and events. “As the largest electronics manufacturing exhibition in North America, IPC APEX EXPO provides companies throughout the industry supply chain with an ideal venue to highlight new products and services through the New Products Corridor and the opportunity to showcase new equipment, products and services on the show floor, allowing attendees access to the latest innovations from the industry’s leading manufacturers all under one roof.”

Access to the exhibit hall is free with an Event Essentials pass to those who register by January 21, 2023, a savings of $40 on-site. Additional savings include a 20 percent discount for those registering through December 16, 2022.                                      

More information about IPC APEX EXPO 2023, including details on education and technology, networking opportunities, show floor activities, schedule, travel, and more is available at www.IPCAPEXEXPO.org.

Fabric Weaving and Circuit Orientations Impact for Skew / Signal Integrity

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This Presentation discusses Improvements for signal integrity.  Signal integrity is based on the copper surface roughness, the oxides on the copper, and the Dielectric constant of the Dielectric material.  The Dielectric material dielectric constant is effected by the glass weave and the weave pattern.  The weave is also effected by skew.   

Author(s)
Eric Liao
Resource Type
Slide Show
Event
IPC APEX EXPO 2019

Innovations for future RF designs

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This Slide show presents RF Cap Layers to normal FR4 Dielectric materials.  This material can be used in multiple configurations including Single sided, Double sided, and Hybrid.   This material contains different and enhanced Dielectric Frequencies for Radio Frequency PCBs.  

Author(s)
Matthew Lake
Resource Type
Slide Show
Event
IPC APEX EXPO 2019

Higher Defluxing Temperature and Low Standoff Component Cleaning-A Connection?

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OEMs and CMs designing and building electronic assemblies for high reliability applications are typically faced with a decision to clean or not to clean the assembly. If ionic residues remain on the substrate surface, potential failure mechanisms, including dendritic growth by electrochemical migration reaction and leakage current, may result. These failures have been well documented.

If a decision to clean substrates is made, there are numerous cleaning process options available. For defluxing applications, the most common systems are spray-in-air, employing either batch or inline cleaning equipment and an engineered aqueous based cleaning agent.

Regardless of the type of cleaning process adopted, effective cleaning of post solder residue requires chemical, thermal and mechanical energies. The chemical energy is derived from the engineered cleaning agent; the thermal energy from the increased temperature of the cleaning agent, and the mechanical energy from the pump system employed within the cleaning equipment. The pump system, which includes spray pressure, spray bar configuration and nozzle selection, is optimized for the specific process to create an efficient cleaning system.

As board density has increased and component standoff heights have decreased, cleaning processes are steadily challenged. Over time, cleaning agent formulations have advanced to match new solder paste developments, spray system configurations have improved, and wash temperatures(thermal energy) have been limited to a maximum of 160ºF. In most cases, this is due to thermal limitations of the materials used to build the polymer-based cleaning equipment. Building equipment out of stainless steel is an option, but one that may be cost prohibitive.

Given the maximum allowable wash temperature, difficult cleaning applications are met by increasing the wash exposure time; including reducing the conveyor speed of inline cleaners or extending wash time in batch cleaners. Although this yields effective cleaning results, process productivity may be compromised.

However, high temperature resistant polymer materials, capable of withstanding a 180°F wash temperature, are now available and can be used in cleaning equipment builds. For this study, the authors explored the potential for increasing cleaning process efficiency as a result of an increase in thermal energy due to the use of higher wash temperature. The cleaning equipment selected was an inline cleaner built with high temperature resistant polymer material.

For the analysis, standard substrates were used. These were populated with numerous low standoff chip cap components and soldered with both no-clean tin-lead and lead-free solder pastes. Two aqueous based cleaning agents were selected, and multiple wash temperatures and wash exposure times were evaluated.

Cleanliness assessments were made through visual analysis of under-component inspection, as well as localized extraction and Ion Chromatography in accordance with current IPC standards.

Keywords: Aqueous based cleaning process, PCB defluxing, wash system cleaning parameters, thermal energy, chemical energy, mechanical energy.

Author(s)
Jigar Patel and Umut Tosun
Resource Type
Technical Paper
Event
IPC APEX EXPO 2019

Methodology for Developing Cleaning Process Parameters

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Electronic assembly processes range from simple to complex and involve a wide range of materials to produce. Each step in the process and each assembly material used will have some impact on the assembly, most affecting the cleaning process window. The first step in developing the cleaning process is to determine the solubility parameters of the residues present post soldering with available cleaning agents. The first step quantifies wash concentration, wash temperature and wash time. The second step determines cleaning energy required to deliver the cleaning agent under low profile leadless and bottom terminated components. The second step determines optimal impingement sources to create a flow to wet and dissolve residue under component bodies. The third step is to test rinsing effects. The third step tests for the presence of cleaning agent and ionic residues left under component bodies. The fourth step is to check materials compatibility with the cleaning agent and process. The fourth step provides the process engineer with awareness of material compatibility risks when cleaning electronic hardware. The fifth step is to validate the acceptability of electronic assemblies using both electrical and chemical test methods. The purpose of this research paper is to determine the feasibility of this five-step method for developing the cleaning process window followed by validating acceptability of the electronic assembly.

Author(s)
Mike Bixenman, Mark McMeen, Vladimir Sitko, Axel Vargas
Resource Type
Technical Paper
Event
IPC APEX EXPO 2019

IPC-J-STD-001 Rev G, Amendment 1, Section 8 Cleanliness SectionSIR Test Method for Developing Objective Evidence for the Production Assembly

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Since the 1970s, ROSE testing was used to determine “clean enough.” In 2015, the J-STD-001 committee assigned a team to develop the next generation of “cleanliness” requirements. Section 8 defines the key concepts that drove the need for developing new cleanliness requirements.

•ROSE testing for product acceptance (pass-fail) is an obsolete practice for determining acceptably clean

•ROSE testing for process control is perfectly acceptable, but the numbers have to MEAN something. And those values need to be scientifically/statistically determined

•No one set value defines the line between acceptably clean and unacceptably dirty

•No one method determines acceptably clean and unacceptably dirty

A qualified manufacturing process should be determined using some form of temperature-humidity-bias sort of testing (such as SIR). Qualifying a manufacturing process through chemical analysis alone (e.g., ion chromatography) does not tell you the effects of the residue under humid conditions, which is where electrochemical failures occur. Companies that have come up with ionic standards by IC also use temperature-humidity-bias (THB) testing somewhere in their qualification process.

The purpose of this paper is two-fold: 1. Research on the development of temperature-humidity-bias instrumentation and test board designs for product acceptance. 2. Follow on DOE to better understand the impact of cleanliness at the bottom termination of the QFN/BTC component.

Author(s)
Mark McMeen, Doug Pauls, Mike Bixenman
Resource Type
Technical Paper
Event
IPC APEX EXPO 2019

Oxidation Resistant Nano-Cu Sintering Paste for Die Attach Applications

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A nano-Cu pressureless sinterable paste was developed for joint formation applications. The material was further engineered in both chemistry and process for enhanced oxidation resistance. This oxidation resistance capability allowed the paste to exhibit a shelf life of 6 months when stored at -10°C. The paste was insensitive to either sintering atmosphere or surface finish type, and consistently exhibited a joint shear strength around 13 MPa. Nano-Ag pastes were observed to be sensitive to surface finishes and performed particularly poorly for OSP-OSP system. The shear strength of nano-Cu was sensitive to sintering temperature and time, with shear strength increased from 220°C/15 min, 220°C/30 min, to 240°C/15 min. The joint shear strength deteriorated with increasing TCT (-40°C/150°C) cycle number. After 3000 cycles, the ranking of shear strength can be shown below: Nano-Cu > Ag-N > Ag-H2 > Ag-H1 > Ag-K > Ag-D. The high Pb joint performed the best. The microstructure of Nano-Cu joint formed at 240°C/15 min sintering condition indicated a continuous sintering progress with increasing TCT cycles, with porosity diminishing and smooth area increasing. This strongly suggests that either a higher temperature or a longer time than 240°C/15 min is desired for improved sintering extent. Further homogenization at paste manufacturing process also resulted in significant improvement in joint strength.

Key Words: Nano Cu, paste, pressureless, sintering, die attach, high power

Author(s)
Min Yao, and Ning-Cheng Lee
Resource Type
Technical Paper
Event
IPC APEX EXPO 2019

Fluxes Suppressing Non-Wet-Open at BGA Assembly

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With the advancement in miniaturization, the die is getting thinner and the solder balls are getting smaller for BGAs. Consequently, the thermal warpage is getting more severe due to the mismatch of the coefficients of thermal expansion between die and molding compound and the decreased stiffness of thinner miniaturized packages. Increased warpage can result in non-wet-opens(NWOs) during BGA assembly. NWO has been ailing the industry for a long time, and costly rework is required to remove the problem. In this study, a “cold-welding barrier” method has been developed to suppress NWO.  At BGA assembly, after printing solder paste onto PCB, the BGA balls are dipped into creamy flux or solder paste prior to placing onto paste printed. This flux pickup effectively suppresses NWO by serving as cold-welding barrier. The efficiency of different material and process variations for suppressing the occurrence of NWO defects have been investigated by using dummy BGA components and PCBs. The results demonstrate that effective NWO defect suppression can be achieved using the proposed method.

Keywords: BGA, non-wet-open, NWO, thermal warpage, solder paste, creamy flux, solid flux coating, cold-welding-barrier

Author(s)
Fengying Zhou, Fen Chen, and Ning-Cheng Lee
Resource Type
Technical Paper
Event
IPC APEX EXPO 2019

Size Matters - The Effects of Solder Powder Size on Solder Paste Performance

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Solder powder size is a popular topic in the electronics industry due to the continuing trend of miniaturization of electronics. The question commonly asked is “when we should switch from Type 3 to a smaller solder powder?” Solder powder size is usually chosen based on the printing requirements for the solder paste. It is common practice to use IPC Type 4 or 5 solder powders for stencil designs that include area ratios below the recommended IPC limit of 0.66. The effects of solder powder size on printability of solder paste have been well documented.

The size of the solder powder affects the performance of the solder paste in other ways. Shelf life, stencil life, reflow performance, voiding behavior, and reactivity / stability are all affected by solder powder size. Testing was conducted to measure each of these solders paste performance attributes for IPC Type 3, Type 4, Type 5 and Type 6 SAC305 solder powders in both water-soluble and no clean solder pastes. The performance data for each size of solder powder in each solder paste flux was quantified and summarized. Guidance for choosing the optimal size of solder powder is given based on the results of this study.

Key words: solder powder size, solder paste performance, solder paste printing, reflow, voiding, solder paste stability

Author(s)
Tony Lentz
Resource Type
Technical Paper
Event
IPC APEX EXPO 2014