Constant increases in feature density of printed circuit board assemblies (PCBA) has highlighted the importance of functional circuit test (FCT) systems in a manufacturing process. Automated FCT has traditionally been an expensive and complicated aspect of a product development, and it often requires significant engineering time to develop. This development cost rises as more features are added. In this paper we present simple methods to reduce FCT development time and cost through the use of modular fixtures and with fully integrated test equipment. These methods have reduced capital costs by up to70% and reduced fixture development time by unto50%. Additionally, we present modern design techniques and considerations which, when combined with modular fixtures improve FCT reliability, ease replication, and increase operational efficiency in high-mix, low-to mid-volume manufacturing test environments.

IoT and 5G applications have theirchallenges when it comes to functional testing –especially for the probing part inside a functional test fixture(hereinafter referred to as “FCT” fixture).In this paperwe would like to demonstrate how to successfully use passive coaxial probes for power level and other tests of IoT and 5G devices. Data rates are fast and especially for 5G frequencies can be pretty high up in the GHz range which makes the use of conventional spring-loaded probes very difficult if not impossible (very short fine-pitch probes or on-wafer architectures would need to be used). Design engineers, production line engineers and test probe manufacturers must work hand in hand for a successful end-of-line test.

For IoT applications, the manufacturers are further challenged with a need for low-cost test probes which poses a risk because cheaper test solutions quite often are not well impedance-defined which could add additional losses to the test –and worst-case lead to false errors. For 5G applications the cost is not the main driver but traditional spring-loaded concepts sometimes would not work at all for more critical measurements –the higher the frequency the greater the impact of mechanical properties is on the electrical performance.

We present a holistic concept for using test probes for these applications and focus on various different topics such as design for test, RF probing challenges, ideas to manufacture probing solutions at a rather low cost, usage of novelty non-conductive probes and its benefits over regular conducted testing and so on. The paper will be of interest for many different groups. The audience will learn how to select more economy priced but high-quality parts for IoT testing, PCB design engineers will learn how to successfully lay out test points for RF probing and production line test engineers will learn which RF probing concepts are out there already and what is being worked on “behind the scenes”.  Please note that we will not discuss any “Over-The-Air” (OTA) technologies in detail but focus on conducted testing for the presented applications.

There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second(Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument calleda synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and “synthesized” into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0(running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.

Microvias connect adjacent copper layers to complete electrical paths. Copper-filled microvias can be stacked to form connections beyond adjacent copper layers. Staggered microvias stitch adjacent copper layers with paths that meander on the layers between the microvias. Both microvia configurations are formed by essentially the same sequential operations of laser drill, metallization, and patterning, using various chemical, mechanical, and thermal treatments to form each layer, one over the other. Stacked microvias must be filled while staggered microvias do not. Process specifics differ manufacturer to manufacturer. Stacked microvias fracture while staggered microvia do not during reflow assembly. Assembly reflow subjects the printed wiring board (PWB) to the greatest temperature excursion. Stacked microvias with a weak interface fracture during assembly reflow and are a hidden reliability threat. This phenomenon was reported in IPC-WP-0231 in May of 2018. IPC-TM-650 Method 2.6.27A is a performance based PWB acceptance test that detects fractured microvias. SEM pictures are presented to initiate discussions in the search for root cause. Included are cross-section pictures of completed microvia structures, SEM pictures after laser drill, and after electroless copper. Not all stacked microvias fail. To learn why, microvia samples were collected from different PWB suppliers. Microvias drilled by UV lasers are compared to microvias drilled by other laser configurations. The pictures show that microvia structure was influenced by laser type. This paper discusses the various laser drilled microvias and presents SEM photographs to begin the search for the root cause of weak copper interface.

The PWB industry needs to complete reliability testing in order to define the minimum copper wrap plating thickness requirement for confirming the reliability of PTH structures.  Predicting reliability must ensure that the failure mechanism is demonstrated as a wear-out failure mode because a plating wrap failure is unpredictable.  The purpose of this study was to quantify the effects of various copper wrap plating thicknesses through IST testing followed by micro sectioning to determine the failure mechanism and identify the minimum copper wrap thickness required for are riable PWB.  Minimum copper wrap plating thickness has become an even a bigger  concern since designers started designing HDI products with buried vias, microvias and through filled vias all in one design.  PWBs go through multiple plating cycles requiring planarization after each plating cycle to keep the surface copper to a manageable thickness for etching.  The companies started a project to study the relationship between Copper wrap plating thickness and via reliability.  The project had two phases.  This paper will present findings from both Phase 1 and Phase 2.

This paper introduces structural electronics technology enabling smart molded structures. It also presents a case for developing industry standards specific to structural electronics materials, processing and testing.  In the first part, we outline the benefits of structural electronics technology as well as the manufacturing processes. Smart molded structures are made by integrating and encapsulating printed electronics and standard electronic components within durable,3D injection-molded plastics. Structural electronics technology and processing differs significantly from conventional electronics. Thus, we describe how these differences influence component and materials certification for use within injection molded plastics. In the second part of the paper, we discuss the lack of suitable standards for structural electronics. Two technologies, bearing a resemblance to structural electronics, have standards. However, they do not cover all aspects and we see a need for further development.

Flexible hybrid electronics (FHE) refer to a category of flexible electronics that are made through a combination of traditional assembly process of electronic components with the high-precision ink printing technologies.  By integrating silicon components with printed inks and flexible substrates, FHE will revolutionize the IoT and wearable industries. With FHE, designers can create a heterogeneous electronic system that can be fully integrated with different sensors, lighter in weight, more cost effective, more flexible and conforming to the curves of a human body or even stretchable across the shape of an object or structure—all while preserving the full functionality of traditional electronic systems.  However, many challenges remain. Industry is still at the early stage of developing and implementing FHE systems. A variety of design, assembly and reliability issues need to be evaluated and addressed. This paper will discuss these challenges and present a case study of making and evaluating FHE systems.

Key Words: Flexible Hybrid Electronics, FHE, Flexibility, Stretchability, Wearable, Printed electronics, Conductive ink.

Inherent variation among human brains causes difficulty in the design of electroencephalography (EEG)-enabled universal brain-machine interfaces (BMI). Existing EEG systems suffer from inconsistent signal quality, while requiring many rigid wires and metal electrodes on a hair cap. Although recent machine learning techniques offer a simpler EEG arrangement with fewer electrodes, these EEG devices still involve intrusive and heavy headgear, equipped with separate non-portable electrical hardware. Here, we introduce a fully portable, wireless, flexible hybrid system on a soft elastomeric membrane, which represents an ergonomic, comfortable, long-term wearable BMI. Additive manufacturing, based on aerosol jet printing, fabricates an ultrathin, open mesh electrode that can be mounted on the skin for biopotential recording, while a wireless electronic circuit is manufactured by the combination of material transfer printing and hard-soft materials integration. These imperceptible soft electronics incorporates a nanomembrane electrode on non-hair-bearing skin, flexible electrodes on hair-bearing scalp, and flexible circuit on the neck for wireless data acquisition. Analytical and computational studies of materials and mechanics establish the fundamental design criteria of the flexible, skin-like hybrid electronics (SHE), which enables seamless, portable EEG recording with significantly enhanced signal quality over commercial systems. With six human participants, this portable system achieves the most efficient information transfer rate (111.75 ± 1.15 bits per minute per channel). An in vivo demonstration of the SHE-enabled BMI shows precise, low-latency control of a wireless wheelchair via two-channel EEG.

The technical and economic benefits derived from lowering the reflow temperatures have motivated the evaluation of new Sn-Bi low temperature alloys for soldering. Eutectic Sn-Bi alloy is usually described as having a brittle nature, not being able to sustain mechanical shock and thermal cycling stresses as well as Sn3Ag30.5Cu (SAC305)solder. A new non-eutectic Sn-Bi solder with 2 wt.% additives(generally called here as alloy A) is evaluated here and compared with other eutectic Sn-Bi alloys and SAC305.Tensile tests at -55oC, -25oC, +25oC, +75oCand +125oC were performed to provide insights on their relative mechanical properties. Mechanical drop shock tests of BGA84 and LGA84 were performed as pertheJESD22-B111 standard, while thermal cycling tests were performed from -40oC (10 min) to +125oC (10 min) as per the IPC 9701 standard. The BGA84 was used for thermal cycling in situ monitoring, while BGA169, SOT223, QFP44 and 1206 chip resistors were also used for evaluating the effect of thermal cycling on IMC thickness, shear strength and tin whiskers. The results show that, for the aforementioned packages, assembly and testing conditions, alloy A is a viable replacement for SAC305. The joints formed with alloy A have the mechanical (drop) shock and thermal cycling performance as good as, or, in some cases, better than the same joints formed with SAC305.

Key words: lead-free, low temperature soldering, thermal cycling, mechanical drop shock, shear strength, tin whiskers.