Assembly Challenges of Die and Die-Size BGAs
This paper presents assembly challenges of mixed area array technologies covering Very Thin ChipArray® Ball Grid Array (CVBGA) and its Land Grid Array version (CV-LGA), embedded Wafer Level Land Grid Array (eWLP-LGA), and Copper-Pillar Flip-Chip (CP-FC) die—all with daisy-chain patterns to enable thermal cycle reliability monitoring for solder-joint failure evaluation. Twenty-seven (27) PCBs were assembled with a large number of variables in the design of experiment (DOE) to address: (1) assembly of mixed die and die-size array, (2) the effect of daisy-chain patterns on top layer or second layer bymicrovia-in-pad connections, (3) the effect of underfilling on improving resistance to thermal cycling, (4) challenges of single--and double-sided assembly processes, and (5) the effect of double-sided assembly on thermal cycle reliability. Acceptable assemblies with and without underfill were subjected to thermal cycling between –40°C and 125°C for solder-joint reliability characterization and failure-mechanism assessments. The paper will present details of DOE assembly parameters with the status of thermal cycle evaluation.
KEY WORDS: ball grid array, BGA, chip array BGA, embedded wafer level package, eWLP, land grid array, LGA,