Rapid incorporation of low cost, small footprint, and high efficiency BTC components with a large thermal plane and leadless terminations presents numerous challenges to the PCB manufacturers. Customers are demanding and many manufacturers are struggling to reduce voiding in the BTC assemblies to levels being asked for. Vacuum soldering has always been one answer for voiding.

Expensive equipment modification was introduced and proposed to reduce voiding. Many papers were published highlighting that, depending on application, voiding levels have little or no detrimental effect on solder joint reliability. Overall industry is struggling to come to consensus on the genuinely tolerable levels of voiding and different mitigation strategies.

This investigation has focused on direct comparison of two different alloys assembled both using conventional reflow process and vacuum soldering. Thermal cycling testing at -40C/+125C with 30 min dwell time was used to evaluate reliability performance of two different sizes of QFN assemblies. Test vehicle chosen for this work had 6 copper layers and includes two different sizes QFN components (MLF100 and MLF52). In all cases the same commercially available solder paste was printed with the same stencil (5 mil). Matching reflow profiles in conventional and vacuum reflow were used. Voiding of all assemblies were assessed. As expected, a drastic reduction in voiding was measured for vacuum soldered assemblies. Very unexpected reliability results were observed, highlighting potentially unintended consequences associated with vacuum soldering and void-free assembly.

Key words: solder joint reliability, vacuum soldering, voiding.

Many leading solder paste manufacturers are currently developing solder alloys for high reliability applications. These solder alloys are doped with elements such as bismuth (Bi), indium (In), and antimony (Sb), which improves the fatigue life and reduces the adverse effects of thermal cycling. This study investigated the effect of solder alloy on the reliability of Chip Array Ball Grid Array (CABGA) and Surface Mount Resistors (SMR) components in an accelerated thermal cycling test. Two types of components—15 × 15 mm CABGA208 and 2512 SMR—were assembled on a test vehicle using five different solder alloys: SAC305, SAC-3.3Bi, SAC-0.5Bi-6In, SAC-0.5Bi-1.4Sb-0.15Ni, and Sn63Pb37. The test board was made up of FR-4 material and included four copper layers. After the assembly, the boards were tested in a thermal cycler after 10 days of storage at room temperature. The thermal cycling profile included cycling between -40°C and +125°C with a ramp rate of 10°C/min and a dwell time of 15 min at maximum and minimum temperatures. The test was completed at 4718 cycles. The failure data were fitted to two-parameter Weibull curves. We used representative cross-sections to investigate the intermetallic compound (IMC)layer and the failure mode. The results showed that among CABGAs, doped Bi-based alloys performed the best, closely followed by SAC305. Among SMRs, SAC with 3% Bi alloys outperformed SAC305 and SnPb. We also observed that the IMC layer growth rate for SAC with Bi alloys was relatively low compared to SAC305. This was due to the presence of Bi, which retarded the propagation rate of the IMC layer.

Keywords: thermal cycling, lead-free, characteristic life, IMC layer

The soldering (wave, reflow, and selective) along with flux removal (cleaning) processes have for years been optimized to yield the best result possible. Today more than ever these processes are stressed by the continued trend toward miniaturization and increased power capability. To achieve increased electrical functionality and assembly miniaturization, the industry has increased the use of leadless and chip-scale packages including those with bottom terminations. It is widely understood that such assemblies tax the process of flux removal, but they also can present challenges to the soldering process.

The purpose of this research is to study how the use of atmospheric plasma and treatment can benefit the soldering, cleaning, and protection of electronic assemblies. The reliability of the test boards will be measured using surface insulation resistance (SIR). The specific researched areas include:

1.Atmosphere plasma treatment of the circuit card prior to the assembly process

2.Expose the assembled circuit cards to highly accelerated life testing (ALT)

3.Measure the SIR across bottom terminated components for both no-clean and cleaning processes

4.Void reduction of the bottom terminated thermal lug and pads

5.SIR on circuit cards that were conformally coated

6.Conformal coating dewetting with and without atmospheric plasma treatment

The test board for this research will be a SIR test board populated with QFNs, a hybrid surface mount/thru-hole connector, and capacitors. The data findings and inferences from the data findings will be presented.

Flip-chip technology has become increasingly prevalent within the electronics industry due to its lower cost, increased package density, improved performance while maintaining or improving circuit reliability, and increased I/O density. This technology is a method for interconnecting semiconductor devices such as IC chips and Micro-electro-mechanical Systems(MEMS) to external circuitry with solder bumps that have been deposited onto the chip pads. However, solder bump technology has proven to be problematic below 125μm pitch as it is challenging to manufacture and assemble. As pitch is reduced, both standoff height and joint reliability decrease, and the risk of shorts are increased.

Given this, traditional solder bumps are being replaced by copper pillar technology. Used as first-level interconnect, copper pillar technology is increasing in popularity. Copper pillar technology has been documented to be efficient to pitches of 80 μm and appears to be promising down to pitches of 40μm. Along with reduced pitch, copper pillar brings several other benefits, including improved electrical performance. This technology is becoming popular since it allows for smaller devices, greater control of standoff height and reduces the number of package substrate layers which reduces cost.

Devices utilizing copper pillar technology have more interconnects per surface area resulting in tighter pitch and lower standoffs heights. As standoff height reduces, flux residues have less area to outgas during reflow. For that reason, there is a critical need to investigate the conditions that would be required to successfully remove flux residues to ensure the functionality and reliability of the final product.

Flux residues can affect reliability, especially with respect to underfill in two different ways. Firstly, if present on the solder bump, substrate or die, thin films of flux residue can significantly reduce interfacial adhesion between the underfill and the surfaces. Once the underfilled device is stressed by thermal shock, humidity or other factors, the underfill delaminates from the surface, and a gap can be detected using acoustic microscopy. Secondly, fluxes can affect reliability by physically impeding the flow of underfill material. Flux residue buildup in the gap between bumps or between the die and the substrate can narrow the gap to a point where the underfill cannot flow or the edges flow faster, encapsulating air and creating a void. To ensure a void-free underfill, homogenous wetting of the underfill must occur on all surfaces. If wetting is not homogeneous, voids in the uncured underfill may translate into reliability problems later.

This study involved using straight DI-water and novel low-concentration alkaline cleaning agent on copper pillar bumped flip-chips. The challenge was to effectively clean flux residues underneath these components. The outcome of this study could provide a benchmark for conducting further studies involving bump pitch less than 15μm and denser packages including 2.5Ds and 3Ds.

The cleaning assessment methodologies employed analytical/functional testing including Fourier Transform Infrared Spectroscopy *FTIR(, Ion Chromatography, (Scanning Electron Microscopy/Energy Dispersive Spectroscopy (SEM/EDS), Thermal Cycling (TC) Test, Underfill Test, High Temp Storage Life (HTSL) Test and Moisture Sensitivity Level 3 (MSL-3) Testing.

Keywords: flip chip, Cu pillar, fine pitch, aqueous cleaning, assembly, reliability

Recently new semi-aqueous in-line cleaning machines (CM) were installed; however, the associated increased volumes of circuit card assemblies (CCAs) being cleaned after SMT surface mount technology assembly resulted in correspondingly more solder paste residue or “goo” building-up on cleaning machine wash / rinse tank surfaces and “gumming-up” sump-pumps, causing sensor failures and interrupting production. Moreover, what remains is very stubborn to remove during preventative maintenance (PM). This goo is attributed to the presence of a plasticizer or flux softening additive in the current solder paste, which is not very soluble in cleaning solutions, and which further concentrates in the non-volatile residues (NVR) or % solids that precipitate / accumulate on cooler surfaces, rather than rinsing away with the other flux constituents. The “no-clean” solder pastes initially used by commercial industry attributed excessive electrical probe test contact fails from the “hard” flux residues remaining on the test pads, since the no-clean solder pastes are not cleaned or removed from the test pads. As a result, a rubber-based softening agent was added to render the flux residue on test pads more probe penetrable for electrical testing. Conversely, the current manufacturing site cleans-off the “no-clean” solder paste flux residue required for subsequent conformal coating adherence for aerospace / defense applications, and therefore does not need a softened flux residue for probing, since the flux residue is cleaned-off the test pads before electrical testing. Solder pastes with and without the softening agent were comparatively evaluated for effects on solder paste volume printed and solder solidified after reflow, ionic cleanliness, solder-joint shear strength, microstructure, IMC intermetallic thicknesses and viscosity on test vehicles and production products.

Traditional Subtractive Etch (SE) processes used to manufacture Printed Circuit Boards (PCBs) are adequate for many of today’s circuit designs. However, certain parts of PCBs, and more generally, certain PCBs in their entirety, are reaching the lower limits of signal conductor line widths and spaces. Today, these dimensions are typically 75 μm / 75 μm (3 mils / 3 mils). New Semi-Additive Process (SAP) technologies can reach much smaller pitches, typically 25 μm trace plus 25 μm space (1 mil / 1 mil) and below. Because the design step precedes manufacturing, this paper will explore the unique challenges associated with designing for SAP fabrication and offers a framework for maximizing benefits. In a specific example, new SAP design guidelines have been applied to the layout of a reference design for a DDR4 SODIMM module. Benefits include: (i) narrowing the trace pitch to route more traces through the Ball Grid Array (BGA) patterns, (ii) reducing the number of layers, and (iii) decreasing the number of microvias. These efforts result in lower costs due to decreased board size and a lower layer count with fewer lamination cycles. Moreover, these modifications collectively should achieve higher reliability. The SAP layers may be combined with SE layers to build a single board. Examples will be shown in the DDR4 memory layout where the two processes can be used. This case study represents a natural first step in the transition to using new SAP technologies in next-generation PCB electronics.

This paper will discuss the evolution of the printed board design to date, how process improvements and new manufacturing technologies and chemistry have enabled the new step down in miniaturization. Herein will be described as the new Ultra High-Density Interconnect (Ultra HDI) product features and include design guidelines, design parameters, performance tolerances, test requirements and end user requirements for the final printed board.IPC has assigned Task Group D-33-AP to develop a guideline for the Ultra HDI level of printed boards, and the result of the D-33-AP activity will be the incorporation of new IPC standards for the design, performance, and acceptability of Ultra High Density printed boards.

This paper will discuss the difference between traditional advanced any layer HDI PCB with subtractive process and Ultra High-Density Interconnect (Ultra HDI) or substrate-like-PCB (SLP) with modified Semi-Additive Process (mSAP). The paper will explain the major market drivers for ultra HDI/SLP and the boundaries of each technology used to form fine conductors. The process flow difference and major manufacturing equipment used to manufacture the Ultra HDI/SLP will be discussed. The major design related considerations to use Ultra HDI/SLP technology and how normal advanced any layer HDI and Ultra HDI/SLP compare in terms of capability, reliability, and cost.

Complex geometries, customized parts and new processes; these are characteristics that are readily associated with additive manufacturing (AM). At the same time, they are often associated with high hurdles in terms of mass production, suitability for series production and reliability. The use of AM is already widespread in industries such as mechanical engineering, aerospace, automotive and medical technology.

What is the situation in the field of "classic" electronics and electronics manufacturing? Here, too, there are initial areas of application suitable for mass production and promising processes. Substrates for electronics are usually "multimaterial systems" (conductive & non-conductive). Appropriate printing systems and printers are today available, eCAD tools and data formats not.