The Connected Factory Exchange initiative enables the use of tools, machines, and computer software to monitor, improve, and produce reliable hardware. The concept of the Digital Twin is to connect and communicate with assembly machines to analyze data, and from the data analytics, adjust and control the process.

There are four basic types of digital twin applications. The first type is visual inspection where software takes the data to create, see, edit, and make changes to better optimize the process. The second type is computational by processing the data to find a solution. The third type is operational by using software to make real-time decisions as to how to control an operation. The fourth type is analytical by finding patterns in the data, which are associated to a particular outcome.

The Electrochemical Reliability of an electronic device can be impacted by flux and process residues that are accumulated during the assembly operation. The idea behind this research is the use of SMART test instruments that qualify and control process contamination to ensure that these devices will function when called upon in their end-use environment.

The purpose of the research is to perform Thermal-Humidity-Bias (SIR) and Specific Area Extraction Testing (SAET) process control testing. The idea is to pattern an Electrical Twin test coupon into the panel of production circuit boards. The Electrical Twin will be populated with components that are representative of the process that can leave behind flux or process residues that can cause a failure. SMART test instruments that are Digital Twin capable will be used to test the Electrical Twin test boards.

Technical Cleanliness, i.e., the quantification, control and mitigation of deleterious effects of foreign object debris (FOD), is a common challenge in engineering. In the context of electronic assemblies, FOD can cause deleterious effects related to manufacturing (e.g. mechanical obstruction during mating of connectors) as well as field performance (e.g. short circuits due to loose particles or reduced electrical clearances resulting in electrochemical migration failures). Drawings as well as specific standards thus often contain general requirements on cleanliness, stating essentially that assemblies shall be free of FOD in general or free of FOD exceeding a certain size. However, such a ‘zero/limited FOD’ approach is typically neither practical nor required in electronics manufacturing: FOD has various sources, ranging from environmental contamination on the shop floor to assembly components and materials, making an elimination of FOD on electronic assemblies a sheer impossibility. This paper provides the results of a thorough assessment of the state of the art of technical cleanliness in electronics manufacturing as well as assessments of cleaning methods including their capability limits. The various sources of FOD, as well as the statistically meaningful quantification of technical cleanliness by suitable analyses and metrics are discussed. The results indicate the existence of the so-called gap dilemma: If loose metallic particles capable of bridging non-common conductors on a given assembly would generally result in electrical failures, the modern world as we know it would come to a halt, as practically all electronics in the field do exhibit such particles. This gap dilemma is rationalized by introducing a risk assessment tool that can be used to calculate failures rates and to assess design changes and specification violations.

Resistance of Solvent Extract (ROSE) testing has been grandfathered not only into the modern IPC standards without validation on modern materials, but it has also become grandfathered into the industry's concept of electrochemical reliability. This is a surprising fact, considering it does not measure electrochemical reliability, it measures a property that is not even directly related to electrochemical reliability, but may have a correlation to it. Between these two factors, a critical evaluation of ROSE testing and its applicability to both its intended use (process control) and its frequent misuse (product acceptance) is needed.

In Part 1 of this research, which was published at SMTAI 2021 we examined the relationship between ionic contamination and ROSE results in the context of method validation. Part 1 helped to establish what the sensitivity of ROSE is, in terms of the minimum amount of contamination required for a statistically valid response, as well as the nature of the response function of ROSE to changes in input (e.g., slope of a linear function).

In this follow-on work, we compare these metrics of the ROSE test method to those of SIR, with the goal of determining the relationship between changes in ROSE data and the corresponding change in electrochemical reliability, as measured by SIR. One illustrative example of the relationship between ROSE and SIR which we wish to explore is how much the ROSE data can vary before a shift in SIR or Electrochemical Migration is observed. This information would be critical to evaluating the use of ROSE testing for process control. Furthermore, combining the data from Part 1 we aim to observe what, if any, danger there is in using ROSE values as a criterion for product acceptance.

The industry is moving toward using exotic dielectric materials with a very low loss tangent to improve insertion loss performance. This leads to the result that the signal loss attenuation due to surface roughness of copper has become a dominant factor. A lot of attention has been on the smoothness of copper foil, while one of the often-overlooked aspects in design is how the copper surface treatment during the PCB fabrication can impact the insertion loss.

In this paper, several electrical test coupons were built with two types of surface treatments, using a 16-layer PCB stack-up commonly seen in datacenter systems. The two types of surface treatments include a low-etch oxide system that has been recently deployed in the industry for high volume manufacturing, and a non-oxide approach with an advanced alkaline aqueous surface treatment formulation for the bonding of copper to prepreg material. Different PCB materials and copper foil types are included in the investigation. It is shown that the non-oxide surface treatment can yield up to 7.6% additional insertion loss reduction, compared to the commonly used low-etch oxide treatment, which is already much better than today’s commonly used brown oxide system. High-resolution cross-sectional analysis was done to reveal how the surface treatment changes the copper profile during the lamination process.

Key words: Insertion Loss, non-oxide, alkaline surface treatment, surface roughness, copper foil

The euphoria associated with the biggest technological step in the field of telecommunications in recent history, the new 5G mobile communications standard, not only made it necessary for OEMs to adopt this technology to keep up with the competition, but also shaped new requirements regarding the production of communication device circuit boards in order to be able to exploit the full potential of this and similar technologies.

In order to approximate this objective, it is essential that noise, distortion and losses of data signals are significantly reduced, since these parameters represent the controllable framework conditions of a telecommunication device, which are directly related to performance losses in terms of transmission speed, reception range and latency. However, common adhesion promoters used in several process steps in the manufacturing of classical PCBs, MLBs and HDI circuit boards are to some extent causing these problems due to the nature of their work mechanism – surface roughening. While these effects played a negligible role at lower frequencies, they now take center stage as distortion, losses and noise amplify with an increasing frequency and roughness. As a solution to this problem, the industry is primarily focused and eager to develop new dielectric materials and non-etching adhesion promoters for inner layer bonding applications. However, further opportunities exist in other production steps, where the signal integrity can still be improved by displacing commonly used micro-etching surface pretreatments for solder-mask and photoresist adhesion with low or non-etching alternatives. Unfortunately, this leads to a subsequent problem, namely lower adhesion, and low production yield due to a weaker mechanical bond.

This work describes the functional principle of a novel, anisotropic, nano-copper engraving, photoresist pretreatment for multilayer and advanced HDI PCBs. It is designed to optimize the signal integrity especially for high frequency applications, while ensuring excellent adhesion. This is done by a two-step surface treatment process, which involves an ordinary cleaner to remove mild oxidation and a special anisotropic conditioner, which selectively engraves nano cavities in z-direction, while maintaining the integrity of the surface dimension. The data indicates that this method can in fact combine the benefits of classical micro-etching and newer non-etching solutions and seems to be a viable addition to the high frequency PCB production process.

Key words: High frequency, micro-etching, adhesion promotor, signal integrity, semi additive process, dry film, photoresist, nano-engraving

The results of a NextFlex project addressing barriers that are preventing inkjet printing from being adopted for prototyping and volume manufacturing of printed circuits, are presented. These barriers include resolution, thickness, reliability and endurance. Silver conductive nanoparticle inks were evaluated with Konica Minolta 512-SH industrial printheads using the PiXDRO LP50 printer platform. These 512-nozzle printheads have a nominal drop volume of 4 picoliters, which corresponds to a drop diameter of ~20 um. The focus was on determining process parameters that enabled printing of narrow and continuous traces in both the in-scan and out-of-scan directions. Treatment of the substrate by wiping with isopropanol, and varying the substrate temperature, drop spacing and printing speed were investigated, and resulted in the demonstration of two silver conductor print settings, for an ink that was developed for this printhead. Trace widths of 50-60 um and 60-70 um were demonstrated on PET substrates at 70 °C substrate temperature for 1-pixel-wide lines in the in-scan and out-of-scan directions, respectively, while diagonal traces were even narrower. The trace width could be controlled by having traces with 1, 2 or 3 pixel width. The resistivity of the annealed traces was determined to be ~2 times that of bulk silver, with excellent adhesion to the PET substrate. When printing with a new printhead and ink, even very narrow traces were printed with high yield. Procedures were establishedfor achieving reliable operation of the ink and printhead over 6 months, after which nozzles began to become non-jetting. Finally, inkjet printing of the NextFlex A15 Arduino-Compatible Microcontroller was successfully demonstrated, including the die-attach section, which has the narrowest features and spacing. This indicates that inkjet could potentially replace screen printing and laser machining processes that are currently used for printing this device.

The emergence of a variety of flexible portable electronics applications has led to increased attention to flexible power sources. Flexible electronics may be subjected to static and dynamic folding during operation in wearable applications that require attachment of applique skin-patch or integration of electronics into wearable garments. Power sources capable of sustaining static and dynamic stresses of daily motion without significant degradation in the battery capacity while subjected to various depths of charge for several charge-discharge cycles are needed for FHE applications. While the reliability of thick lithium-ion batteries has been previously studied for effect of C-rates and operating temperatures, the effect of static and dynamic U-flexing of thin lithium-ion power sources on the battery cycle life is not well understood. In this research study, the combined effects of deep and shallow depths of charge, static-folding, dynamic-folding and twisting load(s), under varying fold orientations and varying C-rates have been characterized for thin-flexible Li-Ion batteries. The lithium-ion batteries studied are less than 1mm in thickness. Effect of cathode chemistries including NMC and LCO have been examined on performance and reliability. Output parameters such as battery capacity and its degradation have been analyzed for battery state assessment. The use of lamination for thin-flexible battery integration has also been studied and compared with non-laminated batteries. Effect of lamination process conditions on the peel strength and the charge-discharge cycling degradation has been quantified. Laminated batteries have been subjected to static and dynamic fold tests as well so as to investigate the combined effect on capacity degradation. Finally, a life-prediction model has been developed for used in estimation of the battery capacity deterioration as a function of number of cycles, operating temperature, and depth-of-discharge. The model can be used to compute acceleration factors between accelerated test conditions and use-conditions. In addition, the model can be used to compute the needed test levels to assure reliability for typical use-cases.

Printed conductors and interconnects on compatible flexible or stretchable substrates are the foundation of flexible hybrid electronic systems that may include conventional silicon-based devices, discrete components, and printed radio frequency components such as microstrip lines, coplanar waveguides, capacitors, inductors, and antennas. The choice of substrates, inks, printing methods, encapsulants and post printing processes are often dependent on the application and its concept for operation. The development of reliable flexible hybrid electronics devices and systems require fundamental understanding of their behavior under different conditions.

In this paper, the performance of printed FHE components on flexible/stretchable substrates under mechanical and environmental stresses is discussed. Selected examples from studies of printed interconnects on compliant substrates are presented. Understanding the electromechanical behavior of FHE components and systems as they are exposed to small, moderate, and high repetitive strains, the impacts of handling during manufacturing, storage, and usage in thermal or isothermal conditions will ultimately lead to the creation of standard tests, expectations for reliable performance and FHE systems lifetime.

Keywords: Flexible hybrid electronics (FHE), electromechanical testing, printed electronics

This paper summarizes recent progress on utilizing liquid metals (LMs) consisting of gallium and gallium alloys for the electronics industry. While gallium is a component of existing electronic materials – such as semiconductors including Ga2O3, GaAs, and GaN – here the focus is on Ga in the liquid, metallic state. As the name implies, liquid metals uniquely combine many of the desirable attributes of metals and liquids1. Metals are fantastic thermal and electrical conductors. Liquids are soft, deformable, and can be manipulated in ways that simply are not possible with solids. Combined, these properties enable some truly unique applications for electronics including stretchable electronics2, self-healing circuits3, 3D printing4–6, and thermal interface materials.

Via-in-Pad Plated Over (VIPPO) designs enable better signal quality and speed, but also cause unintended consequences. At VIPPO locations, with or without a solid copper-filled hole, the coefficient of thermal expansion (CTE) is typically around 17ppm/°C, which is significantly lower than that of the nearby non-VIPPO joints, which are approximately 45ppm/°C. For a double-sided printed wiring board (PWB), the difference in the CTE of the neighboring pads during heat rise in the second reflow could result in excessive tension on the joint at the VIPPO pad site, consequently resulting in a hot tear (HT) defect before reaching the melting point of the solder joints. An epoxy flux (EF) was developed to eliminate HT problems. Dipping EF does not work due to insufficient EF volume pickup and/or too much variation in the volume of the EF picked up. Dispensing EF exhibits good wetting and low voiding and also allows a sufficient volume of EF to fill the gap between the BGA and PWB, thus enabling a strong bonding force to nullify the ΔCTE factor, consequently eliminating the HT defect. The EF developed has the epoxy stress balanced around the solder joints and avoids joint drifting and solder extrusion problems. It cures fully in the reflow process and is not tacky upon touch. Commercial underfills that were tested did not work on preventing HTs from occurring due to joint drift and solder extrusion problems. Compared to other polymeric reinforcement materials, the EF dispense process minimizes the process steps; hence it has a lower cost solution than other reinforcement approaches.

Keywords: epoxy flux, hot tear, VIPPO, BGA, PWB