The 2017 International Electronics Manufacturing Initiatives (iNEMI) Board and Assembly Roadmap had forecast a 20% adoption rate of low-temperature solders (LTS) for board assembly by 2027. BiSn solders are the leading low-temperature candidates. However, the intrinsic brittleness of Bi restricts BiSn solders from drop-critical applications. An In-containing Sn-rich solder paste, referred to in this paper as "DFLT,” developed with a mixed powder technology—allows for reflow as low as 200°C, and shows excellent drop shock performance (comparable to or even better than traditional SAC305 [1]). DFLT has been successfully used in step soldering to interconnect two PCBs, pre-reflowed with traditional SAC solders, through an interposer in 5G mobile phone applications. A new generation of low-temperature lead-free solder pastes are being studied, targeted at further reducing the reflow peak temperature to 190°C while maintaining the drop shock performance and the thermal cycling reliability. One of the leading candidates, “874-71-1,” reflowed with either a 190°C or 200°C peak profile, has shown a comparable drop shock performance to DFLT (reflowed with a 200°C peak profile), which is at least two-orders-of-magnitude better than that of the eutectic BiSnAg. Both 874-71-1 (190°C and 200°C peak reflow) and DFLT(200°C peak reflow)have shown a similar characteristic life in the BGA192 thermal cycling test (-40/125°C), which is comparable to SAC305. The shear force of the 0805 chip resistor for DFLT (200°C peak profile), 874-71-1 (both 190°C and 200°C peak profiles) and SAC305 (245°C peak profile) become comparable after 2000 cycles TCT, although DFLT was stronger than 874-71-1 before TCT.

Key words: lead-free, solder, drop shock, low-temperature solder, mixed powder paste

Two challenges that advanced packaging suppliers are faced with during IC substrate fabrication are meeting the copper plating performance requirements and reducing manufacturing process costs. The copper plating must provide both high resolution and strict height uniformity within unit (WIU) and within a die/panel (WID). Plated features such as fine lines and pillars, whose top shape and coplanarity are critical to the product quality. A non-planar surface could result in signal transmission loss and introduce weak points in the connections. Therefore, copper plating solutions providing uniform, planar structures, that don’t require any special post treatment are highly desirable features for both redistribution layer (RDL) and pillar plating processes. The copper plating solution can also reduce cost by plating two or three types of features in a single step or from a single process bath. This flexibility allows fabricators to save on space and equipment.

In this paper, an electroplating (EPP) package, , is introduced to plate both RDL and pillars under different current densities in vertical continuous platers (VCP). The plating uniformity and coplanarity of both RDL fine lines and pillars was evaluated on a panel level.

The EPP package offered excellent coplanarity within a pattern unit for RDL plating. The variation in the plated height (or thickness) between fine lines and pads, of 5 and 50 μm widths respectively, was below 1.0 μm when using a current density of1.5 A/dm2 (ASD) for 66 minutes. For 10 μm wide lines, the plated copper thickness variation can be below 0.5 μm. The variation of plated thickness across 410 mm x 510 mm panels was below 1.0 μm, when the plated panel was measured at 3 points (top, middle, and bottom). The tops of the fine lines have defined, rectangular shapes. These types of profiles have excellent conductivity.

For pillar plating under higher current density, such as 5-10 ASD, the top of the pillars had slightly domed profiles. The pillars were very uniform within the die and within the panel.

Physical properties of the plated copper deposit are essential for the reliability of the finished product. A few key physical properties are tensile strength, elongation %, and internal stress. These properties show the tolerance of the deposit for thermal stress and warpage. The additives (wetter, leveler, and brightener) strongly influence the physical properties of the deposit. Copper deposited with the EPP package has tensile strength above 40,000 psi, elongation % above 18%, and internal stress below 1.0 Kg/mm2. The physical properties of the deposited copper did not change considerably during the bath aging, showing that the package has stable performance.

The reliability of both pillars and RDL features were evaluated via solder dip. The RDL features were dipped at 288°C, 6 times. The pillars were dipped at 288°C, 60 times. Neither feature showed any cracks or separation from the substrate.

For many years, the electroless copper process has been widely used by the PCB and package substrate industries, where a wide process window and proven product reliability has led to it being considered as the “industry standard” as a means of facilitating multilayer PCBs.

While there have been numerous incremental changes to improve overall capability and further widen its application range, the process as a whole may be considered by many to have remained “virtually unchanged”. Typically, an electroless copper process contains three major application steps, the “desmear” removes unwanted resin residues following the previous drilling operations, followed by a Palladium based “activation” which facilitates the subsequent “electroless copper “deposition. The performance and stability of the above general process has been widely reported, although one “issue” that to date remains unresolved, has been the identification of viable alternatives to Pd based activation. Such activator chemistries have seen a steady increase in their costs, up to the situation today, where Pd metal costs have become an appreciable contributor to overall electroless copper process costs. There have been some publications investigating alternatives to Pd, typically based on silver or copper, yet none appear to have been sufficiently successful to achieve any level of industrial acceptance.

In this paper, we discuss the technical issues that have been overcome in order to develop an activator system that is based on copper colloids. This solution has been shown to offer a process stability that has not been achieved with previous Cu based activation steps, where due to colloid agglomeration and/or oxidation, unacceptably short solution lifetimes have been encountered. We also characterize this fully Cu based process on a range of PCB and package substrate relevant dielectric materials, in order to demonstrate that the electroless copper process as a whole remains comparable to one using the existing Pd based technology, with no loss in physical or thermo-mechanical performance.

The High Density Packaging (HDP) user group has completed a project to evaluate dielectric conditions impacting the reliability of backdrilling escape vias under BGA via arrays. Large BGA sites are characterized by high density routing channels and finer pitch arrays of BGA escape vias. Backdrilling in these areas requires accurate drilling of the primary plated through vias and accurate secondary drilling or backdrilling to minimize the risk of incomplete removal of plated copper that could retain copper residues along the backdrilled surface. Backdrilling of the finer pitch via arrays also require well controlled board layer to layer registration to prevent exposing adjacent copper features and ensure sufficient dielectric encapsulation between the backdrilled via edge and copper inner layers1,2. This work evaluated the impact and risk of different levels of dielectric encapsulation after backdrilling by evaluation of three different backdrill process flows, a range of backdrill edge to adjacent copper spacings, and four different hole fill conditions. These parameters were evaluated and correlated with the following critical backdrill failure modes:

•Incomplete removal of plated copper within the via hole due to backdrill misregistration (copper wicking/ striping)

•Electrochemical migration between copper layers affected by backdrill misregistration, remaining residue, and laminate material manufacturing (temperature/humidity/bias testing per IPC TM-650, 2.6.25)

•Insufficient plating removal by backdrilling

This project aimed to determine the backdrill design parameters and PCB Fab manufacturing processing needed to ensure sufficient reliability of backdrilled BGA escape vias.

Key words: Backdrill, Electrochemical Migration, Backdrill to metal Isolation, Exposed Copper

The number of components and functionality on a printed circuit board increases continuously. Surface mount device (SMD) components become smaller, pitch dimensions shrink, but there are still some through-hole components used on most assemblies. All classes from high-reliability to consumer electronics have through-hole connections. For high-reliability products more expensive materials may be used compared to low-cost consumer electronics. This not only counts for board materials and component selection but also for the solder alloys in a selective solder process. Solder alloys are designed for SMD applications. Some of them have multiple elements to increase reliability. Sn3.0Ag0.5Cu has been the standard lead-free alloy for a decade or more. There are two drawbacks of this alloy:

1.Not reliable enough for high-reliability applications.

2.Too expensive for consumer products.

Under-the-hood and around the engine applications in automobiles require high-reliability electronics. These components have operation temperatures from -40°C to +150°C. A standard Sn3.0Ag0.5Cu is not good enough. Three specially designed high-reliability alloys were used in a point-to-point soldering machine to see how stable their composition is and how robust their solder process.

For consumer electronics there is a different trend with respect to solder alloys. Low-temperature solders are of increasing interest for several reasons. Lower solder temperatures allow the use of cheaper materials and are less susceptible to warpage in reflow processes. These solders are SnBi based, and the absence of Ag makes them less expensive. The alloys have a larger melting range. How this affects the selective process is part of the study. Four different test-boards were used to investigate the robustness of the different alloys in a selective soldering process. The goal of these tests was to define the process windows of the alloys. Hole filling, bridging, solder balls, and open joints were quality characteristics for different Design of Experiments. The hole filling of over 18,000 through hole components were measured for high thermal mass boards as well as thin double layer boards. In two of the tested alloys, the composition of the alloy changed over time. Frozen solder and (Cu, Ni)6Sn5 needles were found during the experiments. Cross sections of the through-hole connections were made to measure the intermetallic thickness at different temperatures and solder conditions. The performance of six new lead-free alloys is compared to Sn3.0Ag0.5Cu.

Rapid incorporation of low cost, small footprint, and high efficiency BTC components with a large thermal plane and leadless terminations presents numerous challenges to the PCB manufacturers. Customers are demanding and many manufacturers are struggling to reduce voiding in the BTC assemblies to levels being asked for. Vacuum soldering has always been one answer for voiding.

Expensive equipment modification was introduced and proposed to reduce voiding. Many papers were published highlighting that, depending on application, voiding levels have little or no detrimental effect on solder joint reliability. Overall industry is struggling to come to consensus on the genuinely tolerable levels of voiding and different mitigation strategies.

This investigation has focused on direct comparison of two different alloys assembled both using conventional reflow process and vacuum soldering. Thermal cycling testing at -40C/+125C with 30 min dwell time was used to evaluate reliability performance of two different sizes of QFN assemblies. Test vehicle chosen for this work had 6 copper layers and includes two different sizes QFN components (MLF100 and MLF52). In all cases the same commercially available solder paste was printed with the same stencil (5 mil). Matching reflow profiles in conventional and vacuum reflow were used. Voiding of all assemblies were assessed. As expected, a drastic reduction in voiding was measured for vacuum soldered assemblies. Very unexpected reliability results were observed, highlighting potentially unintended consequences associated with vacuum soldering and void-free assembly.

Key words: solder joint reliability, vacuum soldering, voiding.

Many leading solder paste manufacturers are currently developing solder alloys for high reliability applications. These solder alloys are doped with elements such as bismuth (Bi), indium (In), and antimony (Sb), which improves the fatigue life and reduces the adverse effects of thermal cycling. This study investigated the effect of solder alloy on the reliability of Chip Array Ball Grid Array (CABGA) and Surface Mount Resistors (SMR) components in an accelerated thermal cycling test. Two types of components—15 × 15 mm CABGA208 and 2512 SMR—were assembled on a test vehicle using five different solder alloys: SAC305, SAC-3.3Bi, SAC-0.5Bi-6In, SAC-0.5Bi-1.4Sb-0.15Ni, and Sn63Pb37. The test board was made up of FR-4 material and included four copper layers. After the assembly, the boards were tested in a thermal cycler after 10 days of storage at room temperature. The thermal cycling profile included cycling between -40°C and +125°C with a ramp rate of 10°C/min and a dwell time of 15 min at maximum and minimum temperatures. The test was completed at 4718 cycles. The failure data were fitted to two-parameter Weibull curves. We used representative cross-sections to investigate the intermetallic compound (IMC)layer and the failure mode. The results showed that among CABGAs, doped Bi-based alloys performed the best, closely followed by SAC305. Among SMRs, SAC with 3% Bi alloys outperformed SAC305 and SnPb. We also observed that the IMC layer growth rate for SAC with Bi alloys was relatively low compared to SAC305. This was due to the presence of Bi, which retarded the propagation rate of the IMC layer.

Keywords: thermal cycling, lead-free, characteristic life, IMC layer

The soldering (wave, reflow, and selective) along with flux removal (cleaning) processes have for years been optimized to yield the best result possible. Today more than ever these processes are stressed by the continued trend toward miniaturization and increased power capability. To achieve increased electrical functionality and assembly miniaturization, the industry has increased the use of leadless and chip-scale packages including those with bottom terminations. It is widely understood that such assemblies tax the process of flux removal, but they also can present challenges to the soldering process.

The purpose of this research is to study how the use of atmospheric plasma and treatment can benefit the soldering, cleaning, and protection of electronic assemblies. The reliability of the test boards will be measured using surface insulation resistance (SIR). The specific researched areas include:

1.Atmosphere plasma treatment of the circuit card prior to the assembly process

2.Expose the assembled circuit cards to highly accelerated life testing (ALT)

3.Measure the SIR across bottom terminated components for both no-clean and cleaning processes

4.Void reduction of the bottom terminated thermal lug and pads

5.SIR on circuit cards that were conformally coated

6.Conformal coating dewetting with and without atmospheric plasma treatment

The test board for this research will be a SIR test board populated with QFNs, a hybrid surface mount/thru-hole connector, and capacitors. The data findings and inferences from the data findings will be presented.

Flip-chip technology has become increasingly prevalent within the electronics industry due to its lower cost, increased package density, improved performance while maintaining or improving circuit reliability, and increased I/O density. This technology is a method for interconnecting semiconductor devices such as IC chips and Micro-electro-mechanical Systems(MEMS) to external circuitry with solder bumps that have been deposited onto the chip pads. However, solder bump technology has proven to be problematic below 125μm pitch as it is challenging to manufacture and assemble. As pitch is reduced, both standoff height and joint reliability decrease, and the risk of shorts are increased.

Given this, traditional solder bumps are being replaced by copper pillar technology. Used as first-level interconnect, copper pillar technology is increasing in popularity. Copper pillar technology has been documented to be efficient to pitches of 80 μm and appears to be promising down to pitches of 40μm. Along with reduced pitch, copper pillar brings several other benefits, including improved electrical performance. This technology is becoming popular since it allows for smaller devices, greater control of standoff height and reduces the number of package substrate layers which reduces cost.

Devices utilizing copper pillar technology have more interconnects per surface area resulting in tighter pitch and lower standoffs heights. As standoff height reduces, flux residues have less area to outgas during reflow. For that reason, there is a critical need to investigate the conditions that would be required to successfully remove flux residues to ensure the functionality and reliability of the final product.

Flux residues can affect reliability, especially with respect to underfill in two different ways. Firstly, if present on the solder bump, substrate or die, thin films of flux residue can significantly reduce interfacial adhesion between the underfill and the surfaces. Once the underfilled device is stressed by thermal shock, humidity or other factors, the underfill delaminates from the surface, and a gap can be detected using acoustic microscopy. Secondly, fluxes can affect reliability by physically impeding the flow of underfill material. Flux residue buildup in the gap between bumps or between the die and the substrate can narrow the gap to a point where the underfill cannot flow or the edges flow faster, encapsulating air and creating a void. To ensure a void-free underfill, homogenous wetting of the underfill must occur on all surfaces. If wetting is not homogeneous, voids in the uncured underfill may translate into reliability problems later.

This study involved using straight DI-water and novel low-concentration alkaline cleaning agent on copper pillar bumped flip-chips. The challenge was to effectively clean flux residues underneath these components. The outcome of this study could provide a benchmark for conducting further studies involving bump pitch less than 15μm and denser packages including 2.5Ds and 3Ds.

The cleaning assessment methodologies employed analytical/functional testing including Fourier Transform Infrared Spectroscopy *FTIR(, Ion Chromatography, (Scanning Electron Microscopy/Energy Dispersive Spectroscopy (SEM/EDS), Thermal Cycling (TC) Test, Underfill Test, High Temp Storage Life (HTSL) Test and Moisture Sensitivity Level 3 (MSL-3) Testing.

Keywords: flip chip, Cu pillar, fine pitch, aqueous cleaning, assembly, reliability