Printed Circuit Structures (PCSs) have the potential to revolutionize next generation printed circuit boards (PCBs) and electronics packaging. Almost every product available today contains sensors, electronics and radios and the growth of the Internet of Things (IoT) is one of the driving forces for this. The circuits are composed of traces, vias, passive components, active components, antennas and more. The PCB or flex circuit must then be inserted into or on an object, and if there are multiple circuits, wires are used to electrically connect them, and bolts and glue are used to mechanically secure them. The extra weight and volume required account for the mismatch in shape and the need to physically access the boards for assembly in the object will often mean the wasted volume for a circuit can be 100 to 1000 times larger than the circuit itself. PCSs have the potential to eliminate that wasted volume, reduce the weight, and increase the number of electronic functions per volume. Even more, the third dimension gives more degrees of freedom for circuit design and allows circuits to utilize physics more effectively than planar designs. We will present a timeline for PCSs, the challenges in software, process and hardware, the advantages, state-of-the-art in PCS today, working demonstrations and the required improvements for PCSs to ultimately exceed the performance of traditional PCBs and flex circuits.

In the LIFT (Laser Induced Forward Transfer) technology, a material, evenly coated on a transparent carrier film, passes under a laser. The laser applies a short burst of energy to it. This releases perfectly consistent drops of material onto the substrate below. The material drops can then be sintered or cured inline, in the same machine. A great benefit is that this technology works for solder and polymers as well as for metals and ceramics. Multiple materials can be printed at the same time. This new technology opens the way to new advanced applications and the fabrication of innovative materials and novel applications. LIFT systems can work with many materials currently on the market and will also leave great freedom to innovate to both material engineers and chemists: they will be able to create products with significantly better properties than those achievable with current 3D printing technologies due to the low constraint requirement on the printed material. Viscosities can exceed 300,000 cPs and fillers of more than 40μm can be added. The current paper deals with one application of this technology, an innovative approach to manufacture circuit boards with the speed of printing.

In the last few years there have been concerns in the industry, especially in products requiring high reliability when using microvia structures. As a result, many fabricators have been mandating push back on very complex high layer count designs.

This has resulted in very conservative rules for designers to use based on the limitations of fabricator capability. Some fabricators have also struggled to ensure that even simple structures are built reliably and repeatably.

This study was designed to look at materials which would ensure that more complex structures could be built reliably. Thinner glass reinforced dielectric layers have been developed for build-up multilayer. These tend to be resin rich in order to flow and encapsulate heavier plated-up copper features. Thin fiberglass-reinforced dielectrics can have issues caused by the lack of flow of ceramic-filled resin from side to side through spread weave fiberglass. These resin rich and higher resin-to-glass ratio dielectric materials are less desirable for the manufacture of reliable stacked microvias in part due to their higher X, Y, and Z axis rates of expansion.

Current industry practice has been to limit designs to staggered microvias and 1-2 layers of stacked microvias. This study shows how a thin, non-reinforced dielectric layer can be used and optimized for stacked microvias that demonstrate solid thermal reliability up to 4 levels of high density interconnect (HDI). It also shows that there seems to be no indication yet of a ceiling on how many layers could be used.

The paper will cover

1) objectives of the study;

2) some of the properties of the material used;

3) tests and results;

4) discussion and conclusions as well as further studies.

Plated and filled microvias are a common feature in modern PCBs, so much so, that they are now considered as the industry norm as a means of achieving high-density designs for modern mobile devices. However, over the last five years or so, there has been growing concern regarding their long-term reliability performance when in a multiple stacked configuration.

Blind microvias (BMV) have potentially complex metallurgical structures, with multiple interfaces located around the target pad to via joint. Where reported, failure analysis typically identifies only two major types of crystal structures formed at the BMV base, yet there is little or no work which discusses how or why such structures have likely developed.

This paper reviews the observed microstructures typically found within filled BMVs and offers proposals on how such structures form. Immediately after deposition, and in the case of electrolytically formed Copper, for some time afterwards, plated layers have a fine nanocrystalline or amorphous structure, and typically undergo significant recrystallisation, which is critical in determining the properties of the final BMV. Herein, we outline “bottom up” and “top down” recrystallisation, which respectively lead to a fully epitaxial interface, or one with significant alignment of Cu-grain boundaries. Using a range of inspection techniques, we offer mechanisms by which such structures develop, which can typically be as a result of process related issues, or through the interaction with plating additives. We then discuss some preliminary results relating the two identified grain structures to mechanical BMV performance and confirm that a region of aligned grain boundaries is detrimental to BMV reliability.

Traditional PCB fabrication technology incorporates copper-plated vias after each press lamination connecting with microvias or mechanical vias. Conductive epoxy or transient phase conductive material are considered instead of copper plating where the board construction undergoes a one-press lamination cycle. The price per board was comparable between PCB fabrication methods; however, the transient phase conductive material process yielded a much shorter turn time (2 weeks versus 10 weeks). Radios tested were close enough in design to provide an opportunity to compare product performance between two fabrication methods. The following report details the findings of the product data, bench evaluations on specific nets, and reflow coupon data collected in production. Development Engineering, PCB Layout group, and Quality collectively established qualification steps for using transient phase conductive material in production.

The steps were:

1) Electrical comparison tests between the two mentioned designs.

2) Accelerated Life Tests between designs.

3) Test to failure and root cause analysis of two designs.

This paper contains the findings of step 1.

Microvia technology has been used in production since the 1990s. In the beginning, the design freedom for HDI PCBs was only limited by the imagination of the designer, resulting in some very ambitions construction. It became apparent quickly that there are limitations on how many microvias one can stack on top of each other and where to place them with respect to the core via. Since product acceptance testing is time constrained, microvia testing is often performed at elevated stress levels that do not directly equate to product life. The aim of the testing is to assert the manufacturing quality of the microvia, under the assumption that a properly manufactured microvia will not negatively impact the reliability of the product.

An extensive test campaign has been executed, covering three levels of microvias in three different materials (high-Tg FR4, RF material and polyimide). Fully stacked, fully staggered and semi-stacked microvia configurations were assessed. For the fully staggered and semi-stacked configuration, the influence of the location of the buried via was investigated. The applied test methods consist of convection reflow assembly simulation followed by air-to-air thermal shock in a HATS2 chamber on daisy chained D-coupon, reflow assembly simulation followed by thermal shock on HATS2 single via coupon, interconnection stress testing (IST) and current-induced thermal cycling. The results revealed both excellent performance of stacked microvias as well as the possibility of the test methods to detect weaknesses in design, material or manufacturing.

As Printed Circuit Board (PCB) designs increase in density, the need for High Density Interconnect (HDI) structures such as microvias is also increasing. With this uptick in microvia usage, there has also been an increase with reliability concerns. A structural weakness at the interface between the microvia target land and copper plating can occur eventually leading to a separation between the plating and the land. When bare boards are subjected to thermal cycling during reflow assembly, the microvias are susceptible to thermomechanical damage, causing intermittent circuit opens, leading to failures during Environmental Stress Screening (ESS) testing. These failures show the potential for latent defects that should they escape could potentially result in field failures. This reliability concern, including test failures, is well documented in the industry through reports from other Original Equipment Manufacturers (OEMs), an IPC white paper released in 2018 [1,2], and from within all Business Areas of Lockheed Martin (LM).

This paper discusses the design of a microvia test coupons panel, the testing of the coupons and results from the testing. The design of the coupons included a wide range of design practices to be examined, including a variation in diameter of laser formed microvias, microvia aspect ratio, offset for microvia-to-microvia transitions, offset for microvia to mechanically drilled buried via transitions, number of via transitions in each coupon and the usage of copper planes in the coupons.

This effort was to identify a range of design parameters that lead to a higher probability of success when it comes to the reliability of microvias. There are also many contributing factors during manufacturing when it comes to creating reliable microvias, including many processing variables that interact with the designs. However, the focus of this study is on the influence of the design features.

As has long been known, each time there is a step up to the next level of PCB technology, the industry is faced with new or the broadening of existing challenges. Today, this is particularly true of microvias. Once relegated to a small segment of PCB designs, microvias, and their reliability, are a growing factor within today’s designs.

This paper will provide an overview of the history of microvias, the challenges associated with the failures of them and the ways in which they can be proactively predicted and addressed during the early stages of the design process.

This paper presents test methods to effectively perform conducted testing on RF and high-speed data connectors for automotive applications. In almost any modern vehicle there are numerous high frequency and high-speed connectors which are used for applications such as cameras, internet connectivity thru cellular data, safety tasks, car entertainment, etc. These connectors are not easy to test. For example, a cable harness connector may have a hermetical seal which makes it hard to contact with a test probe. Connectors on printed circuit board assemblies and modules may be very small and densely spaced, which leads to additional testing challenges. This paper presents how typical RF and high-speed connectors from the automotive industry look like, describe the difference between single-ended and multi-signal / high speed connectors and show spring-loaded test pins that are used to establish temporary electrical contact for the purpose of electrical test. Electrical tests include tests that are done "at speed" as well as simpler applications such as continuity checks. Hi pot testing on such connectors and what that means for the test probe are also addressed. Furthermore, there is a deep dive into test fixture topics and a demonstration of why flexible cabling is a must and how to route wiring for such tasks inside a shielded or unshielded test apparatus. Such fixtures typically are also densely packed - there's not a lot of room for cabling - yet at the same time a simple mistake can cause test probes to be misaligned or worse to get damaged beyond the possibility of repair and there is a demonstration on how to prevent that. After this talk, engineers will have what it takes to successfully plan a test strategy to do functional testing for such applications.