Chemical failures in electronics are typically the result of interactions between materials and their environment. Contaminants can originate from manufacturing processes, such as No-Clean flux residues, partially cleaned flux residues, and wash fluids not thoroughly rinsed during cleaning. These contaminants interact with their environment, leading to the deterioration of components and ultimately causing system malfunctions.
The flux within solder paste plays a critical role in the soldering process by removing oxides from metal surfaces and improving solder wetting. However, the activity level of the flux residue left behind after reflowing can cause a reliability concern. Highly active flux residues can be corrosive, leading to long-term reliability issues such as corrosion and dendritic growth if not properly cleaned. On the other hand, low-activity flux residues may be less corrosive but can still pose risks if not entirely removed, especially in high-reliability applications.
Cleanability is another crucial factor when selecting a solder paste and selective flux. After the soldering process, residues left behind by the flux may need to be removed to ensure the assembly's reliability. If the residues are not adequately cleaned, they can lead to various problems, including electrical leakage, corrosion, and even short circuits.
Testing methodologies, such as Surface Insulation Resistance (SIR), Ion Chromatography (IC), and Localized Extraction testing, are designed to identify potential failure points and ensure electronic systems can withstand the challenges of different environments. This research paper will provide insight into the effects of process contamination and the use of these methods to qualify the assembly process.

This paper presents the 3D X-ray of fine-pitch ball grid array (FPBGA) assemblies at steps from hot to cryogenic temperatures to determine deformation behavior of the individual balls with temperatures. Characterization of deformation adds significant value and is critical for verification of analytical modeling and projection of fatigue life under thermal cycling. The cryogenic thermal cycle (–105℃ to +40℃) vs commercial (–40℃ to +105℃) behavior of the FPGA assemblies were presented at the IPC-APEX2024. As part of the investigation, non-destructive and destructive failure analyses were performed for Core Thin Ball Grid Array with 228 balls (CTBGA2028). It was shown that destructive dye and pry better narrowed partial and full cracking when compared to 3D X-ray at the currently achieved voxel size. A summary of the 3D X-rays and dye and pry with new images are first presented.
In addition, four of these components were examined with Environmental Computed Tomography X-ray (ECTX) at temperatures ranging from +105ºC to –105ºC. A CTBA228 atter 3,000 cycles was subjected to ECTX for a detailed analysis and visualization of internal warpage due to temperature changes, specifically visualization of the solder ball grid array. Comparison visualizations narrowed the outward/inward deformations in microns (μm) relative to RT at +105ºC/–105℃, which were pronounced at the corner balls. Their shapes and values from the ECTX evaluation are presented in detail. Under discussion, the experimental findings were compared to a simple analysis to explain the observed outward/inward deformations and project their shift values. Results are compared to limited literature data, which is required to extrapolate to –105℃.
Keywords: X ray, 3D X-ray, Environmental Computer Tomography, Ball grid array, BGA, FPBGA, CTBGA 228, tin-lead solder, SnPb, cryogenic, thermal cycle, solder joint reliability

This paper presents thermal cycle reliability of a 1657 I/O flip-chip ball grid array (FCBGA1657), which is developed for high-reliability (HR) applications. It also presents the effect of isothermal aging at FCBGA component level to address a burn-in requirement that has been widely used for the HR die screening per a Military standard specification. Four FCBAs were burned-in at 125℃ for 240 hours prior to assembly. For standard leaded HR parts, which leads are gold plated, such burn-in exposures have no effects on solderability of the leads, but this might not be the case for BGAs where solder balls melt or soften and fuse or diffuse with solder paste on PCB pad. Full melting occurs when both the ball and solder paste alloy material are the same and diffuse when they are differ. For FCBGA1657, SnPb was used for both solder balls and paste; therefore both become an integral part of interconnection. Oxidation of balls after burn-in is rare, but for the large I/O case, there is a chance one or two balls to become oxidize. Oxidation could induced undesirable Head in Pillow (HiP) and a chance for solder joint opens if they are functional balls. Literature search indicates, even though industry investigate the cause of HiP extensively for lower I/O BGAs, generally occurrence during reflow, but lacks as how screening under thermal cycling could detect early failures. Also, there are no research for such a large I/O FCBA, which is uniquely developed for HR applications.
For this aspect of investigation, the burn-in and fresh daisy-chain FCBGA parts were assembled onto complementary PCB daisy-chain patterns to generate resistive loops. These resistance loops were monitored during thermal cycling for detecting solder joint opens. Eleven daisy chain loops were designed to better narrow the locations of a failure from die shadow to middle and peripheral balls. Failures at the die shadow considered possible wear out whereas away from that region is possibly a workmanship defect. The FCBGA assemblies were subjected to extreme thermal cycling (TC) between –55℃ and 125℃ to determine cycles-to-failures (CTFs). Early, during continuous resistance monitoring, two out of 4 burned-in FCBGAs showed daisy-chain opens in the regions away from the die shadow whereas there were no early failures of the “As Is” FCBGA assemblies. CTFs for these assemblies are characterized and presented. In addition, daisy-chain opens were used to narrow the locations of failures for micro sectioning to determine failure mechanism. Indeed, X-sectioning revealed the nature one of the early FCBGA failure to be HiP. Micro-sectional images of FCBGA assemblies after 1000 thermal cycles are also presented. It further discussed physics of failure (PoF) with mitigation approaches for avoidance of HiP induced failures.
Keywords: HiP, head in pillow, HoP, head on pillow, isothermal aging, burn-in, ball grid array, BGA, flip chip BGA, FCBGA, 1657FCBGA, FCBGA1657, thermal cycle, tin-lead solder, SnPb

This paper presents the effect of standard single- and double- thickness of polyurethane coating on various sizes of Quad Flat No-Lead (QFN) solder joint assemblies. This coating is commonly used for high-reliability applications. In addition, the thicker coatings better mitigate tin whisker, but it may add additional significant vertical mismatch stresses under thermal cycles, which result in premature solder-joint failures. The stresses significantly increase in an extreme cold environment, e.g., deep-space missions, because of increase in rigidity; therefore, it is of concern for high-reliability applications. The two thicknesses were evaluated under thermal cycling and vibration. Vibration was performed using an innovative Highly Accelerated Life Testing (HALT) method. Aspects of this HALT method with times-to failures and failure mechanisms were presented at the APEX 2024.
The thermal cycling was performed from –55°C to +125°C for the two thicknesses of coatings. Half of each QFN assembly was coated to minimize the effect of manufacturing and testing variabilities. The HALT was performed under 50 g three-dimensional random vibration for five hours at −100°C, based on an analytical stress model that showed solder joints will be in inelastic stress condition at this temperature. The HALT step was followed by 450 thermal shock cycles in the range of −100°C to 125°C to detect possible latent defects initiated in the prior vibration. Monitoring focused on four daisy-chain QFN assemblies during HALT, followed by manual verification at RT after testing. The thermal cycle results are presented in Weibull plots, depicting the effect of conformal coating. The uncoated and coated QFN failures under sequential HALT and thermal shock cycles are also presented and failure mechanisms were compared to previous results. In addition, for uncoated QFN assemblies, the 50 g vibration for 5 hours results performed at 125℃ with subsequent 100 thermal cycles (–180°C to 85°C) are also presented.
Keywords: QFN, BTC, MLF, HALT, Quad Flat No-Lead, bottom termination, solder joint reliability, SnPb, tin-lead solder, thermal cycle, Thermal Shock, vibration, highly accelerated life, cryogenic

MSAP, Modified Semi-Additive Processing and SAP, Semi-Additive Processing are used in high volume in both Substrate and PCB manufacturing. These processes were developed to limit the impact of the base copper being etched subtractively, referred to as the “etch factor.” MSAP and SAP use very thin base copper to create electrolytic circuitry while only needing a slight etching, flash etching, to isolate each circuit.
FAP, Fully-Additive Processing utilizes similar manufacturing equipment and is also electrolytically built up, but instead of flash etching it is encapsulated in dielectric after the circuitry is formed.
All three processes have advantages, and the industry has many studies comparing MSAP to SAP, but this paper will focus on the differences between MSAP/SAP and FAP. While traditionally MSAP and SAP are used with HDI single layer buildup (per side) connections, FAP can be used both for HDI buildup connections and as internal cores for through-hole vias and vertical slot technologies like VeCS.

Modern electronics use bottom-terminated components (BTC) for short interconnections and many IOs. Distances between poles are small. Based on experience, cleaning is the best option to ensure robustness against electro-chemical migration (ECM). Difficult degassing under BTC and harsh environments do not allow compromise with no-clean technology. However, cleaning under BTC is not as simple as cleaning leaded components or simple SMT assemblies. Optimizing and maintaining proper cleaning parameters is complex. Cleaning generally is influenced by more parameters than processes like printing, placement, or soldering.
The first cleaning operation is washing, which dissolves residues. The addition of flux residue and reducing of bath volume by drag-over dynamically change the cleaner's dissolving activity.
Our study describes the influence of cleaner saturation by flux residues. Using different test methods, we also monitor the consequences of the saturation changes on the cleanliness. We compare the results of three cleaner saturation measurement methods: one laboratory, one shop floor, and results from a unique sensor directly on the machine. The sensor is called an organic carbon sensor (OCS) because it gives similar data to laboratory methods for determining TOC total organic carbon concentration)
Experience from other studies has shown that even the tiny residues left under the BTC after cleaning can cause leakage currents and even fatal damage to the board by ECM.
We did this work as a warning for all who clean. At high-capacity processes, the saturation must be measured very often. Only direct and just-in-time measurements of the cleaning process parameters can ensure the quality and stability of the assembly cleaning.

The rapid growing availability and maturity of generative AI and associated LLMs (Large Language Model) is creating new paradigm in enterprise transformation initiatives such as smart manufacturing and factory of future. One primary LLM capability is Retrieval-Augmented Generation (RAG), which excels in document summarization in comparison with previous technologies.
One promising use case of RAG in smart manufacturing is engineering document summarization via chatbot. It is very common that a manufacturing plant has numerous engineering documents (including internal engineering document and industrial standards). It often requires a lot of experience and knowledge for engineers to search for relevant information, requirement or specification in such large number of documents. Employee transition and retirement, which is a major business challenge facing by manufacturing sector, puts the retention of such experience and knowledge in great risk.
The paper presents a methodology to evaluate the performance of RAG for document summarization. The evaluation results are discussed without revealing any particular LLMs and any contents of the engineering documents used in the evaluation.
Keyword: Generative AI, Large Language Model, Retrieval-Augmented Generation, Document Summarization

The automotive industry is currently facing new challenges resulting from the transformation of the powertrain and the development of e-Mobility solutions. In this context, a technology shift is taking place in which organic substrates (printed circuit boards, PCBs) are operated in electronic assemblies at voltages of up to 1250 V. In addition, the operating time over the lifetime of an electronic assembly in the automotive industry is changing from 6000 h to 130,000 h. To select humidity-robust materials for manufacturing electronic devices, new test methods with high voltage (HV) loads are required. The need was recently addressed in the IPC-TM-650 Method 2.5.7.4, but a test coupon and a Round Robin study were missing so far.
A test coupon was now designed for High-Voltage Temperature-Humidity-Bias (HV-THB) testing at 1000 V for the outer layer of a PCB. The influence of different conductor structures and the base copper thickness were investigated. Different types of solder resist were evaluated for 2000 h test time. The results of the insulation resistance measurement are used in a Round Robin test between 3 different laboratories which successfully passed the Gage R&R requirements. The test coupon was additionally used for a factor analysis by different climate conditions and different material types.

Direct Digital Manufacturing (DDM) of additive electronics has gained considerable momentum in recent years due to the 3D design creativity that its additive materials provide. However, the same plastics that afford this creativity have low temperature limits, which hold back the circuit structure from high conductivity performance. Glass substrates are becoming increasingly interesting to performance seeking customers due to their smooth surfaces and higher temperature tolerances. While glass processing temperature (~400°C) outperforms that of plastics and FR4, it is still too low for optimal standard silver application (~850°C). Next-generation nanopastes present a promising lower-temperature solution to bring additive methods to glass substrates, offering excellent conductivity while achieving lower thick film resistance and smooth edge definitions. The methods developed in this work show that dispensed nanopaste on glass substrates gives superior DC and radio frequency (RF) performance, and unlocks a new class of high-performance glass Additively Manufactured Electronics (AMEs).
Silver nanopastes are often used as the conductive trace and interconnect material in AMEs for their suitability in microdispensing. Their conductivities are lower than their datasheet values, however, due to the low working temperatures of the plastic structures in AMEs, which often can go no more than 120°C. Silver nanopastes typically reach maximum conductivity at 250°C or higher. Experiments are conducted to compare silver nanopaste conductivity on traditional plastic AME substrates and glass substrates. A fully functional single layer circuit is then fabricated on glass. Design for manufacture rules and processes are compared between plastic AMEs, glass AMEs, and traditional PCBs.