In laptop and tablet CPU/GPU applications, package thickness tends to be thinner since it brings lighter weight, lower product thickness, and shorter interconnection distance. To decrease package thickness, several parts of the package structure can be considered, such as bump height, ball height, die thickness, and substrate thickness. This study focuses on the thickness reduction of the substrate core.
The copper-filled plating technique will be used to fill the through hole instead of resin plugging when the substrate core becomes thinner, from over 400 μm to below 200 μm. However, during the copper-filled plating process, through hole opening tends to be closed earlier than through hole center due to the nature of electroplating. Consequently, voids are easy to form, causing delamination and crack risk during package reliability tests when the void area is too large or the barrel thickness is not enough. This research mainly explored copper distribution at the early stage of plating since it is important for minimizing void size and controlling barrel thickness. Various combinations of flow rate and current density have been designed to have different throwing powers and interactions with additives. From the results, uniform copper distribution and secured barrel thickness with low current density and high flow rate conditions were demonstrated. At the same time, successful inhibition of copper deposition around the through hole opening lets plating chemicals reach the center of the through hole. Therefore, void size can be minimized to lower the risk of package reliability failure.

The reflow soldering performance of polymer aluminum electrolytic capacitors have a direct impact on their electrical performance. By analyzing the mechanism of capacitor bulges, improve the composition materials and production process, to enhance the high-temperature resistance performance, and reduce the risk of capacitor bulges.

Flip chip BGA, interconnect with semiconductor chips and mainboards, to serve the interconnection of electronic products. This paper is about the study of one of the important warpage modulator in flip chop BGA product. When flip chip BGA interconnects with semiconductor and mainboards, assembly problem can occur by substrate warpage caused by thermodynamic behavior and incoming substrate warpage, CTE mismatch and other noise factor. During assembly process, unexpected warpage behavior can make open or short problem. The warpage of flip chip BGA is made by thickness imbalance, thermal process, mechanical damage and assembly condition. In advanced technology of manufacturing process, all process apply full automation and optimize to thickness control and it can improve a thickness imbalance, thermal behavior and mechanical damage by machine. But in sudden case of machine trouble, operator need to take off the panel by manual and it can make the soft touch of the panel. This study is about how soft touch can affect flip chip BGA product warpage. In case of horizontal soft touch of the panel, the combination of gravity force and product’s weight can make panel warpage and it can make substrate warpage. The thermal reflow test result shows that the increase of soft touch shows increase of abnormal behavior by 0 → 7 →16 →22 EA, when soft touch 0 → 1 → 2 → 3 times increase. This result shows soft touch of the panel can make unexpected assembly open or short problem. From this simple experiment, the effectiveness of soft touch is most important when flip chip BGA manufacturing process.

In the pursuit of ever finer lines and spaces to advance technology's power and efficiency, the substrate and substrate-like production processes must adapt to meet these demands while carefully considering procedural interdependencies. Traditional flash etching, essential for removing the seed layer after pattern plating in Semi-Additive-Processing (SAP) and advanced Modified-Semi-Additive-Processing (aMSAP), presents challenges like undercuts, increased roughness, and trace geometry distortion. These issues are particularly pronounced as conductor size decreases. Hence, the primary objective is to achieve a high etching rate on the seed copper while minimizing damage to the conductor, often referred to as the etching ratio.
However, economic constraints introduce an added layer of complexity. More viable base chemistries, such as ferric sulfate etchants, tend to be costlier in terms of raw materials and dosage requirements. Therefore, cost-effective regeneration measures become imperative to mitigate the adverse commercial impact associated with these solutions. Additionally, specific additives are required to control the etch rate, etch ratio, and working window of the overall flash etching process.
In this paper, we introduce a novel ferric sulfate differential etchant designed to address these multifaceted challenges. We delve into its function and performance, offering insights into how it can serve the substrate and substrate-like production processes by providing an effective, cost-efficient, and environmentally friendly solution to meet the evolving demands of modern technology manufacturing.
Key words
Flash etching, differential etching, seed layer etching, mSAP, Modified-Semi-Additive-Processing, SAP, Semi-Additive-Processing

The protection of metallic substrates from reactive environments is necessary for semiconductor packages, which are mainly made of copper metal. Conventionally, plating with novel metals such as silver or gold is used. In this case, due to the high cost of novel metals, the process becomes complicated, such as plating only the wire bonding part. In addition, since plating is carried out using a wet process, it requires a space for storing the plating solution. This leads to the disadvantage of increasing the facility area needed to perform a continuous process.
Recently, graphene used for surface protection of metals has been grown using chemical vapor deposition (CVD) at 1000 ℃. However, this method has several negative effects, including size deformation and reduction in hardness of the metal substrate due to the high-temperature synthesis.
Here, we demonstrate the growth of few-layer graphene films using low-temperature plasma-enhanced chemical vapor deposition (PECVD) to protect the metallic substrate from air oxidation without causing any physical degradation to the substrate. The structural characterization, focused ion beam (FIB)-Scanning electron microscope (SEM), Raman spectroscopy, and X-ray photoelectron spectroscopy (XPS) studies show that metal surfaces are well protected from oxidation even after an accelerated oxidation evaluation of 85°C and 85% RH for 5 hours.

This study is part of a series of papers on mitigation of voids in solder joints. Voiding is an ongoing concern for printed circuit board assembly (PCBA) manufacturers. As bottom terminated components (BTCs) become increasingly popular, the potential for voiding in solder joints has increased. Voiding limits are often imposed on PCBA manufacturers. These voiding limits lead manufacturers to find ways to mitigate voiding.
There are two major mechanisms for void formation. The first mechanism is gas entrapment in the solder joint. Gasses come from volatile materials in the flux, air gaps in the solder paste print, and from the PCB and components. The second mechanism for void formation is incomplete wetting or spread of the solder. When the solder alloy does not completely wet both the PCB pads and component leads, gaps remain in the solder joint.
This study is a continuation of work on voiding with respect to solder alloy and stencil design for quad-flat no-lead (QFN) components. The solder alloys tested include Sn63/Pb37, SAC305, SnBiCuNi, SnAgBiCu, and Sn37BiX. A water-soluble Pb-free solder paste flux and SAC305 reflow profile were used. The stencil design was varied on the QFN thermal pads to determine how gap size affects wetting of the solder alloy. Wetting behavior and gas entrapment were correlated to voiding for each solder alloy. The data for both parts of the study was summarized, and recommendations given to help “Fill the Void.”

ETS (Embedded Trace Substrate) is one of advanced substrate design that enable to make fine width and space. The Cu trace open defect on ETS layer (L01) revealed by this OSP micro etching is non-detectable defect mode because OS test (Open-Short test) to detect this kind of defects is done before OSP process. The reason of OS test prior to OSP process is to prevent damage on Cu surface coated with OSP caused by OS test pin mark. OS test can be done after OSP process to detect this defect. But there was no specific study or approach regarding solder joint quality with OS test pin mark. TCNCP (Thermal Compression bonding with Non Conductive Paste) solder joint quality associated with OS test pin mark on ETS layer coated with OSP is investigated. This study demonstrates that Cu trace open on ETS layer generated by OSP micro etching can be detected by OS test prior to OSP process, and it is revealed that TCNCP solder joint quality can be worse due to increased NCP (Non Conductive Paste) entrapment as the number of OS test retrial times are increased.

The explosion of data in the 4th Industrial Revolution has increased the importance of high-performance computing (HPC). HPC requires high-density I/O count to be formed in small area, but the low yield limitations of manufacturing large-area chips for this purpose have led to the development of chiplet and interposer. Interposer are used to bridge the difference in circuit width between chips and PCBs. Use of organic interposers is a recent technology trend, which combine the high resolution of Si interposer with the low-cost production of PKG (Package) board. Due to the inter-chip connectivity and performance of top-mounted HBM, Logic, etc., organic interposer can also embed Si, IPD, DTC, etc. dies inside, which can increase the performance of the entire system and gain a cost competitive edge. [1-3] However, the cavity and asymmetrical structure for this purpose causes warpage, so interposer manufacturers are focusing on warpage control to ensure reliability. This paper focuses on a methodology for improving the warpage of organic interposer. We identify the effect of circuit asymmetry caused by embedded chips and cavities on warpage, and forcibly impose structural asymmetry, such as changing the mechanical properties of the insulation layer and the thickness arrangement of each layer, including the core, and propose warpage improvement ideas based on them. Our findings provide material and structural design guidelines for interposer fabrication and can be utilized to improve the performance and reliability of advanced packaging applications

Sn-58Bi lead-free low-temperature solder (LTS) is regarded as a candidate for low-temperature assembly of electronics components, but its usage field is limited in Surface Mount Technology (SMT). The present study reports on the technical issues of a recent conventional wave soldering system when it is combined with Sn-58Bi LTS, the suspected reasons for each defect, and modifications to adapt modern production work. The critical defects on the printed circuit board (PCB) were severe contamination of dross, which was caused by viscosity thickening of flux in a low-temperature environment. In addition, the spongy dross that accumulates in the tank not only worsens the pollution, but also impairs the economic efficiency of the material. A redesigned nozzle and the addition of a dross removal function were introduced to improve system feasibility. Cooling equipment and flux were also optimized to stabilize finish quality. By selecting an effective organic acid based on energy calculations and modifying the viscosity at high temperatures, a new flux was developed to eliminate the fillet volume shortage caused by the inherent oxidation and low surface tension of LTS. A predictable defect in the rework process is lift-off when Sn-based solder is added, and in order to avoid this, it is necessary to maintain a high bismuth density in LTS supply. LTS wave soldering has shown promising results over Sn-3Ag-0.5Cu (SAC305) in terms of TCT evaluation and reduction of energy consumption and CO2 emissions. Through comprehensive research, the LTS wave soldering system demonstrated its industrial feasibility.

Deep microporous crab legs and abnormal crystallization of coating are common defects in the electroplating process, which have a significant impact on the reliability of PCB products. In this paper, the finite element analysis method is used to numerically calculate the flow state of the plating solution on the PCB surface and in the hole during the jet process. The velocity distribution of the plating solution in the blind hole with different aspect ratio (AR) was obtained. In addition, the influence of electroplating parameters such as current density, waveform time ratio, positive and negative current ratio on the effect of deep microporous electroplating is studied through experiments. The results show that when electroplating and jet flow parameters are synergistic, these defects can be effectively improved.