IPC Standards European Committee/Task Group Meetings

Date
- (3:59 - 11:00am CDT)

IPC Standards European Committee Meetings are located at Hotel NH Collection Munchen Bavaria, Arnulfstrasse 2, Munich, Germany. 

We are seeking your valuable input and participation at this year's meetings. IPC standards are developed for the industry by the industry. Any interested person can join at no cost, volunteering their time and efforts in building a stronger community of electronics manufacturers, OEMs, and suppliers. Help us drive the electronics industry forward by participating in any committee of your expertise. We ask you to register so that we have a reasonable count to manage meeting rooms.

IPC Standards and Task Groups - 

  • IPC-Hermes-9852 Task Group
  • IPC-A-610 and J-STD-001 Task Group - Europe
  • IPC-CFX Standard Task group
  • Cybersecurity Protection Standard Task group
  • European Training Group
  • critical Components Traceability and Digital Credential Exchange Task Groups
  • Automated Inspection Process Standards Task Group
  • Sustainability Reporting and CO2e Calculations Task Group
  • Materials Declaration Subcommittee
  • Plastronics Accelerated Reliability Test Task Group
  • Cool Joining Press-Fit Task Group 

Download Meeting Details 

There is no cost to join the meetings. 

Hotel in Munich

We are holding room blocks for your convenience in the following hotels:

  • NH Collection München Bavaria – 4 nights (October 26 to 30), 252€ per night, breakfast included – 8 rooms available
  • Mio by Amano - 4 nights (October 26 to 30), 219€ per night, breakfast included – 16 rooms available
  • 25Hours - 4 nights (October 26 to 30), 195€ per night, breakfast included – 8 rooms available
  • 25Hours - 4 nights (October 26 to 30), 221€ per night, breakfast included – 8 rooms available

All rooms are available until October 20.

 

If you should have additional questions, contact Andres Ojalill, andresojalill@electronics.org

 

Region
Hotel NH Collection Munchen, Germany

Arnulfstrasse 2
80335 Munchen
Germany

Hotel NH Collection Munchen, Germany

Hotel NH Collection Munchen, Germany
Arnulfstrasse 2
Munchen, 80335
Germany

How Artificial Intelligence (AI) Helps on Automated X-ray Inspection (AXI) Process

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The use of inspection systems in production has increased as manufacturers use automated inspection technologies to capture defects in the production process. The benefits of utilizing the inspection systems include optimized production line operation, reduced labor and resource consumption, and an overall increase in yield and quality improvement.

The AXI (Automated 3D X-ray inspection Solution) enables manufacturers to inspect hidden defects and solder joints that SPI and AOI systems cannot see or capture. Due to technological evolution, more and more unique packages appear in the market, further increasing the challenges in this field. Therefore, Artificial Intelligence (AI) has been introduced into inspection equipment, including implementing AI during programming, image reconstruction, programming validation, inspection or classification, and buy-off stages. The AI stands at the forefront of technological innovation, offering many advantages across diverse domains. One of its primary benefits lies in automation, streamlining routine tasks, and freeing human resources for more intricate and creative endeavors. The 24/7 availability of AI systems ensures uninterrupted services in sectors like customer support. This significantly impacts the production environment regarding efficiency, accuracy, and effort reduction, while AI often leads to substantial cost savings over the long term.

Author(s)
Chong Wei Chin, Lim Lay Ngor, Chew Kok Wei, Hee Wei Ken
Resource Type
Technical Paper
Event
IPC APEX EXPO 2024

Technical Research for PCB Design Solution of High Efficiency Thermal Dissipation

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With the high power density and miniaturization of electronic products, printed circuit boards need to have more efficient thermal dissipation. In the thermal design of printed circuit board, more attention will be paid to the overall thermal dissipation of high-power products, usually ignoring its contribution to thermal dissipation itself. According to the demand of terminal electronic products, this article has systematical study to the thermal conductivity materials, the whole thermal dissipation structure, the selection of power devices and the thermal simulation technology, to get the optimal thermal dissipation solution under different heat flow density and working conditions. And design thermal dissipation PCBs with different thermal dissipation grades according to the thermal conductivity requirements of high power products, which can be defined as five grades with T/C from 1W/(m*K) to 800W/(m*K). It needs to match with different thermal dissipation PCB solution for different thermal design & different method of power device package to meet the needs of products of thermal dissipation characteristics.
Key words Thermal dissipation PCB, IMS, High thermal conductivity IMS, inlay, Diamond copper, IMS radiator integration; thermoelectric separation substrate

Author(s)
Wang Jun, Wang Yuan, Luo Qi, Zhang Feilong, Huang Yizhao, Kuang Meijuan
Resource Type
Technical Paper
Event
IPC APEX EXPO 2024

Applying Hierarchical Machine Learning Forecast to Manufacturing Process Sequences Topic/Category: Factory of the Future OR Emerging Technologies

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It has been demonstrated it is possible to combine design, process, and metrology information to create machine learning models that accurately predict the behavior of individual products in the manufacturing line. In this work, we extend the application of these single process models to a full production sequence. Instead of training a large machine learning model to describe the full production sequence, we sequentially train the models in a way that prior models can be used to impute the sparse manufacturing data of previous process steps. This approach uses process and context-aware methods to effectively augment real-world facility data that is otherwise expensive to collect. By doing so, it is possible to identify which process steps have the most impact. While the primary work was validated in the final electrical test after a Back-End-Of-Line process, the methods used have been demonstrated to work in packaging operations. Two of the challenges to apply machine learning methods to manufacturing processes, are the complexity and heterogeneous nature of each individual unit operation, as well as the lack of complete characterization for every single item being produced due to throughput and cost constraints. In this work we demonstrate the benefits of using a hierarchical approach to product manufacturing in which individual unit operations are modelled individually, but results of previous operations inform and forecast subsequent manufacturing processes. To demonstrate this methodology, we have selected a portion of a Semiconductor manufacturing process, composed by over 40 distinct unit operations.

Author(s)
J. Andres Torres, Nathan Greeneltch, Melody Tao, Srividya Jayaram, Mohan Govindaraj, Anastasiia Doinychko,
Resource Type
Technical Paper
Event
IPC APEX EXPO 2024

Reliability Validation of Direct-Write Printed RF Devices

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Additive manufacturing (AM) methods to fabricate and repair printed hybrid electronic (PHE) components and interconnect systems create compelling opportunities in 3D curvilinear architectures for printing RF components and interconnections. However, significant technical challenges remain that must be overcome to develop practical techniques for assuring consistently reliable outcomes. Some of the important RF technology applications where new process development efforts are needed for successful deployment of additive manufacturing methods are: PIN Diodes (die encapsulation and conductive ink interconnections); Coupling Transformers (printed core and windings); and Direct-write Interconnect-over-Fillet (IoF) architecture for mmW MIS Capacitors. When fabricating high-performance RF circuitry for performance up to 40 GHz, direct-write printed versions have the potential to provide a distinct advantage over traditional components by offering smaller form factors and unique conductor/dielectric material formulations. the robustness and reliability of such printed structures have not been sufficiently investigated and demonstrated. The objective of this presentation is to highlight the results of the multi-year effort to develop and environmentally test (temperature excursions, static and dynamic mechanical stresses, and humidity) the RF technologies listed above.

Author(s)
Tom Rovere, Joe Jendrisak, Mark Halliday, Hisham Abusalma, Swarup Subudhi, Abhijit Dasgupta, Siddhartha Das, Emuobosan Enakerakpoo, Steve Gonya, Mohammed Alhendi
Resource Type
Technical Paper
Event
IPC APEX EXPO 2024

The Attempt of Lower Temperature Soldering Process for Large Plastic Ball-Grid Array Board-Level Assembly

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Lower temperature soldering has been regarded as one of the most effective ways to reduce warpage risk. Use of lower-temperature solders, including a BiSnAgCu eutectic and two In-containing, Bi-free solders - ILT, and ILT-2 has been attempted to reflow the 40 mm x 40 mm plastic ball grid array (PBGA928). BiSnAg, under the combinations of reflow profiles P185 and P200 (~185°C and ~200°C peak temperature) and the paste-to-ball (P2B) volume ratio (0.13, 0.25, and 0.5), always formed defective joints. Under the P200 profile with P2B volume ratio of 0.5, SAC305/BiSnAg joints were still dominated by defects, including hot-tearing and shrinkage voids despite forming the desired drum shape. With the constant 0.13 P2B volume ratio, P200 also renders various malformed joints for both ILT and ILT-2. Increasing reflow temperature improved the joint shape and greatly reduced the defects for both ILT and ILT-2. In P220, both SAC/ILT and SAC/ILT-2 joints achieved the desired short-and-fat drum shape, comparable to those reflowed under P240. The formation of the optimal joint is attributed to the sufficient liquid solder volume since both paste and SAC ball melt and merge under the hot profiles, which compensates the displacement caused by the dynamic warpage. Both SAC/ILT and SAC/ILT-2 joints only exhibited limited hot-tearing under the P200 profile. The different metallurgy of ILT and ILT-2 did not result in an enlarged pasty range after joining with SAC305 and thus led to the lower defect rate. Investigation of the joint reliability performance is still ongoing.

Author(s)
Hongwen Zhang, Tyler Richmond, Francis Mutuku, and Huaguang Wang
Resource Type
Technical Paper
Event
IPC APEX EXPO 2024

Liquid Metal Patterning for Electronic Circuits and Thermal Management

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Gallium-based liquid metals have remarkable properties: melting points below room temperature, wide conductivity, water-like viscosity, low toxicity, and effectively zero vapor pressure (they do not evaporate). They also have the largest interfacial tension of any liquid at room temperature. Normally, small volumes of high-tension liquids form spherical or hemi-spherical structures to minimize their surface. However, due to a thin, rapidly forming oxide skin, gallium-based liquid metals can be patterned into non-spherical shapes (cones, wires, antennas, or films for thermal interfaces). In addition, the metal can be rendered into a ‘gel’ or ‘paste’ by incorporating other materials such as oxide flakes or metal particles. These additions change the rheology of the metal and thus, its flow mechanics during nozzle dispensing. This talk describes efforts in our research group to pattern and manipulate metal into useful shapes—such as circuits or thermal interface contacts—that take advantage of the properties of liquid metal. It is possible to pattern liquid metal in unique ways, such as injection or direct-write 3D printing at room temperature to form ultra-stretchable wires, self-healing circuits, and stretchable barrier materials. Perhaps the most fascinating aspect of liquid metals is the ability to use interfacial electrochemistry, removing/depositing the oxide to manipulate the surface tension of the metal over unprecedented ranges (from the largest tension of any known liquid to near-zero). This work has implications for thermal interface materials as well as soft and stretchable electronics, both being devices with desirable mechanical properties for human-machine interfacing, soft robotics, and wearable electronics

Author(s)
Man Hou Vong, Jonathan Major, Dr. Ricky McDonough, Michael D. Dickey, Miloš Lazić
Resource Type
Technical Paper
Event
IPC APEX EXPO 2024

Tracking Voiding and Solder Coverage of SMT Solder Joints by Automated X-Ray Inspection - a Revealing Round Robin Study

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Voiding and solder coverage in SMT solder joints remain a matter of (sometimes emotional) debate in automotive electronics. Meanwhile voiding/solder coverage requirements have been introduced into IPC J-STD-001HA/IPC-A-610HA. But beside the question of reasonable requirements, the topic of void quantification in sample and mass production has to be addressed as well. Many X-ray inspection systems available on the market are offering an automated void quantification option for different solder joints. The question arises how repeatable and reproducible these void values are in a normal sample and mass production environment.
To address this question, a round robin study has been organized by a working group of the ‘Deutsche Kommission Elektrotechnik’ (DKE, the German Electrotechnical Commission) with participation of several automotive electronic stakeholders, including Tier1 suppliers, OEMs and suppliers of X-ray inspection equipment. Predefined components on six product or test boards have been analyzed by nine different evaluators. Solder joints of BGAs, QFNs (especially thermal pads) and chip-Rs have been X-rayed to cover a wide range of solder joint geometries. To investigate the repeatability, all solder joints have been analyzed 25 times.
The final evaluation shows poor repeatability of the analyses at one location, but even more pronouncedly, the reproducibility at different analysis locations was considerably worse than expected. Exemplary results of this study are presented together with main conclusions and recommendations for improvement and void control strategy in mass production. The findings also indicate that discussions about solder coverage requirements on a single-digit level are in vain.

Author(s)
Heinz Wohlrabe, Norbert Holle, Holger Schmitt
Resource Type
Technical Paper
Event
IPC APEX EXPO 2024

Research on High-speed Material Insertion Loss in Server Platform

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At present, with the rapid change of the server market, Eagle Stream platform chipset, which changes the traditional practice of Whiley platform material selection and stack mode compared with the previous and provides a new reference perspective for everyone.
The Eagle Stream platform differs from the Whiley platform in the selection of materials. First, the Eagle Stream platform imposes higher requirements on materials with excellent electrical properties to meet the high frequency and high speed signal transmission requirements of the new platform. In the way of stacking, it also reflects innovation and change, choosing a more complex, but more efficient way to improve the overall performance.
The insertion loss of Eagle Stream platform material is analyzed in this paper. Insertion loss is an important electrical performance indicator, which can reflect the degree of influence of electronic devices on signal transmission under certain conditions. Through a large number of experimental data, we found that the insertion loss of the same material under different structures is significantly different, even enough to affect the overall electrical properties. Therefore, when selecting materials, we should not only pay attention to the performance of the material itself, but also consider its stacking mode in practical applications.
This study provides a direct and effective reference for the material selection of Eagle Stream platform, which is of great significance for optimizing product performance and improving product competitiveness. In addition, we also look forward to the emergence of more innovative platforms after the Eagle Stream platform, which can further promote the development of the server market and better meet user needs.
Keywords: Eagle Stream platform, Insertion loss

Author(s)
Xiang Canjun, Peng JingHui , QinYuan Li, JunLin Chen,
Resource Type
Technical Paper
Event
IPC APEX EXPO 2024

Achieving a Successful ENEPIG Finished PCB under Revision A of IPC-4556

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The 4-14F IPC Standards Committee are close to finalizing (at the time of writing) a revision to the IPC 4556 specification for Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) finished Printed Circuit Boards (PCB). Revision A brings a more comprehensive evaluation of metal layer thickness measurements, compositions, and introduces a quality aspect for nickel corrosion following a successful publication of the revised IPC-4552B (ENIG specification).
The introduction of these revisions will ensure a higher level of quality for conforming ENEPIG deposits, but it will also present some challenges in achieving and consistently delivering the required level of quality from PCB fabrication.
IPC-4556A will require the PCB fabricator to demonstrate capability in measuring and maintaining electroless nickel, palladium and gold thicknesses, electroless nickel %P composition along with conformance to a newly introduced corrosion specification. IPC-4556A covers traditional ENEPIG using immersion gold technology and introduces a newer gold plating technology – reduction assisted gold (also known as hybrid or semi-autocatalytic gold). In short, the fabricator has more work to ensure an IPC-4556A compliant ENEPIG deposit.
This paper will provide a comprehensive review of IPC-4556A, supplying explanations and examples of conforming and nonconforming ENEPIG to help the fabricator understand and embrace the challenges posed by the new specification and provide a higher quality ENEPIG deposit.
Key words: IPC-4556A, ENEPIG, electroless nickel, electroless palladium, immersion gold, hybrid gold, reduction assisted immersion gold, semi-autocatalytic gold corrosion.

Author(s)
Frank Xu, Ph.D., Michael Orsini, Jesus Barajas, and Martin Bunce
Resource Type
Technical Paper
Event
IPC APEX EXPO 2024