IPC Provides Comments to USTR on Domestic Impact of Proposed Tariff Rate Increases on Chinese Imports

The European Union is currently working to update its legislation on export controls for dual-use items, meaning items that can be used for both civilian and military applications and/or can contribute to the proliferation of Weapons of Mass Destruction (WMD). Most importantly, the proposal for an updated Regulation introduces the following changes: • Expansion of list of dual-use items to include cyber-surveillance technologies and those that can be used for human rights violations. • Added obligation for exporters, when conducting their due diligence, to notify Member State authorities, if they suspect exported items not listed in the Regulation are used to violate human rights. • The European Commission is empowered to amend the list of dual-use items covered by the Regulation, so continuous monitoring of this process will be needed to ensure regulatory compliance. The new Regulation does not include any specific mentions of printed circuit boards, but is nevertheless a piece of legislation that IPC members must be aware of, as it could create possible regulatory compliance issues. With that in mind, IPC has drafted a briefing note detailing the new provisions introduced by the Regulation, as well as the state of play and next steps in the legislative process. The updated proposal is currently being discussed by representatives of the European Commission, Council and Parliament in informal “trilogues”. It is possible that the updated Regulation will have gone through the legislative process in the course of 2019. The more detailed briefing note on the new regulation on export controls on dual-use items can be found here: http://www.ipc.org/3.0_Industry/3.3_Gov_Relations/2018/Dual-Use-Export-Controls-Briefing.pdf. IPC members are invited to share their feedback on this document and any other thoughts and concerns they might have on export controls for dual-use items with Chris Mitchell, IPC’s vice president of global government relations, at ChrisMitchell@ipc.org.
IPC is seeking volunteers who represent all segments of the electronics manufacturing industry, for our Technical Education Program Committee, to help guide, create and develop high-quality educational programs through conferences, tutorials and workshops. This is a great opportunity to collaborate with your industry colleagues and to become more involved with IPC. For more information, contact Alicia Balonek, senior director of tradeshows and events, at AliciaBalonek@ipc.org.
Don Dupriest, Lockheed Martin Missiles & Fire Control, has been elected chair of the IPC Technical Activities Executive Committee (TAEC) for a two-year term. Dupriest succeeds Chris Mahanna of Robisan Laboratory, Inc., who held the role for IPC's top standards development oversight committee for the past two years. As a Lockheed Martin Fellow on Lockheed Martin’s Technical staff, Dupriest provides leadership in interconnect technology development for electronic manufacturing and is responsible for advanced technology, process development and product manufacturability for electronic systems. An active IPC volunteer for more than 25 years, Dupriest has provided invaluable service to IPC. A previous chair of the TAEC, he is also a member of IPC’s Hall of Fame and President’s Award recipient. Dupriest currently co-chairs the IPC D-35 Printed Board Storage and Handling Subcommittee. Dupriest was elected to the TAEC post while attending a mentorship meeting for IPC Emerging Engineers. “I have to admit I was surprised to hear I was elected – I guess this is what happens when you miss your first TAEC meeting in twenty plus years,” he joked. “The committee voted to change the rules to allow a second term.” Dupriest added, “I am honored to be chosen and trusted by my peers to lead and serve as the first second term chairman of the TAEC.” Citing his goals for chairmanship, Dupriest stated, “I typically jump right in when approaching any task, so I plan to do that with the TAEC. We now have greater use of task groups within committees to speed up creating content and resolution of requirements under development, but there is always room for improvement. “I’d like to see what else we can do to better execute standards development by revising the Project Initiation Number (PIN) process for each new document at IPC. I’d like the process to better describe potential influences on other general committees and documents; i.e., requirements that might be impacted by the new PIN, giving general chairs a broader idea of activities outside their purview that may be impacted by new document development. I am also interested in keeping the communication lines open between general chairs so that we keep one another informed.” Mentioning his commitment to mentoring the next generation of engineers, Dupriest indicated his interest in bringing emerging engineers to TAEC meetings to give them an idea of what to expect once they are members of IPC. For additional information on the IPC TAEC and its activities, visit www.ipc.org/TAEC.aspx.
The use of high performance electronic assemblies in harsh environments subject solder interconnects to complex loading conditions that are primarily driven by the behavior of circuit card assembly and mounting constraints. These assemblies contain a variety of surface-mount devices which are sensitive to thermo-mechanical (TM) fatigue. Stresses generated by placing certain components within the vicinity of mechanical structures,such as standoffs and connectors,can further influence solder fatigue by increasing PCB strains. The mounting constraints can subject packages to loads which are not expected to occur under non-constrained PCB configurations often used in accelerated testing. In order to determine the influence of complex board constraints on electronic components,thermal simulations are performed using finite element analysis (FEA). Detailed models of large electronic assemblies are often tedious and time consuming to construct. In this study,TM simulations of electronic assemblies are implemented to investigate the effect of mounting conditions on board strains. The software used in this analysis enables fast integration of package level and printed circuit board (PCB) features from design files into comprehensive models enabling efficient analysis of the entire board level assembly under thermal loads. These simulations capture the contribution of both local and global coefficients of thermal expansion (CTE) mismatch in the vicinity of mounting conditions and components. The software package implemented in this analysis enables the prediction of board behavior of complex electronic assemblies under TM loads and provides an efficient approach to enhancing circuit board layout.