In order to provide the functionality in today’s electronics,printed circuit boards are approaching the complexity of semiconductors. For flexible circuits with 1 mil lines and spaces,this means no nodules,no pits,and excellent ductility with thinner deposits. One of the areas that has to change to get to this plateau of technology is acid copper plating. Acid copper systems have changed in minor increments since their introduction decades ago. However,the basic cell design using soluble anodes in slabs or baskets has for the most part remained the same. Soluble,phosphorized,copper anodes introduce particulate and limits the ability to control plating distribution.
The companies worked together to evaluate a new approach using insoluble anodes that are isolated from the main plating bath. Insoluble anodes are known to eliminate the particulate,provide consistent anode area and shape the anode to match the plated part. But isolating the insoluble anode dramatically reduces high consumption of organic additives typical with insoluble anodes. This new approach limits additive breakdown and & consumption normally seen at the soluble anode surface. The end result is a surface free of nodules,pits,and precise control of copper thickness distribution minimizing the impact of breakdown products.
This paper is to document the results from prototype testing through implementation into production. The system was first tested in pilot tanks at the companies to determine the impact on nodules and surface distribution. Data was generated looking at impact of anode design on plating distribution and surface for any defects. This data was utilized to design a full scale production line that is being used to quantify process improvement over existing production equipment. The goal for the work being done is a perfect copper surface.

Copper Via-Fill application in acid copper plating of PWB is experiencing a significant growth due to the booming of smartphone and tablet PC. With this growth,the PC board demand of HDI complexity has also increased. The "any-layer" design is widely adopted in layer count reduction whereas the circuit density is increased due to more freedom in designing the circuitry. This kind of build-up process required 100% blind microvia fill up in every single layer and stack up for interconnect. The challenge of this design is the zero tolerance of dimple/void as well as minimal copper build up for ultra fineline circuit formation. The latest development of via-fill has set the new standard of zero dimple/void with copper build up less than 10 ?m. No copper reduction is required,even for the ultra fineline etching process in which the circuitry goes down from 20/20 ?m L/S to 15/15 ?m L/S. Another challenge of the process is prolonged plating cycle time. This paper will illustrate an advanced super-filling technology which was developed in the combination with green PTH alternative - conductive polymer direct metallization. The direct via-filling on conductive polymer becomes possible which could minimize the use of copper as well as shorten the total process cycle time by more than 50%. The extraordinary coverage of conductive polymer over glass and resin surpass the traditional electroless copper performance; thus enhance the current flow for via-filling. The mechanism of the specialized additive system over the conductive polymer was investigated. Today's equipment for copper via-fill in PWB industry is dominated by either vertical or horizontal conveyorized system. The hydrodynamic impact to super via-fill performance will also be discussed.

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In the area of Printed Electronics,there are a number of functional materials that can include conductors,Semi-conductors,dielectrics,barriers,and adhesives. There are also a smaller subset of functional materials for specialized purposes that are known as Ferroelectric,Piezoelectric,and Pyroelectric materials. The purpose of this presentation is to become acquainted with this group of special functional materials and some examples of where they are being utilized in today’s technology.

The number of failures caused by electrostatic discharges (ESD) has been increasing for some time now. So,it is necessary for everyone,who handles electrostatic sensitive devices (ESDS),to know the reasons of such failures. The paper will give an overview about possible causes for ESD. Particularly automated production lines have some processing steps,where electrostatic charges are increasingly generated. So far one has been focused on the human being. This is controllable. Measurements in production lines show electrostatic charges at the following processing steps: application of soldering paste (printer),assembling (automated and manual (pick and place)),and labeling as well as electric tests (ICT). The electronic components are always assembled directly and without any covering on the PCBs. Thus,the wire bonding process leads to damage of the electronic components. The processing steps,where the PCBs are covered with chassis must be inspected also. Such chassis are mostly made of isolating materials,like plastics. Thus,those can be highly electrostatic charged,while assembling. In summary an optimized ESD Control System for ESD working areas and machines with the emphasis on cost-effectiveness will be compared. Topics: An optimized ESD control system,with an emphasis on cost-effectiveness,Introduction of an optimized ESD Control System for ESD working areas,Solutions for machines and automated processes,Measurement methods in SMT production line and ESD audits,Product quality.

With the push for ever improving performance on semiconductor component I/O interfaces,semiconductor components are being driven into a realm which makes them more sensitive to electrostatic discharge,potentially increasing in sensitivity by 50% every 3-5 years. Today,the majority of modern day semiconductor components are being designed to meet 250Volts of charge device model sensitivity,and that could decrease to 125Volts in the next 3-5 years,and could again decrease to 50Volts-70Volts in the following 3-5 years. The entire electronics industry must prepare for this challenge.
In preparation for this upcoming challenge,we along with some other semiconductor companies are embarking on an educational awareness and preparedness initiative with ODM’s/OEM’s. This includes awareness of the industry technology roadmap,and educating them on what they need to do to prepare for this challenge. As part of the preparedness initiative,we request that they start considering real time electrostatic discharge (ESD) detection within their “high-risk” modules; such as automated surface mount equipment,where direct measurements have confirmed semiconductor components are directly exposed to ESD events.
The call to action for automated surface mount equipment manufacturers is to start to evaluate,and implement,real-time ESD detection technologies in areas where direct contact with the component (i.e.. pick and place) occurs,and incorporating this real-time detection into their new equipment designs,as well as preparing retrofit kits for existing equipment sets. This is not a trivial task and will require time to develop and implement,so we urge the equipment manufacturing community to begin the process now in preparation for the increase in device sensitivity. In this paper,we will share what has learned about real-time ESD event detection in hopes it aids the equipment manufacturer’s preparedness.

Substrates have become more critical with regard to pitch and density in today’s designs with challenges for passive components in terms of surface placement. This negates the opportunity for high speed,high cost components to be placed on the surfaces of the PCB. With this the capacitance and resistive components have to be embedded into the design. This has been accomplished with the advent of buried capacitance cores and buried resistors. Unfortunately this has caused some challenges to the ET Test Centers/Labs in the ability to effectively test these buried passive components. Processes have had to change and adapt to these new technologies. The paper will discuss what these new technologies are and how the Electrical Test arena has adapted to provide accurate testing of the buried resistors and accommodate the buried capacitive cores to not receive false errors from the Grid Testers and Flying Probes.

The PCB industry is ever changing and adapting to new technologies. OEM specifications and requirements have also advanced due to these technologies. In some cases the OEMs are asking for a low resistance test to be performed on some or all electrical test nets of the PCB or on the holes of the PCB. This requirement is typically not well defined on the fabrication drawing and that leads to misleading conclusions by the fabrication house.
4-Wire Kelvin testing has been around for many years but using this type of measurement on bare PCB’s is a relatively new requirement. The requirement for PCB 4-Wire Kelvin testing was originally requested by digital commercial OEMs in the US with the aim to set out to improve the overall quality of the products. The first 4-Wire Kelvin test requirement for PCB’s were on a limited hole criteria. Since that time automotive companies in Japan have also adopted such requirements. Medical applications are also joining in with their own 4-Wire Kelvin requirement.
This paper will use the data gathered by the company’s operations to outline what a 4-wire Kelvin test is and how it can be used. Several examples will be illustrated of what the 4 wire Kelvin test can and cannot do. A clear definition of what limitations are present during the testing operation will be defined. The paper will assist designers in understanding how the low resistance test can assist them and also identify causes that can identify unwanted concerns/issues.

Many researchers have used different failure criteria in the published solder joint reliability studies. Since the reported timeto-
failure would be different if different failure criteria were used,it would be difficult to compare the reported reliability life of solder joints from one study to another. The purpose of this study is to evaluate the effect of failure criteria on the reported thermal fatigue life and find out which failure criterion can detect failure sooner. First,the application of the control-chart based method in a thermal cycling reliability study is described. The reported time-to-failure data were then compared based on four different failure criteria: a control-chart based method,a 20% resistance increase from IPC-9701A,a resistance
threshold of 500O,and an infinite resistance. Over 3.5 GB resistance data measured by data loggers from a low-silver solder joint reliability study were analyzed. The results show that estimated time-to-failure based on the control-chart method is very similar to that when the IPC-9701A failure criterion is used. Both methods detected failure much earlier than the failure criterion of a resistance threshold of 500O or an infinite resistance. A scientific explanation is made of why the 20% increase
in IPC-9701A is a reasonable failure criterion and why the IPC-9701A and the control-chart based method produced similar results. Three different stages in resistance change were identified: stable,crack,and open. It is recommended that the control-chart based method be used as failure criterion because it not only monitors the average of resistance,but also
monitors the dispersion of resistance in each thermal cycle over time.