Solder paste is one of the most common materials used in surface mount technology (SMT) processes. Typical methods for applying solder paste to devices are needle dispensing or screen printing,each one has specific benefits and drawbacks. The process of jet printing of solder pastes and other functional materials enable higher throughput than needle dispensing while eliminating the material waste generated by screen printing. Volumetric repeatability of the jetted solder paste is a critical property that must be ensured for any deposition technology to be considered as mature for real SMT production. According to the 2016 iNEMI roadmap placement accuracy for these kinds of components will reach 6 sigma placement accuracy in X and Y of 30 um by 2023 [1]. This level of placement accuracy for components must be accompanied by a related accuracy for the deposit of solder paste and related fluids in order to fulfill the related increasing demands on interconnect reliability in increasingly demanding environments with respect to temperature extremes,mechanical stresses and/or production limitations. Data will be presented demonstrating equipment accuracy for jet printing solder paste,jetted process capability for a given output and jet printing process capability for varying outputs within a single board. Throughput comparisons will be presented to understand how jet printing fares against both needle dispensing and screen printing.

Components are still shrinking in the SMT world and the next evolution of the passive components are the m03015 (009005) and m0201 (008004). Today it is seen that the 01005 component is still relatively unused in most of today’s printed circuit board assemblies. Usage is mainly seen on module assemblies and smart products. It has been a slow adoption rate for other product technologies. For most assemblies 0402 components are still common but the 0201s are still rising in usage as there is a movement to use these in server,network,base station products. The m03015 and the m0201 will see primary adoption in the products that require more miniaturization which would be system in packages (modules). These modules would then be assembled into products either through attachment to another assembly or via other interconnect methods. This paper will explore the development of an assembly process (SMT only) for the m03015 component. Solder paste and stencil type will be discussed with results from the evaluations,as well as the placement and reflow of these components. Component to component spacing down to 0.100mm spacing will be discussed as well. AOI and the challenges around this area will be presented in a separate paper and rework will not be discussed at this time. At the time of this writing,an investigation is being started on the m0201 and results at the time of the paper will be briefly touched on as well.

In Power Electronics,increasing attention are drawn to silver sinter materials as an attractive interconnect material for its properties and also as a lead replacement solution. New property demands are longer lifetime,better performance,higher efficiency,lower manufacturing cost and crucially non-lead containing. Specifically,for T0220 application,non-pressure sinter pastes are dispensed on the lead frame followed by die placement. Sintering process is performed in a programmable oven under nitrogen or air atmosphere. Typical non-pressure sintering profile takes approximately 4hrs long to complete,which if shortened,increases attractiveness to adopt non-pressure sintering. In this study,the objective was to investigate using IR radiation to reduce the total sintering profile. A 2-step profile was to reduce sintering defects and encourage maximum diffusion properties. Larger dies would be recommended to hold longer than 30mins to achieve homogenous drying. From our investigations using IR radiation,comparable non-pressure sintered results were achieved with 25% of the standard convection oven profile. In the convection oven,non-pressure sintering is achievable up to typically 25mm² die dimension. Above this,risk of sinter defects increases. With IR radiation,cross section of die sizes above 25mm² did not detect channeling nor voids. From our temperature profiling analysis,the uniform heat distribution within the specimen was a critical improvement,which encourages homogeneous densification of the sintered layer. For dies above 25mm2,young modulus difference between the die’s center and edge reduces to improve reliability. Our analysis also reported increases in die shear strength and higher thermal conductivity. The paper will show the detailed results with this new sintering process.

A production process free from defects,with every production step being reproducible and traceable,is the target of quality assurance in electronics production worldwide. In many cases manual rework processes are not allowed,due to quality related reasons and cost issues. Manual rework is time consuming and cost-intensive,and hidden costs such as productivity rates or personnel training need to be considered. Because of this,assemblies with defects often go through the production process a second time. However,in this case the entire board is exposed to the thermal load,not only the faulty solder connections,which can affect the overall product reliability. An automated zero-fault production concept can provide a cost-effective solution. Automated process control and integrated automated rework enable a soldering process free from defects and completely documented. Process Challenges: Compared to other automated processes,selective soldering is considered as particularly demanding. Structures with small pitches result in a small process window,variable parameters such as flux quantity,temperatures or wetting time play a decisive role in terms of solder joint quality and reliability. In addition,material-related influences have to be considered. The Zero-Fault Production Concept: A controlled and reliable process is a basic requirement for approaching a zero-fault production. Besides the selective mini-wave soldering process with monitoring and control functions for all process steps,the zero-fault production concept incorporates integrated automated optical inspection (AOI) of the solder joints as well as a defined and automated rework soldering process at the fault coordinates,corresponding to the fault classification. This is an advantage from the technical processing point of view as only defective solder joints go through the process again,not the entire board. As all work stations are linked with a bi-directional data transfer,all process steps are completely traceable and reproducible. In addition,analysis of trend and series faults allows process optimization at an early stage. This particularly applies for component placement and the soldering process,however,design faults can quickly be identified as well. With a focus on the critical issues in a selective soldering process,this paper will describe all process steps that need to be controlled to ensure consistently high product quality. In addition,it will describe a production concept enabling automated rework with minimal thermal exposure for the assemblies.

Aerospace Defense High Performance (ADHP) electronics products primarily use tin-lead solders,but electrical and electronic component finishes (i.e.,platings) increasingly are designed for lead-free solders. The knowledge-gap on tin-lead integrity with new component finishes is growing over time. Also,the reworking of components to make them tin-lead compatible presents a component reliability risk. Therefore,it is important to understand and overcome the interfacial reliability risk for every combination of solder alloy and component finish used in ADHP products. The intermetallic compounds,which nucleate and grow during the soldering and use environments of electronics hardware,are of two general types. These are,1) Precipitation Compounds and 2) Diffusion Compounds. The precipitation compounds occur during the soldering process. The diffusion compounds can begin during the soldering process,and can grow during the environmental exposure of the solder connection to the product application (time at temperature,temperature cycling). We report numerous material combinations of soldering alloys and plating metals,where a common finding is that the growth of the diffusion compounds,at the solder-to-plating interface,is a precursor indicator of solder connection interfacial failure. The precursor is associated with vacancy accumulation and observation of Kirkendall voiding. Diffusion between the plating and the precipitation compounds leads to connection separation because the vacancy content of the plating can be up to twenty percent,and that vacancy content accumulates into area voids as the diffusion compounds grow. The diffusion compounds occur concurrent with,or subsequent to,the precipitation compounds. So the precipitation compounds are called first compounds. The diffusion compounds are called second compounds. The second (diffusion) compounds are stoichiometrically richer in the plating metal than are the first (precipitation) compounds. Technical examples show cross-sectional microstructures,and compound chemistry identifications,from the following solder-to-plating systems: tin-lead-to-gold,tin-lead-to-copper,indium-lead-to-gold,gold-germanium-to-nickel,tin-lead-to-iron-nickel and tin-lead-to-palladium. The influence of the first compounds on the mechanical properties of the solder connection can be characterized with predictability equations. However,the second compounds need to be avoided or minimized,by means of material selection (solder alloy,volume),plating design (metal,thickness,area) and processing parameters (plating,soldering). Lead-free solder connections to copper and iron-nickel finishes indicate qualification testing is needed,for lead-free solder alloys,showing their failure precursor compounds and voids are minimized.

Printed circuit assemblies have become more susceptible to a failure mode known as “pad cratering” due to the implementation of several material restrictions. Pad cratering is defined as mechanically-induced fracture between the copper pad/trace and printed circuit board (PCB)laminate. If left undetected during manufacturing,pad cratering can significantly reduce the reliable life of electronic products. The industry needs a fast,precise,non-destructive method to assess pad cratering,as it increasingly moves toward thinner,more mobile products. There are several methods being used in the electronics industry,both destructive and non-destructive,but all have significant limitations. Acoustic emission detection is a broad-area,non-destructive technique that has the potential to detect solder joint fractures. Passive acoustic emission detection (AED) records the sound waves emitted by fracture events during structural loading. This technique typically employs an array of piezoelectric transducers to measure sound waves at the surface; the location of the fracture event is calculated using the positions of the sensors,the time delay between the arrival of the events at the sensors,and the sonic velocity through the medium. This article discusses the development work performed to date by the authors in both transient bend and shock. The general test and data analysis methods are discussed. Transient bend and shock tests,results,and validation are described. Finally,further potential for the application of these methods to the electronics industryIPC-9709are presented.

Printed Circuit Board (PCB) weave texture and weave exposure are conditions that may appear similar if appropriate inspection techniques are not applied in a manner that can differentiate between the two. Weave texture is an area where the glass bundles of the PCB are visible beneath the intact resin of the PCB surface. Weave exposure is when there are openings in the resin of the surface layer of the PCB that expose the glass fiber bundles. Either condition is generally acceptable per MIL-PRF-31032/1 or IPC 6012 (Class 1 &2),as long as 1) exposed or disrupted reinforcement fibers on the horizontal surface of the PCB do not bridge conductors,and 2) the minimum conductor spacing is not violated due to the condition. The objectives of this paper are to describe and provide a summary of methods,approaches and techniques engaged in determining whether the functional performance of the printed wiring assemblies (PWAs) would be impacted by the condition found in a recent case history of weave exposure. Due to solder mask hiding the condition on the majority of the PCBs surface,it was initially thought the condition was weave texture. Some of the PCBs were then built into PWAs. Later it was determined that weave exposure was the condition,(with some weave texture).Due to the risks posed by this type of issue,including contamination and Conductive Anodic Filament (CAF) growth,a variety of techniques were utilized to evaluate the issue and determine the viability of using impacted PWAs. These techniques included,but were not limited to: visual examinations,PCB cross-section analysis,acoustic microscopy,scanning electronic microscope (SEM) evaluation with Energy Dispersive Spectroscopy (EDS),dielectric breakdown testing,Conductive Anodic Filament (CAF) testing,and Ion Chromatography testing. This paper provides a structured and methodical approach to determine the impact of weave exposure. The techniques described below may be utilized as a guideline for others facing a similar predicament to determine final acceptability of the product.

Reliable operation of electronics at higher temperatures requires a combination of performance improvements in components,interconnects and substrates. Ceramic based substrate options can be costly,heavy and prone to mechanical damage. Printed circuit board (PCB) options are restricted to lower working temperatures of the organic resins and degradation of their conductive tracks. A collaborative research programme between project partners has successfully developed innovative materials specifically designed to offer protection to organic PCBs and interconnects allowing them to operate at higher temperatures or for longer durations. Currently,the operation of electronic assemblies at higher temperatures is limited by the ability of copper clad PCBs to maintain circuit integrity. The project has developed a coating material which when applied to printed circuit assemblies (PCAs) makes them more suitable for operating at temperatures above 200oC.This paper summarises the work undertaken by the authors to develop and better understand the performance enhancements produced by these materials. The project brought together a materials supplier,an end-user and are search technology organization to jointly develop,test and implement the solution based on silicone coating materials. This paper focuses on the testing and materials evaluation undertaken to determine the long-term performance of these alternative materials in harsh environments. Details of the electrical performance of component and PCB interconnects between the substrates and components during the test regimes are given as well as the degradation mechanisms experienced in unprotected PCAs. The manufacturing process is outlined including details of the test vehicles utilised. Details of the test methodology used and comparable results for coated and uncoated systems will be given. The results show a significant improvement of mean-time-before-failure (MTBF) for coated PCAs and PCBs compared to uncoated samples. The primary performance improvement is shown to be reduction in the oxidation rate of copper in both the inner and outer layers of copper tracking in the multilayer structures.

The electronics industry could benefit greatly from low cost,easy to apply coatings that can be applied to almost any PCBA surface in order to provide effective and practical water (damage) resistance. In an effort to understand the relationship between the relative costs and benefits of the many varied approaches and materials,we have chosen to focus on state of the art,off the shelf,sprayable and dippable materials and compare them to one another as well as to the industry benchmark of poly(p-xylylene) polymer. According to suppliers,there have been some advancements in materials and techniques but the nature of these improvements as well as the specific formulations of the various materials is a closely guarded secret. Basic compositions and process specifics are given. Among the materials tested,there are two different approaches. One uses a very thin layer of material (as a continuous coating) and the other uses tiny “nano” particles to increase the surface energy of the treated surface in order to prevent water from condensing on the surface. In both cases,water and moisture may be present,but,in theory,they are prevented from wetting the surface. On the “coating” side,according to some suppliers,there have been changes (for example) to the cross-linking properties of polymers to enable a better (more rugged) barrier. On the nano-particle side,smaller and more effective particle materials have been developed. This work is an update/addendum to our prior work [1] with several new and “improved” sprayable/dippable water resistant nano-coatings tested. We conducted Insulation Resistance measurements and other tests/measurements including: Contact Angle,IPC-TM-650,test method 2.6.3.4,85/85,and Salt water exposure and present our findings.

In restricted-space applications,flexible PCBs must be able to fold with especially small bend radii. This in turn requires the return planes associated with microstrip and stripline transmission lines be cross-hatched. But the process of cross-hatching the return planes can significantly degrade the performance of these transmission lines. This paper shows examples of how the cross-hatching the ground plane introduces signal distortion and how changing the size,shape and orientation of the cross-hatch pattern can reduce some of the distortion.