The number one issue identified by the 2009 iNEMI Boundary-Scan survey was problems with obtaining correct and compliant boundary-scan description language (.bsdl) files from the semiconductor industry for use in boundary-scan printed circuit board assembly (PCBA) test generation. The major conclusions from the survey were:
• The semiconductor industry needs to make a greater effort to produce correct and compliant BSDLs.
• A better job needs to be done verifying JTAG hardware compliance to .bsdl files.

Non-compliance is typically found when a test is generated and it doesn’t work! The consequences of not having correct and compliant .bsdl file to generate boundary-scan tests is the inability to generate boundary-scan and if tests cannot be generated,the result is lower overall test coverage for PCBAs,resulting in higher manufacturing costs and lower overall product quality. The work presented here by the iNEMI Boundary Scan Phase 3: Investigation into Challenges of Using .BSDL Files Project group takes a more comprehensive view of the problem by surveying the industry to determine if issues associated with IEEE 1149.1 .bsdl files identified in the 2009 iNEMI Boundary-Scan survey still exist,and if so to what extent,and identify any new issues. Based on the data obtained,the results will be used to raise industry awareness of the issues and potential solutions. Current and best practices for .bsdl file creation and validation will be identified and documented.

Increasing system integration and component densities continue to significantly reduce the opportunity to access nets using standard test points. Over time the size of test points has been drastically reduced (as small as 0.5 mm in diameter) but current product design parameters have created space and access limitations that remove even the option for these test points. Many high speed signal lines have now been restricted to inner layers only. Where surface traces are still available for access,bead probe technology is an option that reduces test point space requirements as well as their effects on high speed nets and distributes mechanical loading away from BGA footprints enabling test access and reducing the risk of mechanical defects associated with the concentration of ICT spring forces under BGA devices.
Building on Celestica's previous work characterizing contact resistance associated with Pr-free compatible surface finishes and process chemistry; this paper will describe experimentation to define a robust process window for the implementation of bead probe and similar bump technology that is compatible with standard Pb-free assembly processes. Test Vehicle assembly process,test methods and "Design of Experiments" will be described. Bead Probe formation and deformation under use will also be presented along with selected results.

Solder ball height inspection is essential to the detection of potential connectivity issues in semi-conductor units. Current ball height inspection tools such as laser profiling,fringe projection and confocal microscopy are expensive,require complicated setup and are slow,which makes them difficult to use in a real-time manufacturing setting. Therefore,a reliable,in-line ball height measurement method is needed for inspecting units undergoing assembly.
Existing stereo vision measurement techniques determine the height of objects by detecting corresponding feature points in two views of the same scene taken from different viewpoints. After detecting the matching feature points,triangulation methods are used to determine the height or depth of an object. The issue with existing techniques is that they rely on the presence of edges,corners and surface texture for the detection of feature points. Therefore,these techniques cannot be directly applied to the measurement of solder ball height due to the textureless,edgeless,smooth surfaces of solder balls.
In this paper,an automatic,stereo vision based,in-line ball height inspection method is presented. The proposed method includes an imaging setup together with a computer vision algorithm for reliable,in-line ball height measurement. The imaging set up consists of two different cameras mounted at two opposing angles with ring lighting around each camera lens which allows the capture of two images of a semi-conductor package in parallel. The lighting provides a means to generate features on the balls which are then used to determine height. Determining and grouping points with the same intensity on the ball surface allows the formation of curves,also known as iso-contours,which are then matched between the two views. Finally,an optimized triangulation is performed to determine ball height. The method has been tested on 3 products and exhibits accuracy within 4um mean squared error compared to confocal ground truth height,and the coplanarity of BGA package as derived from calculated substrate depth results.

Nowadays,consumer electronic product is characterized with miniature,portable,light and high performance,especially for 3G mobile products. More and more fine pitch CSPs (0.4mm) come forth as the times require. However,there’s great challenge related to product reliability when applying Fine pitch CSP. Firstly,Fine pitch CSP has smaller solder balls,0.25mm diameter or even smaller. The small solder ball and pad size will weaken solder connection and adhesive between pad and substrate. Thus pad will peel off easily from PCB substrate. What’s more,miniature solder joint reduces the resistance against mechanical vibration,thermal shock and fatigue failure,etc. Secondly,depositing sufficient solder paste evenly on the small pad of CSP is difficult because stencil opening is only 0.25mm or less which can be solved with higher class stencil,while corresponding higher cost is needed. For this study,we focus these items: • Reliability performance of different SMD or NSMD pads; • Bigger pad size with higher adhesive strength; • Different IMCs and different results(such as Ni crack or thick IMC); • Huge improvement of underfill on CSP; • How to make a better solder paste deposition on pad rely on vacuum support; • How a reliable solder joint grow on the basis of optimized reflow profile;

The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies,which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.
Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50µm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production,there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. =50µm tri-tier bond pad with the die larger than 400mm2).
This paper will address the key challenges of each field,such as the Cu trace design on a substrate for robust micro-joint reliability,TCNCP technology,and substrate technology (i.e. structure,surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided,as well. Finally,this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.

A molded interconnect device (MID) is an injection molded thermoplastic substrate which incorporates a conductive circuit pattern and integrates both mechanical and electrical functions. The thermoplastic material is doped with a metal-plastic additive which can be activated by laser. A laser beam is pointed on the surface of the injection molded plastic to form a metallization track by aggregating the metal additives. The metallized path is then plated with copper,nickel and gold finishes subsequently. MID Technology offers great advantages in design flexibility,device miniaturization,and true 3D integration of complex shapes.
Flip chip bonding of bare die on MID can be employed to fully utilize MID’s advantage in device miniaturization. Compared to the traditional soldering process,thermo-compression bonding with gold stud bumps provides a clear advantage in its fine pitch capability. However,challenges also exist. Few studies have been made on thermocompression bonding on MID substrate,accordingly little information is available on process optimization,material compatibility and bonding reliability. Unlike solder reflow,there is no solder involved and no “self-alignment,” therefore the thermo-compression bonding process is significantly more dependent on the capability of the machine for chip assembly alignment.
This paper presents the studies on flip chip thermo-compression bonding (TCB) of gold stud bumps on MID substrate. Non-conductive paste (NCP) is applied on the MID substrate before attachment of bare dies,and subsequently the dies are compressed at elevated temperatures to bond the gold stud bumps to the substrate pads and to cure NCP simultaneously. Daisy chained test vehicles were designed and built to demonstrate this process with multiple assembly challenges resolved. The test vehicles successfully passed long term reliability testing based on IPC standard IPC-SM-784,although the substrate bond pads experienced excessive deformation during the thermo-compression bonding process at higher bonding forces. Regardless of the bonding forces evaluated,a certain degree of atomic bonding is observed between gold stud and gold plating on the substrate,However,such small scale bonding is not adequate to secure the chip in place,the assembly relies on the contraction of non-conductive paste during the cure process to maintain a reliable bonding interface. Based on reliability test results,the bonding force can be further reduced to minimize the substrate pad deformation while maintaining bonding reliability.

As lead-free alloys shift into high reliability electronics,the issue of tin whisker growth remains a primary concern among those in the industry. Current research shows that there is no perfect alloy for all cases of electronic usage. Industry leaders and researchers continue to study and search for a lead free alloy that is able to withstand harsh environments while maintaining high reliability.

The move to lead free (Pb-free) electronics by the commercial industry has resulted in an increasing number of ball grid array components (BGAs) which are only available with Pb-free solder balls. The reliability of these devices is not well established when assembled using a standard tin-lead (SnPb) solder paste and reflow profile,known as a backward compatible process. Previous studies in processing mixed alloy solder joints have demonstrated the importance of using a reflow temperature high enough to achieve complete mixing of the SnPb solder paste with the Pb-free solder ball. Research has indicated that complete mixing can occur below the melting point of the Pb-free alloy and is dependent on a number of factors including solder ball composition,solder ball to solder paste ratio,and peak reflow times and temperatures. Increasing the lead content in the system enables full mixing of the solder joint with a reduced peak reflow temperature,however,previous research is conflicting regarding the effect that lead percentage has on solder joint reliability in this mixed alloy solder joint.
Previous work by the authors established a protocol for soldering Pb-free BGAs with SnPb solder paste based on solder ball size and target lead content in the final solder joint. The units from that testing were subjected to thermal cycling between -55°C and 125°C and compared to a SnPb baseline assembly. Results showed that mixed alloy joints performed as well as or better than standard SnPb joints under these conditions.
This study continues the previous work with evaluation of reliability in a production design. Functional assemblies were built using Pb-free BGAs in a SnPb solder process and subjected to life testing including accelerated aging and highly accelerated life testing (HALT). Results from this testing are compared to SnPb baseline units and previous product development test results.

Low melting 57Bi42Sn1Ag (BiSnAg) was explored for replacing SAC solders as a low-cost solution. In this study,BGAs with SAC105,SAC305,and BiSnAg balls were assembled with SAC105,SAC305 or 57Bi42Sn1Ag solder paste. Joint mechanical strength,drop test performance,and voiding performance were evaluated against the reflow profile. SnPb was included as a control. The findings are as follows: (1) The microstructure of solder joints showed that,among all of the combinations,only BiSnAg-105 LT and BiSnAg-305 LT exhibited well-distinguishable alloy regions. For SAC-BiSnAg systems,Sn-dendrites were noticeable at LT,while Ag3Sn needles developed at HT. The joints were homogeneous for the rest of the combinations. (2) In the shear test,combinations involving BiSnAg solder were brittle,regardless of the Bi alloy
location and reflow profile,as evidenced by stress-strain curves and morphology of the ruptured surface. The strong influence of Bi on the rupture site may have been caused by the stiffening effect of solder due to the homogenized presence of Bi in the
joint. With the stiffened solder,the brittle IMC interface became the weakest link upon shearing,although the brittle BiSn crystalline structure also contributed to the rupture. (3) In the drop test,all Bi-containing solder joints performed poorly compared with Bi-free systems,which was consistent with shear test results. Drop numbers increased with increasing elongation at break of solder bumps as measured in the shear test. (4) Voiding was affected by flux chemistry and reduced by low alloy homogenization temperatures and solid top factors,but was increased by low surface tension factor,melting sequence factor,overheating factor and wide pasty range factor. Compared to SAC or SnPb systems,the BiSnAg system is low in voiding if reflowed at LT. In this study,voiding had an insignificant effect on shear strength and drop test performance.

This paper is the second of two papers discussing the companies Lower Melt Alloy program. The first paper was presented at IPC APEX2013. The program explores the manufacturability and reliability of three Pb-free Bi-containing alloys in comparison with conventional SAC305 and SnPb assemblies. The first alloy included in the study is a Sn-based alloy with 3.4%Ag and 4.8%Bi,which showed promising results in the National Center for Manufacturing Sciences (NCMS) and German Joint (GJP) projects. The other two alloy variations have reduced Ag content,with and without Cu.
BGA and leaded components were assembled on medium complexity test vehicles using these alloys,as well as SAC305 and SnPb as base line alloys for comparison. Test vehicles were manufactured using two board materials,170°C glass transition temperature (Tg) and 155°C Tg,with three surface finishes: ENIG,ENEPIG,and OSP. The ATC testing was done at -55°C to 125°C with 30 minute dwells and 10°C/min ramps,and vibration testing at two G-Force test conditions with resistance failure monitoring was performed on the daisy chained components.
In this paper,the results of 3000 ATC cycles are discussed. The paper gives a detailed description of the technique for the vibration testing using 2 and 5 G harmonic dwells. In addition,the results of vibration testing and some preliminary data analysis are discussed. These results provide data for further statistical analysis leading to the choice of proper combinations of the solder alloys,board materials,and surface finishes for high reliability applications.