PCB assembly designs become more complex year-on-year,yet early-stage form/fit compliance verification of all designed-in components to the intended manufacturing processes remains a challenge. So long as librarians at the design and manufacturing levels continue to maintain their own local standards for component representation,there is no common representation in the design-to-manufacturing phase of the product lifecycle that can provide the basis for transfer of manufacturing process rules to the design level. A comprehensive methodology must be implemented for all component types,not just the minority which happen to conform to formal packaging standards,to successfully left-shift assembly and test DFM analysis to the design level and thus compress NPI cycle times. The elements of such a solution include implementing de-facto standards for package and pin-type classifications,as well as DFM analysis rules that are associated with these classifications and the intended manufacturing processes. The resulting solution enables the transfer of DFM rules from the manufacturing process expert to the design and NPI engineers on the design side responsible for verifying manufacturing-process compliance of new product designs. This paper will demonstrate the technological components of the working solution: the logic for deriving repeatable and standardized package and pin classifications from a common source of component physical-model content,the method for associating DFA and DFT rules to those classifications,and the transfer of those rules to separate DFM and NPI analysis tools elsewhere in the design-through-manufacturing chain resulting in a consistent DFM process across multiple design and manufacturing organizations. Following establishment of a common source of component definitions and classifications,rules-based generation of assembly-level machine libraries is enabled from the same source that drove the DFM process,resulting in right-first-time launch of a new product into the manufacturing process.

The miniaturization of electronic devices demands the continued shrinking of system z-height. A significant consequence of these ultra-thin systems is yield loss due to high temperature warpage during SMT reflow. This warpage results from the Coefficient of Thermal Expansion (CTE) mismatch between the key materials,such as Si,organic substrates,and Cu in the SoC-to-PCB system stackup. Warpage impacts the solder joint formation,and can result in both bridging and open defects due to the compressive and expansive forces experienced during solder joint collapse at high temperatures. Solutions typically consist of mechanical reinforcement such as molding compounds or metal stiffeners applied to the substrate,and while successful,these solutions can be expensive. In this study,we investigate the impact of temperature on the system warpage profile and find that reducing the reflow peak temperature from 245C to <180C appreciably reduces the amount of warpage,thus improving SMT yields. To reduce the reflow temperature,we have used Bi-Sn-Ag solder alloys with a M.P. of 138C. Although reduced reflow temperature improves SMT yield,Bi containing solders have been previously shown to induce brittleness [1] that can jeopardize joint reliability. To overcome this,we further investigate a class of Bi-based solders that also contain epoxy resins to mechanically reinforce the solder joint. This paper describes the yield improvements and defect mechanisms as a function of temperature as well as the impact of epoxy based solder reinforcement materials on SMT process yields. Lower reflow temperatures bring added environmental benefits and we have conducted an analysis of the potential energy and cost savings in HVM due to lowering reflow temperatures by 65C-80C.

Sn3.0Ag0.5Cu (SAC305) is currently the most popular near eutectic lead-free alloy used in the manufacturing processes. Over the last several years,the price of silver has dramatically increased driving a desire for lower silver alloy alternatives. As a result,there is a significant increase in the number of alternative low/no silver lead-free solder alloys available in the industry recently. Our previous study showed that many alternative low silver solder paste materials had good printing and wetting performance as compared to SAC305 solder pastes. However,there is lack of information on the reliability of alternative alloy solder joints assembled using alternative low silver alloy solder pastes. In this paper,we will present the reliability study of lead-free solder joints reflowed using various lead-free alloy solder pastes after thermal cycling test (3000 cycles,0°C to 100°C). Six different lead-free pastes were investigated. SAC305 solder joints were used as the control. Low and no silver solder pastes and a low temperature SnBiAg solder pastes were also included.

Since the implementation of the European Union RoHS directive in 2006,the electronics industry has seen an expansion of available low-silver lead (Pb)-free alloys for wave soldering,miniwave rework,BGA and CSP solder balls,and,more recently,solder pastes for mass reflow. The risks associated with the higher processing temperatures of these low-silver (Ag between 0-3 wt%) solder alloys,such as potential laminate or component damage,increased copper dissolution,and reduced thermal process windows may present manufacturing challenges and possible field reliability risks for original equipment manufacturers (OEMs). In order to take advantage of potential cost reduction opportunities afforded by these new alloys,while mitigating manufacturing and reliability risks,the company has defined test protocols [1-4] that can be used for assessing new Sn-Ag-Cu (SAC),Sn-Ag,and Sn-Cu alloys for general use in electronics. This paper describes initial test results for low-silver alloys using these solder paste alloy assessment protocols for BGAs and leaded components,and the impact of the alloys on printed circuit assembly process windows. Specific pass/fail criteria for acceptance of an alloy are not included,however,as they may vary across industry segments. The assessment evaluates wetting behavior,solder joint thermal fatigue and mechanical shock reliability,intermetallic formation,general physical joint acceptability,and copper dissolution. The variables include multiple component types: two BGA components with the same paste/ball alloy combinations,and numerous leaded components that include common component platings. Surface mount (SMT) process temperature windows are typically constrained on the low end by the ability to melt solder and form acceptable joints,and on the high end by the maximum process temperatures of other materials,such as components. These two constraints have led to a process window of approximately 25°C when soldering with more conventional,Sn-3.0Ag-0.5 Cu paste. Low-silver SMT alloys have been found to reduce the thermal process window even further.

Interconnects between layers of circuitry in multilayer printed circuit boards are produced by drilling and plating. Drilling quality can have a major impact on the longevity of the plated interconnect. Mechanical drilling is especially challenged when the printed circuit board panel is not perfectly flat. Many printed circuit boards (PCBs) contain components and features that create topography that is either expensive or impossible to level out during drilling and other manufacturing processes. A novel material and method have been developed,and benefits demonstrated,that is highly conformable providing a means to produce a level drilling surface without altering or negatively impacting the printed circuit board. In summary,this paper will present a new technology and process in mechanical drill backing material designed to be used in rigid multilayer,rigid-flex and flexible printed circuits. The features and benefits of the technology will be presented as well as examples showing method of use,a comparison to standard drilling methods and the resulting benefits of using this material.

What are the Raw Material Risks?
-Today PCB Suppliers handle a range of customers with different end use environments
-Telecommunications
-Automotive
-Consumer electronics
-Medical
-Industrial,others...
-PCB manufacturers' objective -- minimize variety of solder to as few as possible (not just soldermask,other materials as well)
-Unfortunately subsequent assembly steps such as finishes,fluxes,solder materials are often overlooked
-New class of solder mask defects are influencing the reliability of the finished end product
What is the Subsequent Process Risk?
-After solder mask application,PCBs are exposed to process steps:
-Surface finish
-Wave soldering and reflow processes
-Local/selective wave solder and rework applications
-Blowholes can act as acceptors and reservoirs
-Interaction of process chemicals

Today’s wide variety of laminate materials and specialized dielectric choices pose a challenge for process engineering. In particular,smooth surfaces,such as polyimide,flex circuit substrates and rigid-flex constructions with window cut-outs,can be a challenge for electroless copper and plating processes. Conventional electroless copper systems often required pre-treatments with hazardous chemicals or have a small process window to achieve a uniform coverage without blistering. To overcome the challenge of metallizing smooth surfaces,a new stress-free electroless copper was developed to serve this important sector of the printed circuit industry.

The rapid growth of electronic devices across the globe is driving manufacturers to enhance high-speed mass production techniques in the printed circuit board assembly arena. As manufacturers drive to reduce costs while maximizing production by expanding facilities,updating automation equipment,or implementing lean six sigma techniques,the potential to build scrap product or rework printed circuit boards increases dramatically. Manufacturers have two general paths to reduce the costs of high-speed printed circuit board assembly production. The first path is to reduce cost by focusing on high quality printing and mounting. The other,increasingly popular option is to utilize low-cost materials. In either case,the baseline must provide a consistent high-speed solder paste printing method,which considers the fill,snap-off,and cleaning processes. Building on our expertise and testing,this paper will highlight the two trains of thought with specific focus on how low-cost materials affect print performance. It will also explore technologies,which can help provide stable,high-speed screen-printing. In the end,both paths aim to maximize profitability. As such,understanding how manufacturers can successfully integrate low-cost materials will help ensure high-quality production,reduce costs,and maximize profitability in a high-volume printed circuit board assembly environment.

The SMT stencil is a key factor in the solder paste printing process. It has been shown repeatedly that print quality has the largest impact on end-of-line quality,and a good print process can make or break the profitability of building a PCB assembly. A good print process relies on a good stencil. Much research has been performed to identify individual key factors in stencil performance; this paper and presentation discuss the real-world application of numerous findings. They review the numerous considerations in design,material,manufacturing and coating considerations,and how to best choose them based on PCB layout.

Solder paste screen printing is known to be one of the most difficult processes to quality assure in Printed Board Assembly (PBA) manufacturing. An important process step in solder paste screenprinting is the under stencil cleaning process and one of the key materials in this process is the cleaning paper. This,often neglected,material affects the cleaning process and thereby also the print quality. It is therefore important to perform tests of different cleaning papers before one could be chosen. This article describes how cleaning papers can be tested and it also tells how big differences it can be between different materials.