The use of bottom terminated components (BTC) has become widespread,specifically the use of Quad Flat No-lead (QFN) packages. The small outline and low height of this package type,improved electrical and thermal performance relative to older packaging technology,and low cost make the QFN/BTC attractive for many applications.
Over the past 15 years,the implementation of the QFN/BTC package has garnered a great amount of attention due to the assembly and inspection process challenges associated with the package. The difference in solder application parameters between the center pad and the perimeter pads complicates stencil design,and must be given special attention to balance the dissimilar requirements.
The lack of leads on the QFN/BTC package and the low standoff height result in significantly less compliance relative to other package types,making the QFN/BTC package more susceptible to CTE mismatch issues. Careful assembly of QFNs and proper printed circuit board (PCB) design can result in acceptable reliability depending on the overall design. One area that has not been well addressed,however,is the impact of die to package size ratio,and how this factor should be considered in circuit card assembly. IPC-7093 mentions the inverse relationship between relative die size and reliability,and Syed and Kang found the relationship to be non-linear,yet die size is seldom noted in component datasheets,and vendor recommendations do not include this ratio as a factor in assembly.
In this study,the volume of solder used in assembly of two QFN/BTC packages will be varied to investigate the relationship between standoff height and thermal cycle life,and to determine acceptable process limits with respect to first-pass yields. The QFNs selected have dissimilar die to package size ratios to assess the impact of this factor on the process window. Solder joint defect levels and thermal cycle results will indicate the ability to adjust manufacturing parameters to achieve a balance between the two objectives of process yield and reliability. The results will define a process window that provides the optimal installation of these packages.

As channel speeds approach 25 Gbps,near the expected maximum bandwidth for traditional copper-based PCBs,every available tool to minimize total insertion loss in the board material system will need to be deployed. Material suppliers have devised low-Dk,low-loss dielectrics and fiberglass,as well as ultra-low-profile copper foils. However,one of the last remaining factors has not yet been quite so actively developed – the surface treatment applied by the PCB shop to the innerlayer cores prior to lamination.
In a previous paper presented at IPC,we described the effects of copper foil types,of varying levels of roughness,upon measured insertion loss of a stripline structure. We further showed the relative impact of different surface treatments (oxide and oxide alternative) which were then current in the industry. Recently,however,PCB chemical suppliers have begun offering new treatments targeted specifically at insertion loss and surface roughness minimization,whereas prior formulations were aimed at maximization of bond strength and prevention of pink-ring.
This paper builds upon our previous work by examining the insertion loss impact of such chemistry,holding constant the dielectric,test vehicle board design,and measurement technique used earlier. We are thus able to characterize the relative contribution of lower-roughness innerlayer treatment chemistry to loss reduction,as compared to conventional formulations.
1. Introduction and Background
2. Samples and Measurement Method
3. Measured Insertion Loss Results
4. Discussion and Opportunities for Further Work

This paper is an extension of an IPC paper [1] presented last year which addressed microwave insertion loss of common PCB transmission line circuits. Insertion loss of these circuits is made up of 4 components; conductor loss,dielectric loss,radiation loss and leakage loss. The previous paper focused on conductor loss and dielectric loss,whereas this paper will address radiation loss.
Radiation losses can be a disruptive force for many different reasons. Designs which are sensitive to EMI (ElectroMagnetic Interference) can be affected by radiation loss of a circuit and specifically how the radiated energy may corrupt neighboring circuits. Also the performance of loss-sensitive systems can be impacted with the addition of radiation loss when it is not fully considered. Finally,broadband high frequency RF and millimeter-wave applications certainly have issues with radiation loss and designers expend many efforts to account for these losses.

Nickel-palladium-gold-finished terminals are susceptible to creep corrosion. Excessive creep corrosion can result in device failure due to insulation resistance loss between adjacent terminals. The mixed flowing gas test has been demonstrated to produce creep corrosion on parts with nickel-palladium-gold finished terminals. Conformal coats are often used to protect printed wiring assemblies from failure due to moisture and corrosion. However,coating may not be sufficient to protect lead terminations from failure. In this study,acrylic,silicone,urethane,parylene,and atomic layer deposit (ALD) coatings were examined for their effectiveness at preventing corrosion of nickel-palladium-gold-finished terminals. The coverage of each coating was examined,and assemblies were subjected to eight hours of mixed flowing gas as well as temperature cycling. Non-uniform coating thickness was observed in the areas of the terminals. On some areas,little to no coating material was found for the acrylic,silicone,and urethane coatings. Parylene,which had the most uniform coating,was found to provide the best resistance to corrosion,while corrosion products were observed on the terminals of inspected parts protected by the other coatings.

The iNEMI technical subcommittee on creep corrosion is developing a flowers-of-sulfur (FOS) based qualification test for creep corrosion on printed-circuit boards (PCBs). The test setup consists of a 300-mm cube chamber with two means of mounting the test specimens and flowing air over them to expose them to constant,predefined humidity and temperature conditions and sulfur and other contaminants. The FOS chamber performance has been evaluated using copper and silver foils and preliminary test runs have been conducted on PCBs from a manufacturing lot known to have failed in service. The effect of air velocity on the copper and silver corrosion rates was quite linear. The effect of humidity on copper and silver corrosion rates in the low air velocity range of less than 0.1 m/s showed a strong dependence on relative humidity. In the high velocity range of 1 m/s,there was no clear dependence of humidity on copper and silver corrosion rates. A means has been developed for applying controlled concentration of ionic contamination on selected local areas of test PCBs. Preliminary test runs have shown that ionic contamination found in fine dust may be a necessary condition for copper creep corrosion. Printed circuit boards from a manufacturing lot that suffered creep corrosion in service,with and without dust contamination applied to them,were tested in a FOS chamber at 60oC with 1 m/s air flowing over them. The PCBs with no dust contamination did not suffer creep corrosion in the 3-day test; whereas,the PCBs with dust contamination suffered creep corrosion with morphology similar to that occurring in the field.

The objective of this study is to evaluate conformal coatings for mitigation of tin whisker growth. The conformal coatings chosen for the experiment are acrylic,polyurethane and parylene. The coatings were applied in thicknesses ranging from 0.5 to 3.0 mils on 198 bright tin plated coupons with a base metal of either Copper C110 or Alloy 42. Prior to coating,light scratches were applied to a portion of the coupons,and a second fraction of the coupons were bent at 45° angles to provide sources of stress thought to be a possible initiating factor in tin whisker growth. The coupons have been subjected to an environment of 50°C with 50% relative humidity for 9.5 years. Throughout the trial period,the samples were inspected by both optical and scanning electron microscopy for tin whisker formation and penetration out of the coatings by tin whiskers. Tin whiskers were observed on each coupon included in the test,with stressed regions of the bent samples demonstrating significantly higher tin whisker densities. In addition,the Alloy 42 base metal samples showed greater tin whisker densities than the Copper C110 base metal samples. There were no observable instances of tin whisker penetration out of the coatings or tenting of the conformal coat materials for any of the non-stressed test coupons. The stressed coupons demonstrated tin whisker protrusion of the 1.0 and 2.0mil thick acrylic coating and the 1.0mil polyurethane coating for the Alloy 42 base metal samples. The greater thickness coatings did not demonstrate tenting or tin whisker protrusion. Also included in this paper are tin whisker inspection results of tin-plated braiding and wire that was exposed to an environment of 50°C with 50% relative humidity for over five years.

Embedded capacitors offer board designers the ability to address the demands of high switching speeds and high I/O count packages while stemming the proliferation of minute decoupling capacitors. Nevertheless,the incorporation into a printed circuit board of a thin dielectric layer between power and ground can introduce some unique quality and reliability challenges. Environmental stresses can degrade electrical performance over time,with sudden dielectric breakdown representing a worst case scenario. This presentation will review recent findings concerning the reliability of planar embedded capacitors,including failure modes,mechanisms and models. The emphasis will be on epoxy– BaTiO3 composite dielectrics,although other variants will be discussed.

In light of new process and product technologies in the field of embedded components,questions arise with respect to advantages and potential disadvantages to standard SMT component placement when considering reliability.
This paper is the second part in a progressively complex series of comparative analyses,testing the reliability of standard SMT components in comparison to their embedded counterparts.
In the initial round of comparative tests,we analyzed passive components. In this second part we will compare the performance of similarly specified embedded dies and standard surface mounted CSPs which are designed to simulate an active component (“dummies”) in terms of interconnectivity
The applied reliability tests shall include:
? Drop Test per JEDEC JESD22-B111: 1500g / 0.5ms
? Thermal cycle testing (TCT) per JEDEC JESD22-A104: -40°C / +125°C
? Bend Testing – Based on the IPC/JEDEC 9702 (Monotonic Bend Characterization of Board-Level Interconnects)
With these tests,as with the initial paper on embedded passives,we aim to define possible limitations,advantages,disadvantages and areas of functional application which are relevant to this direct comparison. With the addition in this study of one mechanical bend test we hope to introduce a more well-rounded picture of the reliability one should expect for different instances and component placement methodologies.
As the usage,as well as fields of application,of embedded components increases in part due to more stable and refined methods of manufacturing,it is worthwhile to examine them based on industry norms and standards as a source of comparison to traditional manufacturing methods. Part of this analysis is therefore to investigate the feasibility of employing such standards in the context of embedded components. This investigation,in turn,should offer us a holistic perspective to other current industry projects,such as the EU-funded “Hermes”.

The utilization of embedded components has increased across many applications in various industries,and with rapid emergence of technologies and the need to secure IP,new methodologies are being used to satisfy market requirements. As design teams face constant pressure to implement the latest embedded component technologies,such as embedded SoCs directly within the laminate,many workarounds are used during the design process,leading to costly errors during the manufacturing process. In this session,we will explore the various technologies and challenges with embedded components for current and future designs. We will also discuss new methods to accurately model and design using the latest embedded component technologies,how to eliminate work-arounds during the design process,and how to minimize errors in manufacturing.

The demands on volume delivery and positioning accuracy for solder paste deposits are increasing as the size and complexity of circuits continue to develop in the electronics industry. According to the iNEMI 2013 placement accuracy for these kinds of components will reach 6 sigma placement accuracy in X and Y of 30 um by 2023 [3]. This study attempts to understand the dependencies on piezo actuation pulse profile on jetting deposit quality,especially focused on positioning,satellites and shape. The correlation of deposit diameter and positioning deviation as a function of piezo actuation profile shows that positioning error for deposits increase almost monotonically with decreasing droplet volume irrespective of the piezo-actuation profile. The trends for shape and satellite levels are not as clear and demand further study.