Most manufacturers of electronics grade glass fiber reinforcement used in today’s laminates apply treatments to enhance the bonding strength between the inorganic e-glass and the epoxy matrix which surrounds it in the laminate structure. These treatments,when properly formulated and applied on the glass fibers help to prevent glass-resin delamination due to mechanical stresses or due to thermal excursions during the laminate lifecycle. The thermal excursions can include multiple reflow cycles followed by wave soldering and in some common circumstances a cycle or two of rework. However,such laminates continue to develop glass-resin delamination that promotes a form of electro-chemical migration that leads to a loss of electrical insulation resistance between opposing biased conductors. This phenomenon is commonly known as conductive anodic filament (CAF). The glass-resin delamination can also contribute to a reduction in the mechanical flexural strength,which is not the focus of the present paper. The probability of CAF failure is a function of temperature,moisture content,the voltage bias,manufacturing quality and processes,materials and other environmental conditions and physical factors. The present paper discusses the glass treatments and examines the effects of thermal and combined thermal/moisture exposure on the glass-resin interface. Atomic force microscopy is used for examination of sites to track the state of degradation and changes in the mechanical properties. Micro-Fourier transform infrared spectroscopy is used to track the progression and diffusion of the inter-penetrating network formed as a result of inter-diffusion between the glass-treatments and epoxy laminate material. The results of the studies are expected to show the progression of damage and provide unique quality assurance and failure analysis insights into this less reported contributor to printed circuit board quality.

Internet of Things (IoT) adoption pushes the boundaries of Printed Circuit Board (PCB) miniaturization and speed employing more hybrid stack-ups. The complexity of PCB stack up designs,material selection,advanced processing,and subsequent assembly requirements are driving novel approaches to accelerate engineered solutions. To support the aggressive PCB product development cycle times,the accuracy of physics-based predictive modeling must improve,and the number of lengthy Design of Experiments (DoE) minimized. To facilitate this,effective material characterization techniques and modeling capabilities of these complex systems have been developed,with the goal to mitigate risk,increase reliability and reduce engineering time while ensuring a manufacturable solution. In general,the stress induced on interconnects increases as the interconnect size decreases. However,to accurately model the physical behavior (stress and strain) of PCB interconnects in design stack ups during a reflow or lamination processes requires material property information which necessarily is not present on a typical materials’ supplier datasheet. Some parameters are also not readily available using standard measurement techniques. Additionally,typical numbers in a laminate datasheet only apply to a standard glass style and resin content. Glass style and resin content have a dramatic influence on the end product mechanical properties. Also,the composite nature of PCBs not only result in its thermomechanical behavior to differ along the X,Y,and Z directions,but also relax over time due to the viscoelastic nature of the epoxy resin. Therefore,the anisotropic and viscoelastic properties of PCB materials must be measured. The measurement techniques discussed here are not part of any formal IPC testing protocol currently. However,they capture properties of PCB materials at the small scale very effectively. They rely on using a Dynamic Mechanical Analyzer (DMA)instrument for measurement purposes. These advancements in material characterization and modeling provide insights into micro-via reliability for next generation PCB miniaturization and high-speed signals.

Printed wiring boards(PWBs) have recently been experiencing higher thermal stress in car electronics and high current equipment,etc. In this study, the effects of structural factors and material properties on thermal fatigue life of plated through hole (PTH) in multilayer PWB havebeen investigated by finite element method (FEM) based on Box-Behnken experimental design.This methodology showed the effects of single factor and interactions of multiple factors of PWB on the strain causing an occurrence of cracks in copper (Cu) plating of PTH. The simulation was conducted with obtained properties of thin Cu plating in previous research and a model of a simplified glass cloth equivalent to a cross section of a PWB. It became clear that the effects of Cu plating thickness of PTH,CTE (coefficient of thermal expansion) and elastic modulus of PWB material were significant on inelastic strain range (?ein) in PTH during thermal fatigue. PTH pitch,though,did not haveameasurable impact. The influence of PWB material Tg was found to be so overwhelmingly strong in the experimental design that behavioursof other factors became too muted to be analysed,which means Tmax should be below Tg. A formula of the ?ein,in consideration of the significant factors and its temperature-scaling factor related to ?T,was proposed.In addition,the ?einbecame large in accordance with shape and size of roughness of PTH. When the Cu plating of PTH obeys Manson-Coffin rule, the thermal fatigue life of PTH in consideration of the structural and material factors,can be predicted by the proposed formula on?einand the low-cycle fatigue life prediction law of Cu plating obtained by previous research. Theacceleration factor(AF)equation was established and validated by test data using various PWBs and temperature conditions in temperature cycling test (TCT). The calculated AF roughly agreed with the ratios of Weibull average of TCT results.

This work presents the fabrication of embedded inductors and the experimental laser machining of gaps in the underlying ferrite structure. Design calculations are presented for a test coupon of power inductors. These devices are designed for use in DC/DC converters operating in the 500kHzto 5 MHz range and having inductance values between 1 to 10 uH. The power inductors are constructed by embedding on a ring-shaped ferrite cores (toroids) into an FR-4 substrate,laminating copper foil to the top and bottom surfaces,imaging and etching conductive windings on the top and bottom surfaces. The windings are interconnected with plated-through-hole (PTH) vias. Gapping can be achieved with different laser systems,each having specific benefits and trade-offs. For this experiment,a YAG laser system was used to produce a 0.2 mm gap into a 6.35 mm OD core. Inductance values are presented for before and after the gapping procedure.

As the IoT market demands higher data rates and processing,the PCB technology is driving for smaller form factors,higher signal densities,and advanced material solutions. Miniaturization has been a common trend. Besides reduction in transmission-line and space widths,higher density and bump pitches down to 200 microns,as well as smaller diameter microvias down to 50 microns will be required. The finer features challenge suppliers of equipment,chemistry and materials to find solutions to support the PCB fabrication requirements. This presentation addresses the science and technologies developed in collaboration with supply partners to understand,develop and deliver a 10-layer“substrate-like PCB+” (SLP+) with50 micron diameter stacked microvias,transmission line and space of sub-25 microns and full array 200 micron pad pitch circuit technology solution to enable the next generation of IoT PCB requirements. This SLP+ technology goes beyond the MSAP/SLP technology that several suppliers are currently implementing. The sub-25 µm line and space is achieved with a modified semi-additive process (MSAP) that electroplates copper through openings in the dry-film,instead of using the dry-film as an etch resist. The initial SLP+ designs with leading smartphone customers and M2M modules are in the development phase. The extension of this technology drives feature sizes down to sub-25 micron line/space and 200 micron solder-bump pitch and below. This technology allows down to 200 µm pitch ICs to be directly attached to the PCB,thereby eliminating the need for a BGA substrate. Without the BGA substrate,reductions in z-height are achieved. The thermal resistance to the PCB plane and any rear heatsink is reduced by eliminating the BGA substrate. Similarly,signal integrity is improved by removing impedance discontinuities at the additional interfaces of the BGA substrate. Consumers will see their devices shrink beyond the current state-of-the art,and with performance improvements. The presentation will demonstrate ‘advanced high-density interconnect’ produced in high volume in collaboration with suppliers. The interconnect solutions include a single line between pads at 200 µm-pitch,and two lines between pads at 250 µm-pitch. Thermal cycling (air-to-air and liquid-to-liquid),and 10X solder reflow reliability test results will be presented.

Misregistration of holes is the maximum amount of variation between the centerlines of all terminal pads within one plated through hole in a printed circuit board. The impacts of misregistration can be very serious due to possible electrical opens caused by breakouts or a short or intermittent connection due to a violation of the minimum clearance. This study highlights the differences in registration in Printed Circuit Board (PCB)samples made by the same supplier at two geographical locations. The intent is to determine a statistical correlation between the populations of registration error measurements taken on samples,from layer-to-layer or across layers,and reliability or performance risk. The study includes comparisons between PCB samples made in both the locations. The focus of the comparison includes studying whether both populations reflect the same statistical results,trying to understand where the difference in population occurred and maybe answer the question -which population has the lower amounts of misregistration between layers. Misregistration occurs during board fabrication and is directly attributed to problems involved with the production of the artwork,with artwork materials,with the setup procedures during lamination,and/or with the dimensional instability of the laminate materials used.

Sixteen simple inorganic salts were separately dissolved in water to a specific concentration,applied to separate Surface Insulation Resistance (SIR) coupons,dried and then the coupons were subjected to common SIR testing. A correlation between the final SIR resistance readings and the hydrated radii and ionic charges of the salts has been found. Squares of bare FR4 were immersed in more concentrated solutions of the same salts,rinsed,dried,ground up,leached and the concentrations of the liberated salts were obtained by ion chromatography and inductively coupled plasma optical emission spectroscopy. The results show some discernible correlations with the SIR results.

Rosin-based no-clean solder pastes are the most widely used solder pastes in the world and dominate consumer electronics assembly. The most common rosin-based no-clean solder paste reflow environment is air,which has some obvious advantages such as no-cost and tombstoning mitigation. However,there are a number of manufacturers that use a nitrogen reflow environment for reasons ranging from “shinier” solder joints to head-in-pillow (a.k.a. head-on-pillow) defect mitigation. Most solder paste manufacturersperformJ-STD-004 qualification tests in air unless the solder paste specifically requires a nitrogen reflow environment. Of the J-STD-004 tests,the Surface Insulation Resistance (SIR)test is designed to predict the electrical reliability of a no-clean flux residue. In this test,solder paste is printed onto a test coupon and reflowed. This reflow is typically conducted in air,especially for a rosin-based no-clean solder paste. Knowing that the SIR values are typically the result of a reflow heating cycle conducted in air,some have asked if and to what degree would the SIR values be different if the reflow heating cycle had been conducted in nitrogen. This paper will attempt to address this concern. For this work,three commercially available SAC305 Type 4 rosin-based no-clean solder pastes were used: a halogen-free (ROL0) paste with a traditional residue; a halogen-free (ROL0) paste with a residue optimized for pin-probing; and a halogen-containing (ROL1) paste with a traditional residue. These three different solder pastes were used to see if different chemistries respond differently to a nitrogen reflow environment. These solder pastes were subjected to a total of four different reflow profiles: a nitrogen ramp-to-peak (RTP) profile,a nitrogen soak profile,an air ramp-to-peak (RTP) profile,and an air soak profile. Per J-STD-004B,IPC-TM-650 2.6.3.3 and 2.6.3.7 are the instructions used for SIR testing. In these procedures,solder paste is stencil printed on to IPC-B-24 SIR boards using a .006”/150µ thick stencil. Each B-24 SIR board has four SIR patterns; A through D. Three SIR boards are prepared per paste per scenario. Also,two controls are prepared. The SIR data from these boards will be shared and compared.

Prior to any conformal or chemically vapor deposited coating process,specific areas and components-often called “keep out zones”-on the printed circuit board (PCB) assembly are generally masked to shield them from exposure to coating materials. There are several approaches to masking and,traditionally,this has been achieved through the use of tapes (applied manually),UV curable masking materials,latex-based products and,more recently,a dispensable,peelable hotmelt material. Masking materials,however,can leave residues. These residues may have to be cleaned as there could be a risk of corrosion,electrochemical migration and/or parasitic current leakage. This paper will evaluate polyimide tape,UV curable,latex-based,and hotmelt masking materials and compare residue production of each,in addition to testing the products in relation to performance with no-clean solder paste residues. Results of surface insulation testing (SIR) per IPC TM-650 2.6.3.3 along with Fourier Transformed Infrared Spectroscopy (FTIR) analysis of material residues will be presented.

Since the introduction of lead-free soldering technology,voids in solder joints have been a topic of intensive investigations and discussions. One issue of detailed investigations is the formation mechanism of voids in solder joints. The objective of these activities is the assessment,if and how voids can be reduced to a low or at least acceptable level. The second question for deeper analyses is the effect of voids on solder joint reliability. If the potential for elimination or reduction of voids in solder joints is found to be low,this question comes automatically into focus. Especially within the automotive industry or other business sectors with high reliability requirements for electronic assemblies the relevance of voids for product reliability is still a matter of debate. This is why this paper tries to give a general overview of mechanisms governing void formation,an assessment of the relevance of different influencing parameters on void formation as well as an assessment of the effects of voids on solder-joint reliability. Widely known facts or findings from other studies are combined with additional studies on issues of special interest. The whole paper wants to explain current understanding of solder joint voiding,primarily as an insight on this topic from the perspective of an automotive supplier,but in a next step also as a statement and input for further discussions within scientific and technological working groups dealing with this issue.