An estimated 80% of all SMT assembly in the world is performed with a no-clean soldering process,largely due to the
predominance of consumer-type electronics. The continuing trend of increasing miniaturization that dominates modern electronics devices requires no-clean flux residues to be as benign and electrically resistive as possible. Solder pastes with a IPC J-STD-004 [1] classification of ROL0 or ROL1 rely heavily on two basic mechanisms to render the flux residue as “noclean”: (1) the encapsulating properties that the rosin provides and (2) the heat activation/decomposition of the chemicals in
the flux,commonly known as “activators.” The latter is generally known in the industry,but is rarely taken into consideration for reflow profiling in SMT assembly. Optimization of a reflow profile often focuses on mitigating defects such as voiding,tombstoning,graping,slumping/bridging,etc. However,little thought is given to the reflow profile’s effect on the electrical
reliability of the no-clean flux residue. Because of the wide variation in size and thermal density of SMT components and PCBs,achieving a reflow profile that equally heats the entire assembly can be challenging and often impossible. The temperature under a large component,such as a BGA,is often markedly cooler than a smaller component,such as a passive resistor or capacitor. This paper will discuss an experiment that studied the effect of reflow profiling on the electrical reliability of no-clean flux residues that can be measured using IPC J-STD-004[1] surface insulation resistance (SIR) testing. Both a
halogen-free (ROL0) and a halogen-containing (ROL1) Pb-free no-clean solder paste,exposed to various reflow profiles,were
used in this study.

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Looking back twenty-five years ago,the solder pastes residues had to be cleaned after reflow due to their corrosive nature; two ways of cleaning were possible,either with solvent or by using water,with or without detergent. Now the assembly world is mainly no-clean: paste formulation is safer in terms of chemical reliability and process costs are reduced without cleaning. However,some applications,i.e. military,aerospace,high frequency,semiconductor require a perfect elimination of the residue after reflow. There are several options to achieve this result: the use of a no-clean paste which residue can be removed with the most suitable cleaning method or use the paste desiged to be cleaned,as a water soluble solder paste.
The water-soluble solder pastes generally show great wettability because of tehir strong activation but they are also known to have shorter stencil life and to be more sensitive to working conditions as temperature and humidity,compared to the no-clean pastes. Additionaly,with the components stad-off getting smaller and smaller,washing residues with water only is more and more challenging due to its high surface tension; the addition of detergent becomes often necessary.
The purpose of this paper is to highlight the differences between these two families of solder pastes to guide users in their choice. This will be achieved through the comparison of several recent water-soluble and no-clean formulations as far as reliability is concerned. First the printing quality will be evaluated (viscosity,tack,cold slump,printing speed according to pressure,stemcil life,idle time,printing consistency). Then the reflow properties will be compared (hot slump,solderballing,refow process window,wetting ability on different finishes). Finally the residue cleanibility will be assessed. The IPC SIR will be also done to conclude the study. Bth standardized tests and production tests will be used to evaluate the performance on these two kinds of solder pastes.

Looking back twenty-five years ago,the solder pastes residues had to be cleaned after reflow due to their corrosive nature; two ways of cleaning were possible,either with solvent or by using water,with or without detergent. Now the assembly world is mainly no-clean: paste formulation is safer in terms of chemical reliability and process costs are reduced without cleaning. However,some applications,i.e. military,aerospace,high frequency,semiconductor require a perfect elimination of the residue after reflow. There are several options to achieve this result: the use of a no-clean paste which residue can be removed with the most suitable cleaning method or use the paste desiged to be cleaned,as a water soluble solder paste.
The water-soluble solder pastes generally show great wettability because of tehir strong activation but they are also known to have shorter stencil life and to be more sensitive to working conditions as temperature and humidity,compared to the no-clean pastes. Additionaly,with the components stad-off getting smaller and smaller,washing residues with water only is more and more challenging due to its high surface tension; the addition of detergent becomes often necessary.
The purpose of this paper is to highlight the differences between these two families of solder pastes to guide users in their choice. This will be achieved through the comparison of several recent water-soluble and no-clean formulations as far as reliability is concerned. First the printing quality will be evaluated (viscosity,tack,cold slump,printing speed according to pressure,stemcil life,idle time,printing consistency). Then the reflow properties will be compared (hot slump,solderballing,refow process window,wetting ability on different finishes). Finally the residue cleanibility will be assessed. The IPC SIR will be also done to conclude the study. Bth standardized tests and production tests will be used to evaluate the performance on these two kinds of solder pastes.

During the last period of newly assembled electrical devices (pcbs),new component types like LGA and QFN were also qualified as well as smaller passive components with reliability requirements based on the automotive and industrial industry. In the narrow gaps under components,residues can accumulate more by the capillary forces. This is not that much a surface resistance than an interface issue. Also that the flux residues under such types of components creates interaction with the solder resists from the pcb,as well as the component body was not completely described in the standard SIR measurement. On the other hand also,electrical influence with higher voltage creates new terms and conditions,in particular the combination of power and logic in such devices. The standard SIR measurement cannot analyze those combinations. The paper will discuss the requirements for a measurement process,and will give results. The influences of the pcb and component quality will also be discussed. Furthermore it will describe requirements for nc solder paste to increase the chemical/thermical/electrical reliability for whole devices.

Conductive filament formation or CAF typically occurs in two steps: degradation of the resin/glass fiber bond followed by an electrochemical reaction. Bond degradation provides a path along which electro-deposition occurs due to electrochemical reaction. The path results from poor glass treatment,from the hydrolysis of the silane glass finish,or from mechanical stresses. Once a path is formed,an aqueous layer can develop through the adsorption,absorption,and capillary action of moisture at the resin/fiber interface. The path can be modeled as an electrochemical cell,in which the metal conductors are the electrodes,the driving potential for the electrochemistry is the operating potential of the circuit,and the electrolyte is the absorbed moisture.
Microscopic examinations of failure sites have shown that conductive filaments can be formed along debonded or delaminated fiber glass/epoxy resin interfaces due to breaking of the organosilane bonds. The organosilane bonds can be chemically degraded by hydrolysis (adsorption of water at the fiber glass/epoxy resin interface) or by repeated thermal cycling,which induces stresses at the interface due to coefficient of thermal expansion mismatches. This paper discusses the formation of pathways due to the degradation of organosilanes.

The onset of copper barrel cracks is typically induced by the presence of manufacturing defects. In the absence of discernible manufacturing defects,the causes of copper barrel cracks in printed circuit board (PCB) plated through holes is not well understood. Accordingly,there is a need to determine what affects the onset of barrel cracks and then control those causes to mitigate their initiation.
The objective of this research is to conduct a design of experiment (DOE) to determine if there is a relationship between PCB fabrication processes and the prevalence of fine barrel cracks. The test vehicle used will be a 16-layer epoxy-based PCB that has two different sized plated through holes as well as buried vias.
The DOE will include an 8 run experiment with 2 center point runs for a total of 10 runs. This experimental setup is a half fractional factorial with resolution IV. Resolution IV means that main effects,each factor considered individually,are confounded with 3-way interactions. The PCB manufacturing processes selected as factors include laminate cooling rate,plating current density,pulse waveform,and hot air solder leveling (HASL) reflow. A confounded interaction cannot be separated out statistically from its “aliased” main effect. This DOE is a screening design,which is preferred for early investigation since the likelihood that a 3-way interaction would dominate over a main effect is extremely unlikely.
For this DOE,some deviations from an ideal experimentation setup are present. Since each coupon has multiple holes,samples are not uniquely independent. Also,the factors of pulse waveform and current density are not independent. The pulse waveform is also a nominal variable listed as a continuous factor for design purposes and has no center point value.

The electrochemical short,Conductive Anodic Filamentation,that that can develop within a PCB can be difficult to diagnose and detect,and there are many material and process issues that can lead to failure. Since the failure typically has a low incidence rate and typically occurs within multilayer boards identify the route-cause is challenging. NPL is developing a method for determining the sensitivity to various material and process factors that facilitate characterisation of these factors. Here we describe the first phase of the work where we have built a simple structure where we control the various materials and processes in building a PCB. In this simulation vehicle the resin,the glass fibres,the PTH characteristics are investigated,with various reflow processing to stress the structure. After damp heat testing with electrical bias CAF are formed,and since the simulation vehicle is thin it is easy to identify the CAF optically,in addition to the electrical measurements. The presented results will discuss the relative sensitivity to the material conditions and processing parameters within the simulation vehicle. For example the surface condition of glass fibres were found to be critical.

The Advanced Technology Center of the Lockheed Martin Corporation has developed a nanotechnology enabled copper-based electrical interconnect material that can be processed around 200 °C. The readily scalable Cu nanoparticles synthesis process uses a low cost solution-phase chemical reduction approach. A pilot plant is fully operational producing one lb per batch of nanomaterial. We have demonstrated assembly of fully functional LED test boards using a copper-nanoparticle paste with a consistency similar to standard solder. Further improvements have led to the assembly of a small camera board with a 48 pad CMOS sensor QFN chip and a 26 pin throughhole connector. In addition,we have a fully functional nanocopper assembly line in place for process development using standard industrial off-the shelf equipment. We are currently working with a commercial assembly house to dial-in the board assembly process. The fused material shows a tensile strength that is already in the range of space qualified solder. Once fully optimized,the nanocopper-based (trademarked CuantumFuseTM) solder-like material is expected to produce joints and interconnects with up to 10 times the electrical and thermal conductivity compared to tin-based solders currently in use and with a bond strength comparable or better than eutectic SnPb. Applications in space and commercial systems are currently under consideration.

While the density of chip-to-chip and chip-to-package component interconnections increases and their size decreases the ease
of manufacture and the interconnection reliability are being reduced. This paper will introduce the use of embedded fibers in
the interconnections as a means of addressing these issues.
Flip chips bumps are evolving from large solder balls down to small thin copper pillars. Some copper pillars are solder capped and use a thermo-compression reflow attachment process. Smaller diameter copper pillars,while desirable by users,present a significant challenge to assemblers and reliability issues for end-users.
Nanostructures in the form of carbon nano-tubes have been evaluated for years. The recently created a means of growing metallic carbon nano-fibers,CNF's,to micro bumps which are solderable. When embedded with solder the fiber bumps produce robust component interconnections which can be less than 10 um in diameter and up to 20 um high. Attachment of the fiber micro bumps uses conventional thermo-compression bonding.
Results from the most recent evaluations will be presented indicating electrical performance and showing ease of manufacture resulting of such solder coated carbon nano-fiber micro bumps.