In this work we report results of the fracture toughness of a high thermal stability resin system toughened by The Dow Chemical Company proprietary particulate-type toughening material. Results show a significant improvement in the fracture toughness with minimum impact on other thermomechanical properties such as Tg and Td. Because delamination in electrical laminates is a critical failure mechanism observed in such systems,we also investigated the potential synergistic impact of the toughening material (FORTEGRA™ 351) and glass sizing on adhesive properties of the laminate board. Results showed improvements in both shear and tensile strengths of the test vehicles with the addition of the toughener for two different glass finishes. A drilling test showed significant delamination failure for a non-toughened board as observed by a large halo around the drill-hole,and a punch test yielded similar results. Further,it was shown that copper peel strength improved with the addition of the toughener for the two different glass finish types studied. These results are important because they show that use of the toughener and appropriate choice of glass-finish will significantly improve the thermomechanical integrity of high thermal stability test vehicles during downstream part fabrication processes.

Micro Trace Resistor Technology allows thin film resistors to be built within a printed circuit trace that is less than 100 microns wide. Using standard subtractive printed circuit board processes,it is ideal for high density interconnect (HDI) designs where passive component placement is difficult or impossible. By utilizing the differential processes unique to the OhmegaPly® nickel phosphorous (NiP) resistive material,copper traces can be imaged and etched to define resistor widths that are precise and sharply defined,resulting in the creation of miniature resistors with consistent ohmic values. With low inductance and good tolerances,Micro Trace Resistors are ideal for line termination and pull-up/down applications.

•Two primary failure modes from trapped moisture:
•Premature resin decomposition from incomplete resin cross-linking.
•Explosive vaporization during high temperature thermal exposure.

The next generation of smart phones will demand very thin multi-layer boards to reduce the product thickness again. This paper shows three different manufacturing approaches,which can be used for very thin any-layer build-ups. The
technological approaches are compared on reliability level – the any-layer copper filled micro-via technology which is to be
considered as state of the art technology for high end phones and the ALIVH-C/G technology that is well established in Japan. A test vehicle design featuring test coupons for comprehensive reliability test series has been defined as target application for investigation. The applied test vehicle build-ups comprise an 8 layers build-up with total board thickness below 500 µm. The first test vehicle is based on an any-layer HDI build-up including copper filled stacked micro via
structures,the second test vehicle features an 1+6+1 ALIVH-C build-up comprising an outer HDI prepreg layer while the
third test vehicle is built in ALIVH-G technology featuring a full ALIVH build-up.
The influence of the applied manufacturing technology on the reliability performance of thin PCBs is evaluated based on these three test vehicle build-ups. To cover the behavior during SMD component assembly the produced samples are subjected to reflow sensitivity testing applying a lead free reflow profile with a peak temperature of +260ºC. Failure occurrence and the observed failure modes are
evaluated and compared. In parallel a temperature cycling test is conducted on the test vehicles in a temperature range between -40 ºC and +125 ºC in order to evaluate the thermo mechanical reliability of the test vehicles with regard to the manufacturing technology. In order to characterize the reliability aspects influenced by electrochemical migration phenomenon the different samples are subjected to a HAST test at +130 ºC with 85 % humidity level. The results obtained from reliability testing are summarized and compared within this paper. The identified relations between manufacturing technology and the reliability performance of the test vehicles are shown; strengths as well as weaknesses of the applied any-layer technologies are identified and summarized.

Although QFN devices present a challenge to the SMT assembly process with proper stencil design,proper stencil technology selection (Laser,Electroform,Nano-Coat),and proper PCB solder mask layout these challenges can be overcome. The most popular QFN repair seems to be to print solder paste directly onto the QFN leads and ground plane.

Paste release characteristics are driven by the Area Ratio formula,which is based upon conventional stencil foil materials such as a variety of stainless steel alloys,nickel,etc. The surface energy or “phobic” characteristics of these materials are significantly greater than the newer chemistries used to coat stencils and therefore effectively limits the conventional Area Ratio formula in its ability to predict transfer efficiency in ultra-fine pitch devices.

The next generation miniaturised SMT devices waiting to make their mark will require the assembly community to re think their processes and toolsets. The feature sizes that are involved in this new wave of miniaturisation are sub 200 micron,to put this into context,only a decade ago this would have been considered as Semicon domain.
Of all the process involved within the Surface Mount Assembly process the printer is certainly the most sensitive to these changes. But it’s not only about printing miniaturised features – the process engineer has to balance miniaturisation with the requirements of “standard” technology,thus we are experiencing the age of heterogeneous assembly.
Therefore the miniaturisation program is causing the print process to be challenged in new ways especially the impact on the available process window available to achieve high yield heterogeneous assembly
This paper will investigate the impact of miniaturisation and heterogeneous assembly on the print process and strategies to keep one generation ahead.In latest research work,actual paste deposit volumes and transfer efficiency have been monitored and compared for both square and round apertures with area ratio’s ranging from 0.20 thru to 1.35. This covers apertures sizes of between 100 and 550 microns in a nominal 100 micron thick stencil foil. In addition,the effect of ultrasonically activated squeegees (ProActiv) has been assessed as part of the same experiment. A further comparison has also been made between type 4 and type 4.5 solder paste aswell.
The data presented here will help provide guidelines for stencil aperture designs and strategies for ultra-fine pitch components such as 0.3CSP’s.

The structures of electronic components become smaller and smaller. 5 volts or smaller voltage of an electrostatic charge are enough to damage or change the structures in small electronic components. The structures will achieve such small dimensions,so electrostatic charges can cause permanent damages. In the year 2024 the sizes of the electronic components will be less than 10 nm. Electrostatic charges of 0,1 nC and electrostatic fields of 10 V/cm or 1000 V/m will be enough then to damage ESDS permanently. Many companies underestimate this danger.

Copper filling of laser drilled blind micro vias (BMV´s) is now the standard production method for high density interconnects. Copper filled BMV´s are used as solder bump sites for IC packaging where the filling process enables the required interconnect density and provides the surface to ensure reliable solder attachment. For “smart phone” production use of multiple lamination and typically 10 layers of stacked copper BMV filling is now the preferred technology,this is also known as the “any layer” filling process.
Advances in filling processes are required to maintain the development in circuit miniaturization together with the reduction in overall processing costs and to meet the demand for ever more filled BMV´s on each plated layer. The required filling processes must provide void or inclusion free filling,a minimum of surface plated copper along with the capability to allow stacked filled structures.
This paper describes the function and principles behind BMV filling processes together with methods for non destructive testing of the filled structures. Production processes for BMV filling in vertical and horizontal production equipment with both soluble and insoluble anodes are presented together with a discussion of the plating parameters currently used in volume production. A comparison in filling performance of DC plating with that achieved in reverse pulse plating is also made.
The impact of specific processing parameters on volume production systems is discussed and in particular the use of fully automatic process control and the advantages of such systems in achieving uniform and reliable product quality.

Electroless plating processes are popular because of their performance,reliability and cost effectiveness. The process combines unique deposit properties such as uniform plating build up regardless of geometry,excellent corrosion resistance,superior hardness and wear and the ability to plate on non-conducting materials. The most commonly used electroless plating process is Electroless Nickel (EN) plating using nickel phosphorus baths. The phosphorus content plays a fundamental role in all physical properties of the deposit. It is,therefore,critical to control the phosphorus content within a relatively tight range. X-ray fluorescence is an excellent method to not only measure plating thickness but also weight percent elemental composition of coatings. Previously,it was only possible to measure plated phosphorus content on steel substrates. New developments in XRF instrument hardware and software have extended the measurement application of electroless plating processes to nearly any substrate. The simultaneous measurement of thickness and composition is critical.