Though the electronics industry is nearing the 3-year anniversary marking the ban of lead from electronics products,several
challenges still remain with existing lead-free materials for certain applications. The commonly used and accepted SnAgCu
(tin-silver-copper,also known as SAC) alloy has proven to be a suitable material for the production of many devices but,for
those applications that require extremely high reliability,current SAC materials are less than ideal. In particular,devices that
will find end use in automotive and military/aerospace products require a lead-free material that can withstand the higher
temperatures operation life (e.g. automotive under-the-hood conditions),offer vibration resistance not commonly associated
with traditional SAC alloys and deliver high temperature (> 125oC) thermal cycling reliability levels beyond those available
with current commercialized SAC materials.

This paper discusses the results of several independent experiments designed to address the many aspects of successful PoP integration. Assembly through the use of in-line stacking and pre-stacking was evaluated. Top package soldering was
performed by dipping in either flux or paste. The warpage behavior of each level,as well as the full module was characterized through simulated reflow using Shadow-Moiré analysis. Warpage behavior was found to be a limiting factor in assembly yields.
Reliability of PoP assemblies was evaluated using drop/shock,vibration and thermal cycling. The level at which failure occurred depended on the location of the module on the PCB. Underfill was found to greatly enhance mechanical reliability,however thermal cycling reliability was decreased.

For decades the manufacturers of electronic components have furnished products that were most compatible with soldering
processes that employed a eutectic alloy composition that contained tin and lead. In recent years the European Union (EU)
developed the 'Restriction of Hazardous Substances' (RoHS) directive that forced the global electronics industry supply chain
to modify their materials and processes to accommodate lead-free soldering. Component suppliers responded by furnishing
lead-free alloy terminal plating. To accommodate the lead-free components,board suppliers developed a number of lead-free
surface finishes and coatings. The circuit boards base material has required change as well to meet the requirements of higher
temperature lead-free soldering processes needed for assembly.
Although most of the companies supplying finished electronic products to consumers in North America are not required by
legislation to comply with the EU directive,many are being forced to modify their assembly process because some of the alloys plated on the lead-free components and printed circuit boards are not really compatible with lead-bearing solder materials. The other issue is the components and boards originally developed for eutectic soldering can not be used in a leadfree process due primarily to the mold compounds and base materials lack of capability to hold up at the elevated temperatures required for lead-free soldering. In this paper the author will address three key issues a designer will need to consider during the planning phase of a new products development; Component selection for lead-free applications,Product exemption criteria and Specifying compatible PCB material and finish.

The trend towards increasingly complex designs with smaller physical sizes has been translated into ever-increasing pressure on system developers to pack more functions and options into a given area. In addition,cost needs to be driven down as much as possible. As a result,the design process has become more extensive in terms of resources,complexity,choice of PCB technology and cost reduction. In order to handle this challenge effectively,one would like to predict the efforts involved in the layout design a-priori. This capability is now available in the form of “Predictability Calculator”,described below.
The Predictability Calculator is a tool that provides the designer with the necessary trade-off analysis performed at the feasibility stage,given the constraints of the assigned area. It takes advantage of the fact that all designs are done today using CAD systems,hence data analysis is possible given the electrical schematics that is available at an early stage of the PCB layout design. This initial data include the number of components and their type and characteristics that are known once they have been selected. The number of connections is also available based on the interconnections and busses.
Although it is recognized that the PCB technology may be selected independently of the designer,it is nonetheless a part of the tradeoffs supplied by the Predictability Calculator with the objective of providing maximum performance at a minimal cost.
This tool has been utilized so far in the feasibility stage of over 40 complex boards,and also in post mortem analysis of other boards. It has thus demonstrated a proven capability of providing feasibility data for the routing complexity with a high level of confidence. The next step in the tool development will include an in-depth placement feasibility and the trade offs with embedded resistors and capacitors.

As new generations of electronic products emerge they often surpass the capability of existing packaging and interconnection technology and the infrastructure needed to support newer technologies. This movement is occurring at all levels: at the IC,at the IC package,at the module,at the hybrid,the PC board which ties all the systems together. Interconnection density and methodology becomes the measure of successfully managing performance. The gap between printed boards and semiconductor technology (wafer level integration) is greater than one order of magnitude in interconnection density capability,although the development of fine-pitch substrates and assembly technology has
narrowed the gap somewhat. All viable efforts are being used in filling this void utilizing uncased integrated circuits (flip-chip) and incorporating more than one die or more than one part in the assembly process.
This paper provides a comparison of different commonly used technologies including flip-chip,chip-size and wafer level array package methodologies detailed in a new publication,IPC-7094. It considers the effect of bare die or die-size components in an uncased or minimally cased format,the impact on current component characteristics and reviews the appropriate PCB design guidelines to ensure efficient assembly processing. The focus of the IPC document is to provide useful and practical information to those who are considering the adoption of bare die or die size array
components.

Current leakage on a printed circuit board (PCB) can occur due to a reduction in surface insulation resistance (SIR) between adjacent conductors. This is frequently caused by electrochemical migration (ECM),which is the growth of conductive metal filaments,or dendrites,on a PCB through an electrolyte solution under the influence of a DC voltage bias.1 Since the mechanism of ECM involves the electrodissolution and migration of metal,the metallic species present on the PCB surface represent an important factor which can influence ECM time-to-failure. Despite the widespread adoption of tin-silver-copper solder alloys in response to RoHS requirements,there have been relatively few reported assessments of their propensity for ECM in temperature-humidity bias conditions.
This paper presents results of temperature-humidity-bias (THB) testing of over 1500 hours duration at 65°C,88% relative humidity for comparative evaluation of ECM on circuit boards processed with Sn-3.0Ag-0.5Cu solder versus Sn-37Pb solder. In situ monitoring of SIR was performed throughout these tests. In addition to assessing the effects of solder alloy,several other factors were investigated: solder assembly process (wave versus reflow),board finish (organic solderability preservative,or OSP,versus hot air solder leveling,or HASL),spacing (25 mil versus 12.5 mil) and voltage (40V versus 5V bias). Measurements of SIR were combined with observations from optical and electron microscopy to determine the effect of each factor on ECM. Results revealed significant differences in current leakage and metal migration behavior between SAC 305 and eutectic tin-lead assemblies. Furthermore,in some cases,short-term trends in SIR were not maintained over the longer duration of these tests,showing the value of extended test durations for reliability testing of long-life products.

Foresite has investigated many whisker failures and found that consistent high levels of chloride,sulfate and amines are present in and around the areas of whisker formation even in hot dry environments with high stress conditions in the solder joints.

Inkjet printing is of great interest in the field of electronics manufacture because its digital nature negates the need for
physical tooling. A wide variety of active and passive materials are currently being investigated for use in inkjet printed electronics. These include semiconductors,light emitters and photovoltaic materials as well as dielectric materials and straight forward conductors. The range of conducting materials that can be printed is somewhat limited by the constraints of inkjet printing. Ideally,particle sizes should be below 1 micron and the viscosities and surface tensions of the fluids need to be tailored to the particular printhead being used. Regardless of these limitations,various technologies are now being implemented in the production of circuit boards,interconnects and antennas by inkjet printing. The properties of these inkjet printed circuits do not currently mimic traditional PCB materials – in particular,the sheet resistances of inkjet printed materials tend to be significantly higher than traditional copper clad laminate and the minimum feature sizes are somewhat larger than state of the art semi-additive plating. However,inkjet printed circuit technologies are a still finding many
applications which are particularly well suited to their properties and the digital nature of their application.

The cracking and delamination of printed circuit boards (PCB) during exposure to elevated thermal exposure,such as reflow and rework,have always been a concern for the electronics industry. However,with the increasing spread of Pb-free assembly into industries with lower volume and higher complexity,the occurrence of these events is increasing in frequency. Several telecom and enterprise original equipment manufacturers (OEMs) have reported that the robustness of their PCBs is their number one concern during the transition from SnPb to Pb-free product. Cracking and delamination within PCBs can be cohesive or adhesive in nature and can occur within the weave,along the weave,or at the copper/epoxy interface (see Figure 1). The particular role of moisture absorption and other PCB material properties,such as out of plane expansion on this phenomenon is still being debated.

In recent years there has been an increasing emphasis on miniaturization of Board Mount Power (BMP) modules and electronic subassemblies. In addition there has been a shift from predominately through hole to predominately surface mountable modules using FR4 substrates. This trend coupled with the recent transition to Pb-free products has led to questions regarding Moisture Sensitivity Level (MSL) ratings of Power Modules and subassemblies. Attempts to apply J-STD-020 ratings to subassemblies may not be appropriate and has major implications on the packaging and handling of these products. In addition,there continue to be questions and concerns from manufacturers of power products related to MSL ratings of bare PCBs. Failure to properly protect PCBs from moisture induced damage during the fabrication of PCBs and PCB assemblies can lead to costly yield and reliability problems.
IPC-9592 was released in the Fall of 2008. It addresses Quality and Reliability issues related to Power Products. This document highlights the concern with potential reliability risks due to moisture sensitivity of BMP assemblies. Since there are no established industry standards to address this concern,it is left up to the manufacturer and supplier to take appropriate precautions. The PCB is one of the most moisture sensitive components in BMP assemblies. Vulnerability to delamination especially during Pb-free reflow soldering will be one of the main driving forces in determining BMP module MSL ratings. This paper will present results of moisture studies performed on Lineage Power PCBs and Modules. It will also suggest methods that will reduce the vulnerability of the PCB and the PCB assemblies to moisture induced damage.