The reliability of lead-free (LF) solder joints in surface-mounted device components (SMD) has been investigated after thermo-cycle testing. Kirkendall voids have been observed at the interface component/solder together with the formation of fractures. The evolution,the morphology and the elemental analysis of the intermetallic layer have been evaluated before and after the thermal treatment. Voids produced by the release of volatile species during the soldering process due to the application of flux were present. If compared with SnPb soldered systems,lead-free joints are characterized by larger and a higher amount of voids. In several electronic joints (ball grid arrays (BGA),surface-mounted device components (SMD),etc.) fractures developed after the thermal stresses generated during the accelerated thermal aging. Warpage of the PCB has also been observed. Backward and forward compatibility of SnPb and lead-free BGA connections has been performed on pads with an ENIG finish. The effect of the reflow peak temperature on the structure of the intermetallic layer has been assessed.

The High Density Packaging Users Group (HDPUG) consortia completed an extensive study of 29 different bare board material and stackup combinations and their associated performance after 6X Pb-free reflow at 260C. Data presented will focus on the air-air thermal cycling,IST testing and material survivability after Pb-free assembly reflow portions of this testing. Test board design aspects,manufacturing processes,Weibull analysis,and failure analysis data will be presented. The impact of plated through hole pitch on laminate integrity and how material properties relate to the results will be discussed.

The signal channels that link high speed processors to memory and various other peripherals,are limited by the inherent characteristics of the printed circuit board. These are what ultimately connect information to the outside world. One limiting factor is the effect of non-uniformity of the glass fiber distribution in the printed circuit substrate material,also known as fiber weave effect (FWE). FWE introduces signal skew and timing errors which place an upper limit on bit rate and trace length.
Using unique fabrication techniques and a proprietary low dielectric constant glass composition,a revolutionary glass fabric is presented that is essentially free of fiber weave effect while demonstrating inherently improved resistance to conductive
anodic filament (CAF) formation. Improved laminate performance is demonstrated with finite element modeling and HyperLynx simulations,and corroborated with dielectric property measurements on prototype substrates.
A printed circuit board using this material demonstrates superior signal integrity performance over the traditional glass-based
solution. By uniformly distributing glass fibers the maximum surface area becomes available to bond with the resin,which is
enhanced by direct application of a finish to provide a high quality interface between glass and resin. Two high profile performance issues,fiber weave effect and CAF,are addressed by a unique laminate reinforcement.

Over the years,signal integrity performance and bandwidth gets more critical for today’s higher signal transmission speeds and bandwidth demand in every field of applications such as computing,multimedia,communication infrastructure and a variety of communication bus and cable like PCI express,SATA II and AGP bus for computer system. Base material electrical performance especially for dielectric loss will dominate signal communication behavior while communication speeds push up to 5~10Gbps.
Because one labors under the hypothesis of lead-free process compatibility,high Tg demand and thermal reliability concerns,the base resin system candidates for print circuit boards is limited. Basically,bisphenol-A novolac construction resin has been the mainstream resin in the market for years. Unfortunately,its characteristic restricts its dielectric loss performance . How can one further improve dielectric loss and signal integrity performance? Besides post-remedial measures in manufacturing technology like oxide treatment roughness,laminate construction,resin content,fabric weaving density,etc.,CCL resin system reactivity and the choice of catalyst system are two significant factors for electrical performance improvement beside the resin and hardener design. Our study shows that a resin system reactivity with and without optimization can make a difference of up to 20% gap in signal integrity performance.

Copper Wrap Plate as specified in IPC 6012B table 3-2,is a requirement developed to enhance reliability for PCB’s designed with via structures that require planarization and surface capping. PCB’s built without wrap plating are more prone to failures associated with separation between the interconnection of the barrel copper to the surface copper. The improvement in reliability is a function of the copper wrap thickness,which supports the difference in IPC requirements for Class II and Class III programs. The general rule is “the thicker the wrap plating the better the reliability.” The increase in copper thickness,associated with wrap plating,however competes with the ability for PCB fabricators to manufacture products with high density and fine features. The general rule for manufacturing fine features is “the thinner the copper the better the manufacturability.”
The technology developed by DDI Corp. called FLAT-WRAP™ offers a copper wrap solution that does not require build-up of copper on the external surface of a filled plated hole. This allows the improvement in reliability without sacrificing the ability to manufacture designs with high density and/or fine features. This technology also facilitates,in process non-destructive copper thickness measurements and ensures consistency of copper wrap thickness across the entire board surface. In this technology,the external surface copper thickness of filled plated holes will control the copper wrap thickness. In Printed Circuit Board designs requiring multiple copper wraps,the benefits of this technology are even more evident.
This article examines the current process problems with copper wrap plate and discusses the benefits provided by the new technology with respect to manufacturing and reliability.

Many BGA and CSP component suppliers have begun shipment of components with a variety of “second generation” Pb-free solder ball alloys. Much of the motivation for the alloy changes has been to improve mechanical shock resistance. Several publications have established the improved performance of such 2nd level BGA/CSP sphere alloys; however,much less has been published regarding the thermal fatigue resistance of components with these new Pb-free ball alloys. As these components and alloys become mainstream,their use in situations where thermal fatigue resistance is critical to product life will become an important consideration. Therefore,an understanding of thermal fatigue performance for new alloys is necessary for OEM/ EMS/ ODM companies to make design and procurement decisions,and for component suppliers to
ensure the reliability of their products under a range of field use conditions.
In this study,the thermal fatigue performance under accelerated test conditions is compared for three common BGA ball alloys: SAC105,Sn-3.5Ag,and SAC305 as a control. Accelerated thermal cycle (ATC) testing was performed using 676 PBGA components with 1.0 mm pitch and electrolytic Ni/Au finished component pads. These components were assembled to high-temperature rated Cu-OSP coated printed circuit boards using SAC 305 solder paste,which represents one of the most common assembly practices in industry today. ATC testing was performed using the IPC-9701A TC1 condition of 0/100°C with 10-minute dwells (nominal); 3 different failure criteria were used in constructing the Weibull failure curves. The data indicate that SAC105 has the lowest thermal fatigue resistance among the alloys tested,with Sn-3.5Ag and SAC 305 having similar and superior performance. The impact of failure criterion on the Weibull curves is also presented. The
implications of these findings and areas for further study are discussed.

Although the EU RoHS legislation restricts the use of lead in electronics equipment,many high-end multi layer server printed circuit board assemblies (PCBAs) continue to be built with lead under the server equipment exemption. As the industry prepares to comply with the RoHS directive without the use of exemptions,several studies and research efforts continue to focus on expanding the lead free assembly process capabilities for these types of high density,thick PCBAs. In this space,a different approach is required to mitigate the often encountered technical challenges of a lead free process such as solder hole fill on PTH barrels,copper dissolution effects and reflow thermal profiling.
The additional thermal mass on thick heavy assemblies’ further narrows the process windows to achieve the temperature
profiles required. On these assemblies the printed circuit board thickness can often extend to over 0.130 inches with layer counts in excess of often 18 or more,comprising of 1 ounce and 2 ounce copper planes. These circuit board stack ups introduce an increased level of PTH solder hole fill difficulty which cannot be addressed by normal process optimization techniques. Furthermore during SMT reflow,the additional thermal mass from the PCB and number of large BGA devices generally increase the overall heat required in producing an optimized reflow profile condition to meet the solder joint attributes,while at the same time be constrained by the thermally sensitive components. These challenges requires new
approaches to achieve optimization which will need to be considered at the conceptual stage of board lay out and component selection.
This paper examines the effects of varying surface finishes,temperature sensitive component limitations,process parameters
and the resulting interactions that affect the solder attach attributes. The study includes characterization of solder joint
attributes from a time zero perspective and extends to accelerated temperature cycling with post stress characterization. Additionally,the intent of this work is to document the need to identify design and process options for applications where density and PCBA functions extends beyond the commercially developed lead free solutions.

Some Ball Grid Array suppliers are migrating their sphere alloys from SAC305 (3% Ag) or 405 (4% Ag) to alloys with lower silver contents. There are a numerous perceived benefits to this move in terms of cost and performance,but process compatibility and reliability concerns have yet to be addressed.
Process compatibility concerns stem from the fact that the low-silver SAC replacement alloys have higher melting temperatures than SAC305,approximately 227°C as compared to 221°C. Certain families of electronic assemblies,such as consumer portables,are often heat-sensitive and are reflowed in the low end of the established lead-free peak temperature range,typically 230-235°C. The small temperature difference between the spheres’ melting temperature and the peak reflow temperature raises questions about the reliability of the solder joints that are formed under this tight thermal margin. These are similar to the concerns raised with the backward compatibility of SAC305/405 spheres with tin-lead solder processes. Some of the solutions identified in the lead-free ball/tin-lead paste scenario may apply to the low-silver ball/SAC305 paste combination,but they require review for their applicability with this new set of mixed metals.
A study has been undertaken to characterize the influence of alloy type and reflow parameters on low-silver SAC spheres assembled with backward compatible pastes and profiles. The DOE combines low-silver sphere materials with tin-lead and lead-free solders at different combinations of peak temperature and times above liquidus. Solder joint formation and reliability are assessed to provide a basis for developing practical reflow processing guidelines.

Portable Electronics devices are having more functionality but the size is getting smaller. What it means to SMT is to place more,smaller and ultra fine pitch devices on PC board. This makes SMT process capability the key measure to SMT quality. A number of the companies study the process capability at the time they evaluate or purchase the equipment,or at the time they design the product to fit the process capability. But process capability is changing over time. The process/machine was capable before may not be capable now. The paper focuses on process capability and process control. It suggests process capability study should be a routine rather than a one time work. The paper is based on the practices in our company’s manufacturing environment. For placement,the Cpk measurement was trialed on some of our lines. The measurement machine problem was analyzed and a proper measurement machine that fits the requirement was chosen. The Cpk result and product yield after proper calibration were very encouraging. For printing,a DOE was conducted based on the 0.4mm pitch BGA. The significant factors related to output of paste volume and paste deposit variation were found and an optimum setting combination was suggested to production. The process characterization has been proved to have a significant financial impact.

The European Union list of Substances of Very High Concern (SVHCs) published in the Registration,Evaluation,Authorization and Restriction of Chemicals (REACH) regulation,requires producers of Articles to provide a declaration regarding the presence of SVHCs to their customers within 45 days of request. To effectively communicate regulatory compliance,organizations require infrastructure and application development to incorporate 1752 and 9535 template standards.
Concurrently,a “green” movement is transitioning product design focus beyond regulatory and legislative compliance to
market-driven,eco-friendly electronics. This is causing many supply chain partners to be pulled in the direction of green leaders with a serious impact on organizations dependent upon the same sources of supply,design standards,and supply chain constituents.
This session will review today’s global manufacturing direction to eco-friendly products and its impact on electronic components and systems. It will explore compliance pressures and other very real concerns such as counterfeit parts,high reliability design,pursuit of Pb-free alternatives,supply volatility,and obsolescence. From component manufacturer and OEM/EMS perspectives,it will also discuss PCN/EOL,data transfer,and published standards that are de facto communication methods but vary significantly in practice. Given complex BOM configurations and the nature of specialized,outsourced supply chains this presents a greater threat to lifecycle performance. A framework will outline preparatory product lifecycle actions and leading approaches taken to address the Green product development movement.
This Executive Briefing discusses the results of two benchmark studies conducted in 2008 by Supply & Demand Chain Executive,in conjunction with IHS,“Benchmarking Green Supply Chain Priorities” and “Benchmarking Product Lifecycles for Green Performance.” Research of more than 300 companies demonstrates that Green is a disruptive market transition that has introduced supply chain volatility and unbalance without any apparent near term resolution.
This paper previews the most serious issues that impact supply chain stakeholders. Along with more comprehensive companion papers,it may serve as a guidebook to plan,prioritize and execute programs. Its central objective is to inform business leaders of both,direct and indirect,influences of Green marketplace behavior,and equip their organizations with strategies to maintain competitive performance,mitigate business risks,and ensure supply chain continuity.
It is a misconception that Green applies only to makers of eco-friendly products or those required to comply with regulations
like RoHS,REACH and EuP.* Although industries like aerospace and defense or communications may seem once-removed from the issues,they cannot ignore the supply chain changes that Green imposes,and they are arguably at greater risk to its influences.
The bottom line: Green is a mainstream marketplace shift,the influence of which ultimately impacts and changes supply and
demand dynamics. Regardless of regulatory compliance requirements,environmental product ambitions,or even short-term
competitive gains,those who chose to ignore its impact may face dire consequences and run the risk of being left behind.