Printed Circuit Boards (PCB) and IC Substrates are the essential building blocks of electronics. As the technology moves rapidly into the future,the electronics industry faces issues with hot spots,solder joint stresses and Co-efficient of Thermal Expansion (CTE) mismatch in a PCB and IC substrates. The most popular material used in the PCB industry is glass fiber based composite material. It delivers great electrical properties but has minimal thermal and mechanical properties. As more functionality is required from a single device,the PCB is getting denser and has a very high heat load per unit area. Also,the speed of the electronics is becoming more critical. This means it is necessary to have the shortest electrical path between silicon and the PCB. This requires eliminating long wire bonds and moving to the Flip Chip types of packages. Flip chip type packages have more functionality and faster speed but also have very low CTE compare to traditional PCB material. Thus it is necessary to have a low CTE printed circuit board in order to keep solder joints intact with such low CTE packages. There are currently several materials available in the market to address thermal and CTE challenges but each material has its own
advantages and limitations. For example,heavy copper is often used for thermal management with a thermal conductivity up to 385 W/m.K. But it has a higher CTE (17 to 20 ppm/C) and high density (8.9 g/cc) and is not easy to drill for the smaller holes required for HDI PCBs. Thus,heavy copper has the ability to do thermal management at the sacrifice of weight,CTE and limited to non-HDI technologies. On other hand,CIC has ability to deliver lower CTE but again CIC is very heavy and hard to drill for smaller vias. Other material non woven Aramid can deliver low CTE but does not have good thermal conductivity. It also has a very high Z-axis expansion and is sensitive to the moisture absorption. Thus all above materials can address one issue but are limited in other areas.
The ideal solution for the challenges would be a material that has the ability to do thermal management,CTE control
and provide increase rigidity with no additional weight. Thus,it is necessary to think outside the box and find a material that can address multiple issues at once. If you look at carbon fiber,it has very unique thermal and mechanical (CTE and Stiffness) properties but it is not a dielectric fiber unlike glass fiber. If we manage to use carbon fiber along with the glass fiber,we can address electrical,thermal and mechanical aspect of the functionality required by the industry. This presentation will address: (1) Details of the carbon fiber,(2) Carbon fiber composite types and shapes necessary for the PCB and Substrate,(3) How to make the electrical conductivity of the carbon fiber a plus point as opposed to a hurdle,(4) What needs to be done to use it successfully,(5) How it can address thermal and CTE challenges,(6) Basic understanding of manufacturability: (6a) Compatibility with FR4,Polyimide and other materials,(6b) Effect of feature sizes,scaling,drilling,routing and (6c) DFM through CAM. If carbon fiber could be used as reinforcement material instead of glass fiber (only in few layers) it could bring following benefits to the circuit board:
•?Enable efficient conduction cooling
•?Create a thermal path from hot IC Chips to the frame or chassis
•?Allow the PCB to act as Heat Spreader and/or Heat sink
•?Control the CTE of a PCB to match with Components such as Ceramic BGA (CBGA),Ceramic Column Grid
Array (CCGA),Flip Chip (FC),and Chip on Board (COB) etc.
•?Deliver additional stiffness
•?Give a higher stiffness to weight ratio increasing shock and vibration reliability
•?Provide a thermal management material that does not add weight to the product

The increasing use of lead-free solder has introduced a new set of process parameters when setting up wave solder equipment for effective soldering. Determining the proper flow characteristics of the solder wave for adequate hole fill is an essential step in achieving a reliable process. A variety of solder waves exist in the industry; each with advantages and disadvantages when performing lead-free wave soldering. One way to ensure adequate hole-fill is by increasing contact time at the Chip Wave.
This paper will present recent work done on an innovative way of increasing contact time,hence improving hole fill for relatively challenging board design. This work also examines effect of various process parameters including effect of nitrogen on hole fill. In addition to the experimental work,comparison and discussion of many variations of solder waves including: “A” type waves,laminar waves,dual waves,inerted shrouds,tunnels,and non-inerted waves will be discussed in this paper. Information will be provided on improved utilization of old wave solder equipment and the correct selections of new equipment to optimize lead-free wave soldering.

Copper erosion from plated through holes (PTH) barrels in printed circuit boards (PCB) during both wave soldering and mini-pot rework can increase the risk of PTH reliability failures during field use. Alternative Alloys are being touted as one solution to reducing copper erosion. This study will compare the copper erosion resulting from use of one alternative alloy in wave soldering and mini-pot rework with the currently used SAC305 solder alloy. The PTH knee thickness will be measured on as-received boards,after wave soldering and after one 45 second cycle of mini-pot rework,and compared with the minimum PTH thickness necessary to meet product reliability requirements. The board test vehicle for this study has a thickness of 93 mils (2.362 mm) and its design is similar to a mid-size server board. The SnCuNiGe alternative alloy was chosen from the results of the previous investigation that compared 5 different alloys for the magnitude and variation in copper erosion from PTH knees when subjected to a mini-pot rework cycle,without prior wave soldering [1]. While the mean value of the copper erosion data sets from all 5
alloys did not show any technically significant difference,a particular alloy exhibited significantly lower variation in copper erosion data at the PTH knees. A comparison of this alloy with the SAC305 alloy for PTH knee copper erosion under actual wave solder and mini-pot rework process conditions was required.

Recent industry trends have focused around alternatives for the commonly used SAC305 or SAC405 alloys for wave soldering and solder fountain rework processes. Industry consortia are currently focusing efforts on researching other “alternative Pb-free alloys” which are available on the market today [1]. Financial and technical reasons are driving many process engineers to consider an alloy change. The financial motivation is based on the increasing costs of the high silver content SAC alloys. With the constant pressure of having to reduce manufacturing costs,an opportunity to switch to a lower cost alloy for wave soldering would be a welcomed change. The cost of some of the alternative Pb-free alloys can be as little as half that of SAC – an attractive option. The technical reason for moving away from using SAC alloys for wave soldering and solder fountain processes may be even more significant. The high copper (Cu) dissolution rates which result from using SAC305/405 alloys for solder fountain rework have been documented as a major concern for the electronics industry [2,3]. The SAC305/405 Cu dissolution rates are so high that there is barely enough time to perform a 1X rework and in most cases do not allow enough contact time to perform a 2X solder fountain rework without experiencing irreparable damage to the PCB. This process limitation is a concern,especially for high reliability,long life products which may require multiple reworks during their lifetime. This technical issue in turn creates further financial impact through increased product scrap. To help address this technical issue,the evaluation of alternative Pb-free alloys continues. Previous work on some of these alternative Pb-free alloys has shown the benefits of having Cu dissolution rates similar to that of the 63Sn-37Pb alloy [4].
The financial and technical reasons for making a change away from using SAC305 or SAC405 alloys at wave solder and solder fountain are indeed compelling. However,before making a change to an alternative Pb-free alloy,a number of questions need to be answered,such as,what alternative Pb-free alloy/s should be considered? Which alternative Pb-free alloy/s offers the best process yield? Which offer the best thermal and mechanical reliability? As these alternative Pb-free alloys are relatively new to the electronics industry and therefore data limited,further study of their reliability performance is essential. A number of comprehensive investigations studying the reliability of PTH structures assembled with SAC and select alternative Pb-free wave alloys have been published to date [1,5-8].
This paper,an evolution of earlier work on this topic,discusses results obtained from an internally designed PTH test vehicle constructed to evaluate three commercially available alternative Pb-free wave alloys (Sn-Cu-Ni,Sn-Ag-Cu-Bi and Sn-Cu-X) by comparing their performance to SAC405 and SnPb. The process performance of each alloy is discussed,including profile optimization and process yield analysis. Failure analyses are presented to identify and explain observed failure mechanisms. In addition,the thermal and mechanical reliability analysis of each alloy is discussed. The objective of this work is to select a suitable wave alloy replacement to SAC305/405 that provides similar if not better overall solder joint quality as well as thermal and mechanical reliability.

As designers strive to extract ever more performance from high speed transmission lines on FR4 substrates and their high speed derivatives,a requirement has arisen for a practical and robust “Go / No Go” test technique for loss to be deployed on the PCB production floor. The intent of this paper is to propose that RIE (Root Impulse Energy) testing is a practical and achievable test method. It is easily deployed and offers repeatable,reliable discrimination between PCBs fabricated with a range of varying base material loss characteristics.
Until recently digital signals on PCB transmission lines operated at sub gigabit data rates. Consequently,losses were safely ignored while characteristic impedance was the major transmission factor. Today loss is a major consideration when pushing the limits of transmission lines on PCB boards. A board may be designed to take advantage of the transmission capabilities of a high specification dielectric,but an inadvertent substitution of an inferior specification core or prepreg during the manufacturing cycle,which may easily go unnoticed,could be fatal to the electrical performance of the system.
This test is designed to give fabricators a first indication of a change in loss characteristic on a given transmission line structure / layer stackup. This change in characteristic loss may be due to a number of factors including incorrect material used in a stackup. It may also be used in conjunction with other techniques (more suited to lab / QA use) to flag the need to escalate problem builds for more detailed laboratory analysis.
The RIE method has been presented in previous papers and presentations [1]. This paper looks at some of the more practical implementations of deploying this method in a conventional production environment. TDRs from two manufacturers were used for the acquisition of results in this paper.

More and more circuit board designs require signals paths that can handle multi-gigahertz frequencies. The challenges for organic circuit boards,in meeting these electrical requirements,include using high-speed,low-loss materials,manufacturing precise structures and making a reliable finished product. A new circuit board HDI technology,using Z-interconnect,is presented that addresses these challenges. The Z-interconnect technology involves building mini-circuit boards of 3 or 4 layers each,then assembling several thin circuit boards together to make the finished product. Designing and manufacturing the thin circuit boards separately,then assembling them together,makes it possible to reliably manufacture circuit boards with no via stubs,very low-loss materials,nearly arbitrary transmission line structures and a lot of flexibility in tuning features to reduce signal loss. In the present paper,we have designed and built a circuit board test vehicle (TV) to make new RF structures,using Z-axis interconnection (Z-interconnect) building blocks. A typical 50-ohm stripline was designed with a
ground-signal-ground structure. The stack-up had 23 metal layers,including 5 0S1P joining cores and 6 2S1P signals cores. Teflon-based Taconic materials TPG30 and TLG30 were used for the dielectric layers. Laminated conducting joints show low resistance in the range of 1 milliohm for a 0.3mm diameter,250um length joint. Electrically,S-parameter measurements showed very low loss at multi-gigahertz frequencies. The losses were low enough to support typical SERDES links up to 15 Gbps over 30” net length. This effort is an integrated approach on three fronts: materials development and characterization,fabrication,and design and electrical characterization at the board level.

Typical PCB materials have inherent properties (the “Fiberweave Effect”) which can be detrimental to the Signal Integrity of the physical link. This presentation describes the effect and a means to mitigate for it (image rotation). The possible effects on PCB fabrication and manufacturing include: dimensional; SMT solder joint; mechanical properties (elastic modulus,warpage,and CTE); and impact to Solder Joint Reliability. A study of those effects is summarized and presented. INTRODUCTION Image Rotation was outlined as a mitigation technique for the Fiberweave problem in an earlier Intel White Paper [5]. This paper represents follow-on efforts to analyze the viability of that strategy for High Volume Manufacturing. The intent was to answer the following questions regarding Image Rotation:
1) Are features distorted? E.G..,are trace widths affected?
2) Are features’ locations distorted?
3) Are Surface Mount Technology (SMT) structures (solder joints) negatively affected?
4) How are PCB mechanical properties (elasticity,warpage) affected?

Failure analysis was performed on fourteen thermally cycled or vibration tested PDIP components from the JCAA-JG-PP Lead-Free Joint Test Project. The components differed in component finish,solder alloy used for assembly,test vehicle/circuit board type,rework (yes or no),and rework alloy (if relevant). Components were either vibration or thermally tested. A qualitative comparison was made between the extent of damage visible using 3D digital microscope images of the solder joint surfaces and the damage seen in optical microscopy cross-sectioned joints. It was found that use of a digital microscope,in conjunction with resistance measurements,made the decision of which joints to cross-section easier. However,it was not found that the digital microscope can be used exclusively,without cross-sectioning samples,to reveal the important damage features on stressed solder joints.

As the use of area array connectors has become more widespread in electronic assemblies,the need to evaluate their reliability has increased. There is,however,limited information on how best to perform accelerated thermal cycle testing of area array connectors. Though specifications such as IPC-9701A can serve as useful guidelines in assessing second level reliability of these components,area array connector test vehicles are more complicated than test vehicles designed for testing traditional area array packages,as they require the use of daughter cards to allow the daisy chain to be completed and to properly emulate a real-world implementation of the connectors. While IPC-9701A can provide useful guidance in designing the motherboard,it offers no insight on the design of the daughter card,nor does it provide assistance in determining which version of a connector to test in cases where there are several variations within a connector product family. As accelerated thermal cycling tests can be expensive and time consuming,there is a need to assess the impact of these variables on the reliability of a connector to provide guidance in choosing the best way to test,and to assist in understanding how changes in the design between the test vehicle and the final product design may be expected to change the reliability. The “Metro2” test vehicle was used to help generate data on these issues. In addition to providing manufacturability and reliability data on a selection of lead free area array connectors,three variations on one of the mezzanine connectors were studied to help assess the impact of design variables. The first comparison focused on the impact of changing the daughter card thickness from 0.062” to 0.093”. Previous work on a tin/lead version of this connector indicated that the flexure of the 0.062” thick daughter card during thermal cycling played a role in the location of the solder joint failures observed,and as a result,it is expected that the increase in thickness may change the location of the failures and could also affect the reliability of the connector. The second comparison focused on the stack height of the connector. A 4mm stack height version of the connector was compared with a 6mm stack height version. The results of accelerated thermal cycling will be presented for the variations of this mezzanine connector along with the failure analysis results. Results will also be compared to those obtained on the tin/lead version of the same connector.

Solder joints tend to crack after extended thermal cycling,if the component and the circuit board are CTE mis-matched. Predicting t-cycle lifetime is a crucial first step in optimizing product design and/or in-service conditions. Predictor models embody cyclic fatigue physics and math,and require inputs of the materials and geometry of the hardware as well as the thermal conditions of the environment. The output is the predicted number of t-cycles to fail (i.e. to develop electrical-open cracks thru the solder-fillet). Several predictor models are in use within the industry. This paper describes a comparison among several predictor models,rating them for ease of use,and for accuracy against known actual test results and against each other. The study uses a round-robin approach; wherein each participant was given the same input data for ten different components,but the actuals were withheld until the respective predictor results were in. Also,this paper describes a related study on the ability of each model to perform parametric analyses: i.e. to define the effect of variations in hardware and environmental conditions on t-cycle life. The results offer guidance on t-cycle life prediction,as well as on improving t-cycle life