The handheld wireless product market place demands products that are small,thin,low-cost and lightweight and improved user interfaces. In addition,the convergence of handheld wireless phones with palmtop computers and Internet appliances is accelerating the need for functional circuits designed with smallest,low-cost technologies.
The miniaturization of portable electronics and Mobile handsets is resulting in thin form factor cell phones,camera modules and Bluetooth packages. The consumer appeal for sleek phones is driving the need for thin PWB roadmaps for the handset. [1]
Qualification of thin PWBs (less than 0.8mm) require careful evaluation of PWB stackup for warpage,delamination and successful lead free reflow and rework. The paper presents the qualification testing of thin PWBs for warpage characteristics. X-sectional analysis,shear testing,thermal shock,temp. Humidity testing and drop test for long-term reliability.

The conversion to lead free Ball Grid Array (BGA) packages has raised several new assembly and reliability issues. One reliability concern becoming more prevalent is the increased propensity for pad cratering on Printed Circuit Boards (PCBs) [1,2].
Lead-free solder joints are stiffer than tin-lead solder joints,and lead-free compatible (Phenolic-cured) PCB dielectric materials are more brittle than the FR4 (dicy-cured) PCB materials typically used for eutectic assembly processes. These two factors,coupled with the higher peak reflow temperatures used for lead-free assemblies,could transfer more strain to the PCB dielectric structure,causing a cohesive failure underneath the BGA corner pads.
The likelihood of pad cratering occurring in any given assembly depends on several factors including,but not limited to,the BGA package size,construction and surface finish; and the PCB pad size,material and surface finish. Standard assembly level bend,shock and drop tests can be used to determine if the entire assembly can survive a given strain and strain-rate range without having any failures.
However,with these standard assembly-level tests,it is difficult to determine if the failures occurred due to an unusually weak PCB dielectric/PCB pad size or a stiffer BGA package. It is critical to have a standardized test method that can be used to characterize and rank-order different PCB dielectric materials and PCB pad sizes.
In this study,an easy-to-implement test method to quantify the propensity for pad cratering in different PCB materials is presented. Gage repeatability and reproducibility studies to fully develop the test method were performed. Several different design variables,such as PCB material,resin content,solder alloy,number of reflows,pad size and shape were studied with a range of material sets. The test method was refined to develop a comparative metric that can be used to rank-order different PCB materials and pad size combinations.

For many critical electronic applications,there is a need for dielectric systems that exhibit better electrical insulation
performance than epoxies and other conventional materials. In the production of advanced telecommunications,high-speed
electronic and microwave equipment as well as radomes and other products being developed today throughout the world,
manufacturers rely on materials such as Teflon®,cyanate esters,and cyanate ester/epoxy blends to meet their performance
requirements. However,these materials feature disadvantages that can make them costly and difficult to use as dielectrics in some of these demanding applications.
We have an active research program to develop novel new thermosetting polymers with low Dk/Df properties. This paper
focuses on the testing of one of these materials as a base resin for PWB multilayers. This new system may also have applications outside the scope of this study.

Two major trends in printed wiring boards electronics are applications that require higher operating frequency,often in the radio frequency range (GHz),and the use of lead free solder assembly. Material requirements for dielectric materials have become more stringent. Key characteristics for dielectric materials are low dielectric constant,low dielectric loss,high use temperature,and low moisture uptake. The use of engineering thermoplastics has been investigated as a means to enhance performance of thermoset resins. In particular,polyphenylene ether (PPE) exhibits excellent hydrolytic stability,low moisture absorption,extremely high glass transition temperature,outstanding electrical properties over a wide temperature and frequency range,and ease of flame retarding without the use of halogenated materials. Investigations on the use of engineering thermoplastics in thermoset resins have pointed out the complexities of the network molecular architecture. Indeed,a wide variety of network morphologies were obtained within the fully cured material. PPE telechelic macromers have been reported as a breakthrough in the search for materials that broadly enhanced performance of dielectric materials. Thus the use of PPE macromonomers as a co-reactant in epoxy resins resulted in extensive performance advantages. Indeed,the use of PPE macromoners in epoxy resins resulted in single-phase networks,exhibited an increase in glass transition temperatures (Tg),lower dielectric properties,lower moisture absorption,and increased toughness. Single-phase matrices were also obtained with cyanate esters that exhibited lower moisture absorption and increased toughness. Vinyl modified PPE macromers were used in resins cured via radical polymerization. These resins exhibited very low moisture absorption in addition to high Tg and very low dielectric properties. The advantages of PPE macromoners in enhancing key properties of various dielectric materials suggest utility in a variety of demanding electronic packaging applications.

The use of flexible circuit boards in the design and manufacture of electronic products has experienced a consistent and rapid growth over the last 15 years because their light weight and physical flexibility make it possible to combine electronics,packaging design,and styling to create exciting new consumer products. And as the capacity and pin density of electronic components has continued to increase,new demands are being created for flexible circuit boards. These new demands include the need for thinner copper on thinner flexible substrates with greater bending flexibility and durability.
The most common commercialized process today for the deposition of ultra-thin copper on flexible base materials is a vacuum sputtering process. In this process,there is a sputtered tie coat of chromium or other metals or alloys to improve the adhesion to the base,followed by sputtering of a thin layer,usually about 0.2 micron,of copper. Quite often the substrate is pre-treated with plasma to improve tie coat adhesion to the base material. This is often followed by the electro-deposition of copper to the desired final copper thickness. These products have been successful in the adhesiveless-copper-on-flexible substrate marketplace. However,the process is expensive because of the need for high capital cost vacuum deposition equipment,is energy intensive,requires the use of toxic metals,requires many processing steps,and is inherently single sided. In addition,the process requires additional processing steps beyond normal etching processes for the removal of the tie coat.
We are commercializing an innovative approach for metalizing flexible substrates. This new approach,which was developed
in the labs of SRI International (formerly Stanford Research Institute) is a non-vacuum process that eliminates the need for
expensive vacuum deposition,eliminates plasma treatment of base material,eliminates several expensive process steps normally associated with conventional copper coating techniques,and produces superior adhesion without the need for a tie coat. All of the process steps can be single or double sided,and have been implemented with a roll-to-roll manufacturing process. Flexible circuit materials made with this process can be used in most types of flexible circuit board manufacturing processes including subtractive and semi-additive methods. The copper deposited is ductile,and has good thickness tolerance. We have achieved outstanding adhesion to the base material along with good surface insulation resistance (SIR) and other pertinent properties. The process that has been implemented can produce coated copper with a thickness ranging from 0.1 micron to 18.0 micron. A variety of base materials have been studied with good results. These include polyimide,particle filled polyimide,liquid crystal polymers (LCP),polyesters,and composites. And the total process is inherently “greener” than existing materials and methods because of the elimination of most (99.95%) or all of the etched materials used in conventional subtractive and semi-additive processes today.

Embedded passives technology offers high-density high-performance solutions,but needs characterization before becoming a resource in harsh-environment applications. This paper discusses two critical factors: a) uniformity as-received from the fabricator,and b) long-term stability under extreme environmental conditions. PWB test specimens spanned a range of embedded resistors and embedded (distributed and discrete) capacitors,from several suppliers,using a variety of materials and processes.
Data as-received includes: Comparisons between target vs. measured values; board–to-board uniformity,uniformity of various spots on the same PWB; comparison edge-to-edge of the same board; and comparisons between coupon vs. PWB,Environmental stability data includes: values as a function of temperature; after long-term storage at elevated humidity and temperature; after vibration,long-term thermal-cycling,water immersion,
molten-solder-dip thermal-shock; and stability after surface over-heating.
As-received uniformity data reveals differences up to 20-40%) between the target value and the actual value,as well as among nominally equivalent features,and between coupon and board. Differences depend on type of element. This is before any cherry-picking or screening by the supplier. Tight fab process control will be necessary. Environmental stability is reassuringly robust. Most exposures cause relatively little change. Stability depends on materials,processes and geometries.
This information could help enable tolerances and yield expectations; develop QC sampling and acceptances protocols; and help designers’ qualification and performance expectations,under adverse in-service conditions.

Nickel plating is often used on PWBs to increase wear resistance and to prevent diffusion between copper and other plated metals. The nickel plating is often present in through holes as well as on the surface,such as when the entire PWB panel is nickel/gold plated or when press fit pins are used for assembly. When the plated through holes are evaluated by micro sectioning,it often becomes apparent that the nickel plating is not uniform. It tends to be much thinner in the middle of the hole than on the surface of the board,and may not meet minimum thickness requirements. This paper will evaluate the effect of various plating parameters and chemical additives on through hole plating uniformity. Data will be presented comparing direct current and pulse plating. This paper will also evaluate how the addition of chemical additives to increase throwing power affects the intrinsic stress and grain structure of the nickel. Tests include plating PWBs having through holes of varying diameters and aspect ratios with nickel in thicknesses up to 100 mils. Nickel thickness and uniformity are evaluated both by microsection and X-ray fluorescence measurement techniques.

Phenolic cure of epoxy resins produces high glass transition temperature materials for electrical laminates fabrication. These resins are brittle due to the high crosslink densities. Consequently,this causes high drill bit wear and breakages along with poor drill-hole quality during board fabrication. This can increase cost and pose a reliability concern for the printed circuit board (PCB) industry. A smooth drill-hole wall surface facilitates even copper plating and reduces locations where small cracks or defects can be initiated that can lead to conductive anodic filaments. The current challenge is to incorporate toughening technology that will enable a high Tg,highly cross linked epoxy resin to pass performance tests,reduce drilling costs,and provide smooth hole walls for improved reliability. Furthermore,development of a correlation between PCB drillability and material properties of the composite laminate is critical.
In this work,the drill-hole surface roughness for epoxy formulations toughened with different tougheners is presented. Results show that the drill-hole surface of a non-toughened system suffers brittle failure particularly in the resin-fiber interface. A toughened system,on the other hand,exhibits a smoother drill-hole surface that resists failure in the fiber-resin interface.

In order to meet the never ending desire for smaller and cheaper electronics,many companies are pursuing the use of embedded passive technologies. There are several examples of embedded
capacitors,especially for digital functions such as decoupling. Up to this point however,it has been more difficult to use embedded capacitors as part of RF circuitry such as filters. This is due to the
fact that most materials used for forming embedded discrete capacitors have relatively high loss at GHz frequencies. Also,the capacitance density can change as a function of frequency and
temperature and affect the performance.
New materials have been developed to address the loss and capacitance variation of the typical embedded capacitor materials. The paper will show a comparison of the new versus existing
materials used for embedded capacitors and demonstrate a lower temperature coefficient of capacitance (TCC),lower loss at frequencies up to 10 GHz and stable capacitance density to 10 GHz.
In addition,several manufacturing techniques will be shown to incorporate this material into an organic chip package,as well as ways to minimize the variation of the electrode areas to improve
total tolerance.
In summary this paper will show a path for those who are designing RF modules on LTCC (due to stable performance) a way to reduce cost by going to organic packages and incorporating embedded capacitor materials.

The fabrication of EPAD PWBs have come about in response to the pursuit of reduction in real estate,demand for improved electrical characteristics and higher durability and reliability needs from the end user. The circuit board uses of ALIVH (Any Layer Interstitial via Hole) technology and thinner components have made the manufacture of EPAD PWBs possible.
The major concerns of fabrication are the thinness of the substrate,thinness of the components and the narrow pitch of the ICs. The substrate thinness will lead to deformation of the PWB. During the SMT process,components can be chipped or cracked due to their thinness and substrate thermal expansion characteristics. The narrow pitch of the ICs (C4-FC) can lead to opens due to the same characteristics of the substrate mentioned earlier.
The Flake on Film process combines several tools and processes to deliver a complete package in the manufacture of EPAD PWBs. The use of a Joint Protection Solder paste adds a bonding agent that coats the surface of the solder to the substrate to minimize cracking during and after reflow. The PWB is mounted to an adhesive backed carrier with suction holes for vacuum support and used for the entire SMT process from printing to reflow. After reflow the carrier is separated from the PWB and reused. The use of a Stamping Unit increases the solder volume on the balls to insure proper wetting and the use of the APC system places the components centered to the print to insure proper contact. The use of the FoF process will increase the overall productivity by controlling all aspects of the SMT line from solder paste to reflow.