Many of the latest SMT assemblies for hand held devices like cell phones present a challenge to process and manufacturing engineers with the introduction of miniature components such as .3 mm CSP and uBGA devices as well as 0201 and 01005 chip component devices. Printing these miniature devices along with more conventional SMT devices like .5mm QFP’s and 0603 and 0805 passives,in addition to RF shields is a challenge. Whereas a 4mil (100 micron) or 5 mil (125 micron) thick stencil provides good paste transfer for the normal SMT devices,stencils with this thickness have very low Area Ratios for the miniature devices. For example a .3mm CSP with a 7.5 mil (190 micron) has a .47 Area Ratio for a 4 mil thick stencil.
This paper will examine stencil technologies (including Laser and Electroform),Aperture Wall coatings (including Nickel-Teflon coatings and Nano-coatings),and how these parameters influence paste transfer for miniature devices with Area Ratios less than the standard recommended lower limit of .5. A matrix of print tests will be utilized to compare paste transfer and measure the effectiveness of the different stencil configurations. Area Ratios ranging from .32 to .68 will be investigated.

The reliability,as tested by thermal cycling,of printed wire boards (PWB) are established by three variables; copper quality,material robustness and design. The copper quality was most influential and could be evaluated pretty accurately by microsectioning methods to determine the general quality of the board. Next in the hierarchy of influence came the robustness of material,and the tertiary influence was design. With the advent of Removal of Hazardous Substances (RoHS) causing lead to be removed from solder and the increase in thermal excursions for assembly and rework to 260C,materials tend to be as much a problem as copper quality in the robustness of PWBs. At the new lead free assembly temperatures the materials tend to break down adding to the failure modes caused by lead free assembly. Both the copper quality and material robustness are improving and now PWB designs are beginning to become more influential in the ability to provide a robust board in a lead-free environment. In this paper we will review the general trends in design like the use of non-functional pads,or nickel as part of the surface finish and rank the overall robustness of each.

Working through the New Product Introduction (NPI) flow between the product design and manufacturing is usually a challenging process,with both parties being experts in their own fields and inextricably linked in the flow of getting a new,differentiated product from an idea into physical,profitable reality. Suggestions intended to reduce costs and improve time-to-market are often met with reluctance due to an inability to effectively communicate between these diverse technology cultures.
PCB systems design follows basic or generic manufacturing rules,but still,the manufacturer will find many issues or “opportunities to improve” in each design. Any one of these opportunities can be result in significant cost savings; a small correction up-stream can result in a huge saving when scaled by the volume of manufacturing. The cost of the design alteration “spin” however is also high and potentially delays the product release.
Another factor is the quality of information passed to the manufacturer from the designers. In most cases this is,for example,basic Gerber data format,which must be reverse-engineered,introducing potential for errors and variation. Time needed to reverse-engineer the data results in the reported opportunities to improve often coming too late and less effective than they could be.
A breakthrough,practical methodology to represent and communicate manufacturer’s needs,capabilities,and preferences upstream to the design process would reduce or eliminate the need for respins. Conversely,going down-stream,the manufacturer wants all of the information required to set and prepare processes without reverse engineering.
This paper explores manufacturing needs,and benefits to both design and manufacturing as well as the benefits of efficient transfer of key information from design into manufacturing,eliminating reverse engineering. Together these define a new paradigm for Design to Manufacturing.

A great deal of work has already been done to determine the equilibrium temperature of a PCB when exposed to a heat source such as the thermal environment of reflow soldering. This study will go beyond an equilibrium condition and explore the temperature-time distribution of the board when a variable temperature heat source is applied to both outer surfaces. For simplicity,the model will be a two-sided board. Obviously,the model board has two material interfaces. An interesting observation is that anywhere within the board,including the material interface,thermal energy must be conserved. There is not a similar requirement for the temperature. Consequently,at the material interfaces we can expect the thermal properties’ of the board to change in a profound manner. A similar situation occurs when a fluid passes through a shock wave. This will be reflected in such board properties as the thermal stresses in the various layers and the resulting warp. This phenomenon also explains and quantifies why a thermal shock can be devastating while a slow temperature rise to the same endpoint may well be tolerated.
The analysis will use a one dimensional,time dependent model i.e. there are two independent variables. This necessitates a partial differential equation to describe the temperature variation within the board. The boundary conditions are the outer temperature of the board,which is the temperature of the heat source on both outer surfaces. The third boundary condition is at the copper epoxy interface where conservation of thermal energy is required.

A joint project between Flextronics Inc. and North Star Imaging Inc. is being conducted to correlate current x-ray imaging and cross-section analysis of BGA voiding with state of the art high resolution CT-Scan imaging. Our primary objective is to validate the void measurements obtained from non-destructive imaging techniques,with the physically measured void measurements of cross sectioning. A secondary goal is to characterize void properties before and after reflow.
Typical AXI inspection equipment provides one to three horizontal planes of reference for BGA void measurements. CT Scan imaging provides a full 3D volumetric representation of the BGA void,allowing for size,volume,and void position data. Information that can be used in failure analysis and process characterization projects,without physical destruction of the printed circuit board.
Five 50.0 mm FCBGA devices and five 52.5mm FCBGA devices,with known voiding,are being used in the study. The voiding for each device has been measured on a 3D AXI machine (Figure 1),a2D off-axis high resolution x-ray machine (Figure 2),and CT-Scan system (Figure 3). The devices will then be placed and reflowed onto printed circuit boards. After reflow,all the voiding will be measured again using each piece of equipment. In addition,select voids will be cross-sectioned,polished,and measured using a high magnification digital microscope and correlated to the other x-ray imaging tools.

Prior to committing production boards to vapor phase soldering,we performed an evaluation to assess reliability and evaluate the vacuum soldering option. The reliability of vapor phase processed BGA solder joints,with and without vacuum applied,was evaluated by means of a test vehicle circuit board assembly. The test vehicle was designed with daisy chain nets through multiple solder joints. These were designed with all of the solder balls in a chain having a similar distance from neutral point,so this factor could be part of the reliability assessment. The boards were temperature cycled for 8250 cycles of -5 to 95°C,by which time all of the outermost daisy chains had failed. The number of cycles-to-failure was analyzed using Weibull plots and characteristic life was calculated.

Voids in solder joints are representing one of the main problems especially for power electronics. A low and homogeneous
thermal resistance of solder joints is demanded for a quick and uniform conduction of the heat loss from the power chip. The
same applies for the electrical conductivity of solder joints. Enclosed voids can cause a displacement of electrical and
thermal paths and a local concentration of power and heat. In addition,gas voids are anxious to form spheres in the solder
gap,which could be a cause for tilting of chip components and a wedge-shaped solder gap. This is tightening the problem of
patchy distribution of current or heat and is causing stress and cracks.
The amount of voids can be influenced by different measures,e. g. a good wettability of metallization,solder pastes with
special adopted solvents and an adequate preheating profile. However,a special vacuum process step during soldering is
demanded for absolutely void free solder joints. But this vacuum process is associated with some essential disadvantages.
Besides of the technical expenses for vacuum pumps and additional locks,the vacuum process excludes the use of gas
convection for heating and cooling. Apart from a special vapour phase–vacuum technology,most machines are using
infrared radiation or heat conduction for soldering.
The same principles as used in vacuum soldering technology are applicable also for a higher pressure level. If the void in the
solder joint is arising for an excess pressure,the normal atmosphere pressure could be sufficient for escaping of enclosed gas.
Essential for this effect is the pressure difference between inside and outside of solder joint. A benefit of soldering with
excess pressure is the possibility of gas convection for heat transfer. This allows the application of conventional components
and the realization of the usual temperature distribution and profiles.

The world of spring-loaded test probes and special probes for in-circuit and functional tests have grown tremendously over the past few years. Ever increasing demands for electro mobility applications,the telecommunications market and the automotive sector force the manufacturers to think beyond the concepts of a traditional standard probe in order to meet the demands of today’s highly complex test applications. In this paper,we like to demonstrate probing concepts for three different scenarios: (1) High speed probing for fast data rate applications,(2) high current probing for multi-probe-environments and finally (3) pneumatic probing for sequential probing applications and fixtureless installations. The challenge for all application areas but especially for high current and high frequency probes is to not only look at the mechanical properties of a test probe to successfully mate with the counterpart but to follow a holistic approach to combine high frequency behaviour etc. with mechanical aspects.

Test point optimization for the PCB electrical test domain brings the test speed faster for the flying probe tester (FPT),
and the fixture cost lower for the fixture type tester. The importance of optimization is increasing along with the shrink of
PCB design rule,especially for the fixture type testing.
There are 2 types of test point optimization:
1. Probe position optimization (position optimization of the probe contact point in the test pad for the larger
margin). The optimization reduces the probe contact failure for the FPT and fixture,so that the pass rate
increases.
2. Probe type optimization for the fixture type test (selection of optimum probe type such as size and head
shape). In general,the smaller the probe diameter,the higher the probe pin cost. So the cost of fixture
can be reduced by selecting the larger diameter probe pins.

Many companies use “one stop testing” as a solution to the test issues in a manufacturing environment rather than discrete
“islands of test”. Low volume,high mix electronic manufactures are concerned about floor space,which can be expensive.
As well as operator training,which can be considerable if a separate test solution is used for each product manufactured.
Very high volume manufacturers can also benefit from a single stage electrical test solution if the test times are less than the
beat rate of the line. This is especially true if the system in fully automated. As with low volume manufacturers floor space
and operator training costs can be reduced,but the significant saving is in early defect detection that helps reduce scrap rates
and improves line efficiency.
By combining electrical test into one system and having the system directly integrated into the production line,the system
can detect defect at the earliest stage of the board manufacture. As a base,incircuit test (ICT) is a well-established electrical
test technique and has been used successfully for a number of years and has a long history of being integrated into the
production line. PXI has established itself as the standard for cost effective integrating of functional instruments into a test
system. By combining ICT and PXI into one solution,it can perform incircuit test,help overcome ICT access issues and
perform functional tests. This universal test solution provides a smaller footprint,consistent operator interface and overall a
lower cost of test.
This paper will discuss the advantages of a universal integrated electrical test solution,at the normal Incircuit Test stage of
production,to minimize production costs and help improve product quality using two case studies. One is a low volume
high mix manufacturer and the other a high volume automotive electronics manufacturer.