The challenges of successful solder printing in the High Volume / Low Mix cell phone environment,which is linked with the continuing trend to miniaturize electronic assemblies,requires a new approach to improve the printing capabilities and process repeatability. Actual stencil technologies such as electroform or laser-cut limit the stencil opening due to aspect and area ratios at the smallest devices producing a very tight process window. It’s here that Nano Technology will assist in the printing process. Using Nano Coating over the stencil openings to smooth the surface and improving the paste release,helps reducing aperture openings,and creates a wider process window. Additionally,panel stretch and PCB fabrication tolerances produce a silent non constant variable that moves the process outside the quality printing window,without obvious signs of variation.
To obtain an advantage,and successfully implement this technology,the process requires new controls of chemical and parameter settings. We will discuss some aspects of process optimization and how this very tight process window is affected,by identifying the challenging process parameters,including circuit board fabrication,component pad design,and printing parameters (speed,separation,pressure,etc.). This printing study will consider the effects of print speed,print pressure,and separation speed,to optimize solder paste transfer efficiency (TE) to establish an statistical process control that gives real time warnings of an out of control printing process. We will discuss our data results which will include the advantage of using Nano stencil vs. E-Fab and Laser NiEX. TE improvement is 5% at the smallest stencil aperture across a panel of 4 images. The cleaning speed significantly reduces defects from 2% with a 50mm/sec,to zero defects using 20mm/sec. By improving the TE by 5% will increase the number of prints without a paste bridge on any board,even up to10 prints between cleaning.

We describe a coupon design that makes available,in an elegant and efficient way,information unattainable even from multiple-coupon vertical cross-sections. The new design allows quantitative determination of annular ring and of breakout angle on internal layers of printed circuit boards. The new design provides evidence for compliance (or lack of it) with user requirements regarding internal annular ring and breakout angle. It permits assessment of the adequacy of design rules and allows collection of data for statistical process control or process optimization via designed experiments.

The desire to have more functionality into increasingly smaller size end products has been pushing the PCB and IC
Packaging industry towards High Density Interconnect (HDI) and 3D Packaging (stacked dies,embedded packaged
components). Many companies in the high-end consumer electronics market place have been embedding passive chip
components on inner PCB and IC Packages for a few years now. However,embedding packaged components on inner
layers has remained elusive for the broader market due to lack of proper design tools and high cost of embedding
components on inner layers. Many more companies worldwide now have development projects,prototypes or first series
of embedded products that are starting to be produced from several manufacturing sources. Miniaturization and 3D
integration are clearly the drivers for PCB embedding technology to support new silicon packages and modules with
active and passive components. Environmental issues around the technology are becoming important and need to be
properly managed to generate an error free path from the generation of the design data through the production line to the
functional test. The standardization on the embedding technology has been started years ago and this year the activities
for functional test have begun.
This paper will highlight several key industrialization aspects addressed in the frame of the European funded FP7
HERMES* project to build a manufacturing environment for products with embedded components. The program entered
its third year and is now dealing with the manufacturing of functional demonstrators as an introduction to
industrialization.
The focus of the paper will be placed on three critical activities:
- The development of a PCB CAD design solution that supports embedding packaged components.
- The thermo-mechanical activities performed to support the definition of design rules. The latter has been achieved
through FEA simulations supported by a comprehensive test program based on strain gage measurements under
torsion which will be detailed. The work enabled to characterize the mechanical behavior of embedded PCBs taking
into account the build-up as well as the effect of soldered components,which ensures reliable and highly functional
embedded PCBs and modules.
- The high production yields in order to achieve a cost effective technology driven by process control and using
advanced tools like high definition 3D laser scanning.

In light of new process and product technologies in the field of embedded components,questions arise with respect to
advantages and potential disadvantages to standard SMT component placement when considering reliability.
The fact that components are embedded in the substrate opens up new variables in terms of drop test resistance and
thermal cycle test.
- One may expect fundamental qualitative differences to galvanized bonds within a laminate framework in
comparison to current external solder joint performance.
- One may expect variations in the component thermal integrity of an embedded component within a substrate
and that of a soldered component when subjected to TCT test conditions.
This paper aims at analyzing and confirming the reliability performance (in terms of the above identified test criteria) of
embedded components compared to that of standard SMT components through usage of embedded and SMT soldered
component test vehicles. These analyses make use of the process technologies and methodologies of the currently
running EU-funded project “Hermes”.

High temperature operating life (HTOL) testing was performed on embedded planar capacitors (with epoxy- BaTiO3 composite dielectric) by subjecting these devices to highly accelerated temperature and voltage aging conditions. The objective of HTOL testing was to precipitate avalanche breakdown failures as a result of defects in the composite dielectric. These defects include porosity,voids,and agglomeration of BaTiO3 in the epoxy matrix and are introduced during the manufacturing process. Since these tests were conducted under highly accelerated conditions,the failure mechanisms observed may not occur under the normal operating conditions of this device. However,the results of HTOL can be used in qualification of embedded planar capacitors and to further improve manufacturing processes to reduce the number of these defects.
During HTOL testing,the failure modes observed were a gradual decrease in the capacitance and a sharp decrease in the value of insulation resistance. The sharp decrease in the value of insulation resistance after some time was expected to be governed by the avalanche breakdown (ABD) of the dielectric. The ABD failures were modeled using the Prokopowicz model. The effect of the area of the capacitor and dielectric thickness on the time-to-failure as a result of ABD was also investigated.
A novel failure analysis technique was developed that can be used to locate the failure site of avalanche breakdown and understand the failure mechanism in this material. This technique can also be applied to some other dielectric materials as well. It was also observed that before ABD failures the dielectric material started to show signs of degradation. These degradations were detectable using AC measurements (measurement of dissipation factor) but were not observed in DC measurements (measurement of insulation resistance).

Some ball grid array suppliers are migrating their sphere alloys from SAC305 (3% Ag) or SAC405 (4% Ag) to alloys with lower silver contents and often with “micro alloying” additions. There are numerous perceived reliability benefits to this change,but process compatibility and thermal fatigue reliability have yet to be fully demonstrated. The current study has been undertaken to characterize the influence of alloy type and reflow parameters on low-silver SAC spheres assembled with backward and forward compatible pastes and reflow profiles. This study combines low-silver sphere materials with eutectic tin-lead and lead-free SAC305 solder pastes.
This is the seventh report in a series being published as data become available,and presents the results of the thermal cycling of mixed metallurgy solder joints. Thermal cycling conditions include both 0 to 100oC and -40 to 125oC,with 10 minute dwell times. The accelerated thermal fatigue reliability of mixed Sn-Pb/Pb-free solder joints with varying Ag and “micro alloying” element concentrations are compared to those of 100% Sn-Pb and 100% Pb-free joints for four different package types. Further,the impact of thermal cycle conditions on the rank order of the reliability for the different solder joint compositions is presented. The implications of the data regarding the efficacy of using BGAs balled with low Ag alloys and soldered with Sn-Pb paste,and areas for future work are discussed.

Many BGA and CSP component suppliers have begun shipment of components with a variety of second generation lead-free
solder ball alloys based on the improved mechanical shock resistance. Although in general mechanical performance has been
improved,there have been questions raised on how much the mechanical performance of these lead-free solder ball alloys
can vary with different board surface finishes such as NiAu and OSP.
Mechanical testing was performed on Sn3.5Ag and Sn1Ag0.5Cu 676 PBGA components with 1mm pitch and electrolytic
Ni/Au finished component pads. These components were soldered with Sn3Ag0.5Cu paste on either electrolytic Ni/Au or
high temperature rated OSP board surface finish. The mechanical shock data indicated that among the four board surface
finish/BGA component sphere alloy combinations,the Sn1Ag0.5Cu (SAC105) BGA sphere with NiAu board surface finish
had the lowest drop test resistance among the combinations evaluated,which was not expected.
Failure analysis of this and the other drop test combinations was carried out by dye-pry analysis and cross-sectioning to
understand the failure locations on the soldered BGA joints. The results were assessed in terms of Weibull failure distributions,failure modes,failure locations,and microstructural analysis which included IMC thickness measurement and IMC compositional analysis and distribution. This analysis suggested a possible direct or indirect relationship between drop test results and unique IMC spalling of the Sn1Ag0.5Cu (SAC105) BGA sphere with NiAu board finish. The implications of these findings and areas for further study are discussed.

With a melting point of 199°C,about 20°C lower than the liquidus temperature of SAC305 the Sn-Zn eutectic (Sn~9% Zn) appears to be an attractive candidate as a Pb-free solder. With,at July 2010 market prices,a raw material cost less than half that of SAC305 the Sn-Zn eutectic also has the attraction of substantial cost savings. And,in contrast with Ag,Zn is a relatively abundant element of low toxicity with a comparatively low impact on the environment. The mechanical properties of Sn-Zn alloys are more than adequate in most situations and they have found widespread application in specialised areas such as the joining of high voltage aluminium cables. The Sn-Zn eutectic has,however,found only limited application as a Pb-free solder in electronic assemblies because of early mechanical failure on Cu substrates where the substantial difference in electronegative potential drives galvanic corrosion in the presence of even quite low levels of moisture and ionic contaminants. In this paper the authors report studies that indicate that with the use of a microalloying addition of Mn joint integrity can be maintained on some of the substrates commonly encountered in electronics assembly. Sn-Zn alloy solder joints were exposed to high temperature (150°C) and humid heat (85°C/85% RH) for up to 1000 hours,the mechanical properties measured and the microstructure monitored. Joints were also exposed to salt water and to electric current under conditions of heat and humidity. These studies indicate that there is potential for wider use of alloys based around the Sn-Zn eutectic as solders in electrical and electronic applications.

Properties of printed circuit board laminates are a function of the type and levels of its components. Endeavors to a balance various performance criteria involve balancing the types and amounts of materials that can have similar or opposite effects on key properties. This paper explores the combined use of silica with use of silica and PPE macromonomer in optimizing properties of epoxy-based laminates. Silica exhibits low dielectric properties. However,particulate fillers can lower the toughness of composites. PPE macromonomer has been shown to be very effective in enhancing properties of epoxy resins. In particular,PPE macromer increased the toughness and improved the dielectric properties of epoxy-based laminates. Hence,the combination of PPE macromer and silica filler suggests a way to expand the performance window of epoxy-based laminates. Structure property evaluations were used to quantify the effects epoxy/silica,epoxy/PPE,and epoxy/PPE/silica on dielectric properties,CTE,toughness,and flexural properties. Types of silicas evaluated included ground,fused,platy,and diatomaceous earth. The results showed that using the macromoners in conjunction with silica give performance enhancements over epoxy-silica,or epoxy-PPE alone. Epoxy-based laminates were made which exhibited low Z-axis CTE and low loss tangent.

With ever increasing data transfer rates,insertion loss has become a limiting factor on today's systems.
Insertion loss can be separated into dielectric loss and copper loss. While dielectric loss can be influenced by choosing a base material with the appropriate dissipation factor,copper loss is more complex.
Copper loss is a function of bulk resistivity,cross sectional area of the conductor,conductor surface roughness as well as frequency. Conductor surface roughness is influenced by the copper foil type (STD,LP,VLP,…) and the oxide replacement process during PCB manufacturing.
To better understand the contributing factors to copper loss,the influence of the copper foil roughness,'as received' and 'modified by the oxide replacement? was evaluated.
A DOE was performed with three different types of copper foils (RTF,VLP,ultra low profile) and ten different oxide replacement chemistries. Insertion loss as well as impedance and DC line resistance were measured on the various test samples. The results were compared using a statistical ANOVA approach.
The paper describes the performed measurements and will discuss in detail the influence of copper foil,oxide replacement,line width and copper thickness on the key parameters impedance,DC line resistance and insertion loss. An 'analysis of variances process' is used to understand the level to which the contributing factors affect the electrical parameters.
A measurement at two different frequencies is used to demonstrate the varying influence of the independent variables on insertion loss.