In today’s PCB industry,the challenges are no longer just on how to control and improve the manufacturing
processes,but also to ensure the fabricated product is compliant to the industry standards and leads to high quality. Due to the
requests for more detailed information about the products,numerous techniques for PCB characterization were developed. In
this paper,we proposed the Enhanced Root Impulse Energy (e–RIE) loss method. The original RIE was presented in the
papers and presentations of IPC meetings. Different from previous work,instead of directly differentiating the time–domain
TDR waveform and using it as the impulse response h?t ?,the e–RIE method implements the time–domain Thru–Reflect–
Line (t–TRL) calibration technique on the time–domain TDR/TDT measurements. The t–TRL is a complete calibration
technique and it removes the discontinuities due to the transition from SMA connectors to the stripline launches and
improves the accuracy of impulse response measurement and the RIE loss calculation. Excellent agreement is achieved for
the RIE losses obtained from the t–TRL and the VNA measurements. Also in the paper,the relationship of the RIE loss and
loss tangent is studied. Based on the theoretical derivation,the RIE loss is calculated as a function of tan? for a given pair of
test and calibration lines. The sensitivity of RIE loss vs. different test and calibration pairs is studied. Overall,the longest test
line (>10 inches) and the shortest calibration line (<1 inch) give the best RIE loss sensitivity. The e–RIE extended the
applications of the original RIE method and it provides a simple and practical test method for the transmission line loss
characterization in high–volume PCB manufacturing.

Circuit housings used in industrial and utility applications have requirements often not needed in the commercial or consumer electronics industries. The device may be used in locations as diverse as in a chemical factory,wind turbine,transit station,offshore platform,wastewater control panel,or a Smart Grid communications box. These applications often require a high degree of resistance to shock and vibration. They may also be required to operate over wide temperature ranges,especially if mounted in outdoor locations where a lot of electronic equipment is now deployed. They might need to adhere to specific shielding requirements or conform to certain physical sizes and shapes. Others may require DIN mounting options or have touch-safe connector requirements. This presentation will introduce the audience to these issues and provide information about how organizations such as the IEC address them with standards and approvals.

It is widely known and understood that the overall cost and quality of a product is most influenced by decisions made early in the design stage. Finding and correcting design flaws later in the product development cycle is extremely costly. The worst case situation is discovering design problems after failures occur in the field.
Designing for reliability has been “easier said than done” due in large part to the many competing interests involved in a design. For example,the designer is challenged with increasing the product performance while continually reducing the form factor. The reliability engineer may raise concerns about design risks,but without the ability to quantify the potential impact,they are often unable to meaningfully influence the design decisions. Implementing a newly developed reliability prediction analysis tool,Sherlock,will forever change this equation. Before a single product is built,this valuable new tool enables the engineer to import the design files and quantitatively predict the life of the product according to the assumptions made for the user environment. The failure rate is predicted for thermal cycle fatigue of solder joints and plated through hole vias as well as for shorting from conductive anodic filament (CAF) formation. The software also produces a finite element analysis of the circuit boards showing regions susceptible to excessive board strain during vibration or shock events. The greatest value comes from the ability of the engineers to perform various “what if” scenarios to determine the impact of any number of design choices.
? What if I change the mount point locations?
? What if I change the via diameters,the spacing,or the copper thickness?
? What if I change the laminate thickness or material selected?
? What component is at highest risk of failure and what if I change its? format?
? What is the reliability impact of changing from SnPb to SAC305 solder?
Finally,once the design has been optimized to satisfy the many competing requirements,the software can be used to predict the rate of failure over the lifetime of the product. This information can then be used to more accurately plan for the warranty costs. With margins shrinking in the electronics industry,OEMs depend more on profits from extended warranties. Inaccurate life prediction can cut heavily into this income stream. Under-prediction of the failure rate will lead to cost overruns while overestimating failure will mean lost business to competing extended warranty plans and the setting aside of funds that could instead be used for further product development. This paper will illustrate the capabilities and value that this new tool provides to the various functional units within an electronics manufacturing company.

Modern electronics typically consist of microprocessors and other complex integrated circuits (ICs) such as FPGAs,ADCs,and memory. They are susceptible to electrical,mechanical and thermal modes of failure like other components on a printed circuit board,but due to their materials,complexity and roles within a circuit,accurately predicting a failure rate has become difficult,if not impossible. Development of these critical components has conformed to Moore's Law,where the number of transistors on a die doubles approximately every two years. This trend has been successfully followed over the last four decades through reduction in transistor sizes creating faster,smaller ICs with greatly reduced power dissipation. Although this is great news for developers and users of high performance equipment,including consumer products and analytical instrumentation,a crucial,yet underlying reliability risk has emerged. Semiconductor failure mechanisms,which are far worse at these minute feature sizes (tens of nanometers),result in higher failure rates,shorter device lifetimes and unanticipated early device wearout. This is of special concern to users whose requirements include long service lifetimes and rugged environmental conditions,such as aerospace,defense,and other high performance (ADHP) industries. To that end,the Aerospace Vehicle Systems Institute (AVSI) has conducted research in this area,and DfR Solutions has performed much of the work as a contractor to AVSI.
Physics-of-Failure (PoF) knowledge and an accurate mathematical approach which utilizes semiconductor formulae,industry accepted failure mechanism models,and device functionality can access reliability of those integrated circuits vital to system stability. Currently,four semiconductor failure mechanisms that exist in silicon-based ICs are analyzed: Electromigration (EM),Time Dependent Dielectric Breakdown (TDDB),Hot Carrier Injection (HCI),and Negative Bias Temperature Instability (NBTI). Mitigation of these inherent failure mechanisms,including those considered wearout,is possible only when reliability can be quantified. Algorithms have been folded into a software application not only to calculate a failure rate,but also to produce confidence intervals and lifetime curves,using both steady state and wearout failure rates,for the IC under analysis. The algorithms have been statistically verified through testing and employ data and formulae from semiconductor materials (including technology node parameters),circuit fundamentals,transistor behavior,circuit design and fabrication processes. Initial development has yielded a user friendly software module with the ability to address silicon-based integrated circuits of the 0.35um,0.25um,0.18um,0.13um and 90nm technology nodes.

Cost reduction in electronic assembly and soldering is a key issue for economic survival in the global market. Very promising
ways to reduce failure costs and increase productivity are: reduce solder paste bridging and reduce soldering failure modes
caused by insufficient solder paste depots. Increase line Productivity by reduction of cleaning frequency in the stencil printer. Nowadays highly sophisticated nano-coated laser cut stencils show an increasingly significant role in electronic production. The potential of nano-coated stencils is demonstrated with extensive printing experiments and is shown in this paper,
especially for critical area ratios. The stencil design was build up on BGA´s and QFP-structures with an area ratio going
down to a value of approximately 0,4.
The coating process is based on a Sol-Gel process and is followed by a temper process to start a multistep polymerisation.
The reaction layer is responsible for the high chemical- and mechanical resistance and provides the stencil with a high antiadhesion effect with a low surface energy. The coating is applied on the bottom side of the stencil and in the aperture walls.
The nano-coated surface offers a high functional surface with hydrophobic character and minimized adhesion of the solder
paste which results in a high efficiency of the printing process with a significantly reduced failure rate. An additional advantage of the nano-coated stencil is the reduction of cleaning intervals of the stencil bottom side due to the fact,that the adhesion of the solder paste to the stencil is dramatically reduced. Cost saving for less cleaning material is obvious and goes hand in hand with higher production line efficiency.
Further the paper shows the significant increased freedom of design rules due to the fact of smaller area ratio.

The demand for product miniaturization,especially in the handheld device area,continues to challenge the board assembly industry. The desire to incorporate more functionality while making the product smaller continues to push board design to its limit. It is not uncommon to find boards with castle like components right next to miniature components. This type of board poses a special challenge to the board assemblers as it requires a wide range of paste volume to satisfy both small and large components. One way to address the printing challenge is to use creative stencil design to meet the solder paste requirement for both large and small components. Examples of stencil design include step stenciling,dual printing,over-size apertures,etc. The stencil printing process,at its most basic level,involves pushing solder paste through a stencil (with various size apertures) by a squeegee blade. As the squeegee blade and the stencil are in constant contact with the paste during the printing process,their surface characteristics play an important role in the printing process. The most important attribute of a stencil is its release characteristic. In other words,how well the paste releases from the aperture. The paste release,in turn,depends on the surface characteristics of the aperture wall and stencil foil. The recent introduction of a new technology,nano coating for both stencil and squeegee blades,has drawn the attention of many researchers. As the name implies,nano-coated stencils and blades are made by conventional method such as laser-cut or electoform then coated with nano-functional material to alter the surface characteristics. This study will evaluate nano-coated stencils for passive component printing,including 01005. Various print experiments will be conducted using different stencil technology,stencil thicknesses,aperture size,aperture orientation,aperture shapes,and selected paste type,with optimal print parameters to understand the effect of chosen factors on the print quality. Print quality will be determined by visual inspection and 3D measurement of the paste deposit to understand the volume transfer efficiency.

As consumers the expectation of increased functionality within new products is a given. However there comes a time where this tireless demand for product efficiency starts to stretch the design for manufacture (DFM) rules. Fabricating products with decreasing feature size and increasing complexity is not the issue nor is producing products that have larger components; the dilemma is when products require both.
This predicament is now upon the Surface Mount Assembly (SMA) community,the imminent role out of 0.3mm CSP looks to be pushing the feature size below 200 micron but still RF shields and connectors are required - or put another way heterogeneous assembly is looming upon us.
The main issue surrounding the stencil printing process when dealing with heterogeneous assembly is area ratio (the ratio between stencil aperture open area and aperture wall area). When complying to traditional design rules and maintaining area ratios greater than 0.66 then it becomes near impossible to design a print process for a wide mix of fine and large pitch components.
Whilst developments in solder pastes and stencil manufacturing techniques in recent years have allowed skilled operators to push the area ratio rule of thumb to 0.5-0.6 to accommodate 0.4CSP assembly,the next generation of component technology (0.3CSP’s) is one step beyond this capability.
To address this,new techniques have been investigated with the aim of increasing solder paste transfer efficiency in the screen printing process. Of several techniques investigated one has stood out and has been the subject of intense laboratory trials. The results of this investigation have shown that existing area ratio rules can be seriously challenged and broken to permit 0.3mm pitch CSP assembly within a traditional SMT process. Details of these new developments together with substantive paste transfer efficiency data will be presented.

Handheld portable products such as smartphones are trending toward smaller form factors while simultaneously increasing in functionality to keep up with consumer demands. This is achieved in part by decreasing the size of components and increasing the density of the circuitry. These unique product needs drive different Design for Manufacturing (DFM) recommendations than those that are in use for larger products – while for larger products,reworkability is paramount,for handheld portable products,high first pass yields and fitting the required functionality into an appropriate form factor are of greater concern in many cases.
This paper summarizes a new test vehicle designed to emulate a next-generation smartphone product. One of the goals of this project was to study the effect of pad design and component spacing on assembly yield. The test vehicle includes a representative range of component types including 01005 and 0201 discretes,0.3mm pitch CSPs,Package-On-Package,QFNs,and RF shields. For selected components,different pad designs were included on the board,allowing a direct comparison of the various options and recommendations for the optimal pad designs. In addition,a range of component to component spacings were used on the board,ranging from spacings in common use in today?s products to extremely aggressive spacings that push the limits of the PCB manufacturers. The test vehicles were inspected after assembly,and yields were determined for the various component to component spacings studied to determine what the limitations are and to update DFM rules specific to the needs of extremely dense handheld portable products.
The results of the yield study will be presented along with the analysis of the implications for the DFM rules.

Although many of the QFN and bottom termination products are small in outline and utilize a plastic encapsulated copper
lead-frame structure they do not resemble the more traditional small outline (SOIC) lead-frame packaged semiconductors
because the termination features do not extend beyond the package edge. Many of the QFN packages have an exposed die
attach pad (DAP) feature on the package bottom surface to provide a more direct thermal interface with the mating circuit board surface. Since there is no protruding lead on the package and DAP features are relatively large,solder defects are often beyond acceptable levels.
Key issue: Because the DAP feature can be rather large,printing solder paste with a matching outline can result in uneven solder distribution during the assembly process. This uneven solder distribution causes the parts to tilt,often causing solder bridging and/or disconnect of the perimeter located terminal contacts.
Solution: To compensate for this condition and potentially reduce solder defects,unique DAP print pattern variations can be adopted. Optimizing the solder stencil pattern will ensure that the package bottom surface remains parallel with the circuit board surface during the reflow solder attachment process.
In this paper we will review a wide range of plastic encased no-lead package configurations,industry package standards,and terminal design variations as well as defining the criteria for land pattern design and solder paste stencil development and assembly process methodologies detailed in the new IPC-7093 standard,“Design and Assembly Process Implementation for Bottom Termination Components”.

The CAD library is the starting point that affects every process from PCB layout through PCB manufacturing and assembly. There are dozens of things to consider when creating a CAD library that are often overlooked or not even considered that will directly affect the quality of the part placement,via fanout,trace routing,post processing,fabrication and assembly processes. Part 1 of this paper describes every aspect that should be considered when creating chip CAD library parts and the impact that each feature of the CAD library has in the PCB process.