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As the electronics industry prepares to meet the requirements of the European Community’s RoHS directive on lead in electrical and electronic equipment an issue about which concern is frequently expressed is the apparently inferior wetting performance of lead-free solders. The general observation is that lead-free solders are slower to wet and then do not spread far beyond the area of direct contact. There is also much discussion of the relative merits of various lead-free solders in terms of their wetting time,which is usually reported as the time from first contact of the sample with molten solder to the time at which the net force on the sample is zero. However,the performance of some lead-free solders in this wetting balance test has been found not to correlate with their practical performance in soldering processes; an alloy with what appears to be
inferior performance in the wetting balance test performs better in actual production soldering than an alloy that had a better result in the wetting balance test. In the work reported in this paper the data that emerges from a wetting balance test was studied in detail. It was found that the result of the wetting balance test could be correlated with the performance of the alloy in production soldering only if the force vs time plot is analysed in terms of five distinct stages with the performance of the alloy as a solder correlating best with time taken for the force to increase from its maximum negative value to zero and then
to the maximum wetting force.

Lead-free wave soldering requires tighter process control than soldering with lead based alloys. A key area of the machine that impacts the ability to solder lead-free alloys without defects is the flux system. A large variety of fluxers are available for use with lead-free soldering - each having advantages and disadvantages. This paper compares the more popular flux systems in terms of through hole penetration,coverage accuracy,cost level,maintainability,and chemical compatibility. Ultrasonic,air atomization,and jet type flux systems are discussed and test data presented for each system.

The process challenges of lead-free wave soldering often require the use of new flux chemistries when compared with the relatively tolerant tin-lead wave soldering process. In some cases,the fluxes used in tin-lead soldering work well in lead-free assembly. In other cases,however,the complexity of the assemblies dictate more active,heat-sustainable products formulated specifically for lead-free applications.
This paper reviews the J-STD-004 and how it is used in flux categorization and selection. It also discusses the major types of flux formulations available,and the design,process and reliability implications of using each type. The purpose of the paper is to help the reader make an informed choice when selecting wave solder fluxes for lead-free processing.

Since the beginning of the digital printing era,methods have been sought to employ this knowledge for use in an elegant approach for producing circuitry. As long ago as the early 80s,companies were working with inkjet printing to apply a
conductive or catalytic ink to standard circuit substrates in the quest to build an additively printed circuit. In 1983,I visited a small Silicon Valley startup company,Elf Technology,with Joe Fjelstad. In this small office park,Joe had taken a standard desktop inkjet printer and developed an ink with high enough conductivity to support electroplating. He was able to go from CAM file to inner layer on a desktop followed by electrolytic plating. Unfortunately,the technology
never made an impact on the market. In the mid 1990s,while working at Litchfield Precision Components (now Innovex),I was involved in a development project with a spin off of Bayer AG called AMEG. This small engineering company had developed a UV curable ink that was catalytic to electroless copper and could be photoimaged. We discussed inkjet application at the time,but the project stalled because of continuing problems with the stability of the ink bath.
With advances in both inkjet head technology and ink formulations,the pursuit of this ultimate “printed” circuit has advanced to the point that in 2007 we should see an impact in the market.

Increased electronic functionality can be achieved through the development of more complex silicon integration but that course generally requires a great deal of capital resources and an excessive amount of time. Hand-held communication and entertainment products necessitate a very short development cycle. And,with each generation offering more and more features and/or capability,rapid deployment of system level integration and miniaturization becomes a priority. In addition,the end user is expecting that each generation of product to be smaller and lighter that its predecessor. Companies are finding that for these rapidly evolving products,the multiple-die package concepts are proving superior to the system-on-chip alternative because it minimizes financial risk and has the potential for economically integrating several different but complementary functions. The paper developed for the IPC APEX program presents a view of current expectations for multiple-die BGA and CSP technology for wireless applications and review the evolution taking place in developing systemin-
package capability.

This paper presents the results of our study on the development and optimization of lead-free wave soldering process for large and thick printed circuit boards (PCB),through multiple designs of experiments (DOEs) including many variables from design,material,component and process. Design variables were pin-to-hole ratio,pad diameter,annular ring diameter,component orientation,spacing,thermal relief pattern,internal copper thickness,and the number of copper layers connected to PTH barrel. Material and process variables included flux materials,flux amount,preheat temperature,solder pot temperature,conveyor speed,contact time,wave atmosphere and wave system. A variety of plated through hole (PTH) components were tested. Two board thicknesses (2.4mm and 5.0mm) and two board surface finishes (immersion silver and immersion gold) were used. The results showed that there were strong correlations between flux materials,process conditions and hole-fill. Bridging and insufficient solder defects were reduced by optimizing wave process parameters. Design parameter optimization could be used to improve the PTH hole-fill,and reduce defects of PTH bridging,insufficient solder on SMT components,and voiding in the PTH solder joint.

fast approaching this horizon is the 0.3mm CSP. This device represents a major assembly revolution within the Surface mount assembly (SMT) arena. The implementation of this device will require arrays of mass imaged solder paste that only a few years ago where within the hemisphere of semiconductor fabrication. This transition into SMT is a huge step when you consider the typical sub 7 sec cycle times requirements of SMT against relatively slow Semicon ball bumping cycle times,the thin uneven FR4 boards generally used in SMT against the perfectly flat wafers found in Semicon and the standard working environments opposed to the clean room environments found in Semicon.
This paper will research the key elements that influence the deposition process. Process design factors such as solder paste,squeegee construction and stencil design will be fully investigated. In addition the impact of typical fabrication defects associated to the fabrication of stencils will be observed to ensure that an authentic picture is created and not one that belongs in a laboratory. The deliverables from this paper will be clear and concise implementation solutions for the surface mount engineers who are about to encounter the 0.3mm C.S.P.