Highly dense circuit assemblies increase the cleaning challenge. Batch cleaning equipment designs provide a small footprint,low cleaning fluid consumption,and low cost of ownership. Batch cleaning machines use flow,time,temperature,impingement,and advanced cleaning fluids as critical drivers for delivering a clean part. Increased density,low standoff components,and Pb-free flux residues place increased importance on the cleaning fluid design. There is a need for improved cleaning fluids to remove Pb-free flux residues from populated circuit assemblies in batch cleaning machines. The purpose of this designed experiment is test populated circuit cards using innovative new cleaning fluid designs on a range of popular Pb-free flux residues in batch cleaning equipment. Validation will be reported using visual images of the test assemblies processed within the designed experiment.

One of the most popular pieces of equipment in the PCB fabrication industry is the inline processor. These machines are used for a variety of tasks including resist removal,etching and cleaning. In most cases,the machines are multi chambered,with a counter flowing chemical solution. The solution is normally pumped from the chamber to spray nozzles which deliver the solution to the work piece; a PCB panel. After impinging upon the panel the solution drains back into the chamber along with the dissolved superfluous material. Anecdotally,the effectiveness of these processors is related to the rate of product throughput,rate of turnover of the chemistry in chamber,the rate of introduction of fresh chemistry and volume of the chambers. The intent of this investigation is to mathematically model the performance of these processors and thereby characterize the behavior. The most important result of the analysis is identifying an initial transient in these processors which occurs at startup and may require a half an hour or more to reach a steady state condition. During this period,the so called breakpoint will fluctuate (that is the position in the processor where visually the superfluous material on the panel appears to have been removed down to the base material) Most PCB processing engineers have empirically accounted for this behavior by processing “dummy” panels at the outset of the process,hopefully exceeding the time of the transient. During this transient the performance parameters will vary in both time and position which will render machine characterizations (such as DOEs) futile. For purposes of this model it is assumed that the principal mechanism for removal of the superfluous material is dissolution. It is also assumed that the dissolution rate is proportional to the saturation level of the working solution and that when saturation is reached; the solution becomes inert for purposes of this process.

In recent years,various studies have been issued on cleaning under low standoff components; most however,with incomplete
information. It is essential to revisit and describe the latest challenges in the market,identifying obvious gaps in available
information. Such information is crucial for potential and existing users to fully address the cleanliness levels under their respective components. With the emergence of lead-free soldering and even smaller components,new challenges have arisen including cleaning in gaps of less than 1-mil.
This study was initially designed to investigate the impact of mechanical vs. chemical energy contributions during the removal of contamination under 1-2 mil standoff components. To validate the results obtained,extensive studies were conducted,specifically prepared test-assemblies,iterative experimentation,as well as new mechanical innovations that might help users in the future. The latter include,but are not limited to,various flow pattern designs and industry-leading cleaning agents. As a result,the authors will also include experimental data to address fluid flow mechanics,temperature and solvent concentration-related effects.
Initial results obtained indicate that cleanability of residues under low standoff components has become a non-trivial issue. Not only are residues becoming harder to remove,the penetration of the cleaning agent seems to be in direct relationship with the geometry and height of the components in question.

The flux management system for a reflow oven is highly critical to the quality,cost,and yield of a reflow process. Flux accumulation and dripping inside the oven not only requires frequent maintenance,it can also result in poor quality,low throughput,and safety issues. Understanding that high volume electronics manufacturers do not like downtime for maintenance,this is the driver for continued development of advanced flux management systems that incorporate self-clean features and do not require interruption of production for maintenance activities.
This paper will review some basic past and present flux chemistries that affect flux collection methodology. It will also review some of the most common flux collection methods,self-cleaning techniques,and maintenance goals. And,finally,data will be presented from high volume production testing of an advanced flux management system.

Mixed leaded and lead-free processing requires that reflow ovens change temperature. Cooling a modern oven can take a long time,even longer than an older oven because modern ovens are more insulated. We recently acquired new ovens and needed a method to cool them quickly. We analyzed two methods,a method of letting the oven cool without intervention,and a method of running aluminum heat sinks through the oven. Other methods,such as opening the oven or injecting liquid nitrogen,are also considered,but no analysis was performed on these methods.

New packaging technologies are making higher demands on components and also jointing techniques. The application of
polymer electronics as well as the integration of optical components into the PCB results in a maximum admissible soldering temperature of 150°C on the one hand. The introduction of new lead-free solders raises the soldering temperature up to
260°C on the other hand.
The main objective of developing the soldering methods for electronic devices in recent years was to ensure homogenous
distribution of the temperature over the entire board. The introduction of convection soldering therefore showed great
advantages compared with the infrared soldering processes which were being used previously. Vapour-phase soldering meets the demands of special components and assemblies which can only withstand slight variations in temperature.
It is no longer sufficient to satisfy the requirements of merely distributing the heat homogeneously nowadays and for future
applications. New demands are additionally being made on reflow machinery and processes by the transition to lead-free manufacturing processes. This situation particularly applies to issues such as the parallelism of conveyor rails as well as process gas cleaning.
The current demands made on polymer electronics,electro-optical assemblies and high-temperature electronics require a new
technology for making the soldered joints,which allows the solder paste deposit to be heated stronger and faster than the temperature-sensitive components and substrates. This new technology,which is particularly interesting for the production of
RF-ID tags or „Smart? labels,combines a simultaneous soldering process (jointing of all components at the same time) with
selective heating (the soldered joints can be heated up more than the substrate and components). Such a process combines
convectional reflow soldering and microwave heating. A joint project called „MICROFLOW?,which is being funded by BMBF (the German Federal Ministry of Education and Research),is intended to develop a combined reflow soldering machine.
This paper highlights the first results of practical research from the MICROFLOW project. It also examines in detail all of the issues concerning lead-free soldering techniques in relation to the machine.

Increased functionality and smaller devices are significant drivers in innovative packaging designs. One of the newer package types to be introduced into the market place in the past few years is the package on package (PoP) devices. While packaging houses have been stacking die within memory and other packages for several years,this methodology is subject to known good die issues and other challenges that can drive up cost. In addition,this limits the designer on what functionality can be “stacked”,since these come packaged together in a single unit. Stacking packages offers significant advantages from a design standpoint. As long as the pad designs are compatible,different device types can be stacked allowing for more versatility in the design and the assembly. On the other hand,assembling these devices on a standard SMT line can present challenges. Some assemblers purchase or acquire these devices pre-assembled,but the trend is towards assembling these on the printed circuit board (PCB) during a standard SMT process. Once solder paste is printed on the PCB and the first level component is placed,the attachment methodology of the second level device is not as clear. Therefore,in order to reflow these all in one pass alternative measures need to be investigated.
In this paper we compare the process conditions and yield achieved when assembling package on package devices utilizing different materials and methodologies. In all cases the devices were Pb-free devices with solder paste used for the bottom package. The material and process and materials were varied for the top package. The materials used for the top package assembly included tacky flux,solder paste,and an epoxy flux system. Once assembled the devices were tested for electrical yield,solder joint metallurgy integrity,and standoff height.

The motivation for developing higher density IC packaging continues to be the personal entertainment and the portable
handset markets. Consumers? expectations are that each new generation of products be smaller,thinner,lighter in weight and
furnish greater functionality. The challenge electronic manufacturers face when competing in the global marketplace is to
offer a product that will meet all functional and performance expectations without increasing product cost. To address the
need for more functionality without increasing product size,a number of companies have adapted various forms of multiple die
3D packaging. A majority of these early,multiple function devices relied on the sequential stacking of die elements onto a single substrate interposer using a conventional wire-bond process. Because the wire-bonding of multiple tiers of uncased die is rather specialized and the die used may have had relatively poor wafer-level yields,overall manufacturing yield of the stacked-die packaged devices have not always met acceptable levels.
The information presented in this paper focuses on the stringent qualification requirements for a very-thin,vertically configure dµPILR package developed for high-volume memory and mixed function products. A key advantage of this innovative package-on-package (PoP) configuration is that each layer of the package can be pre-tested before joining. This capability greatly improves the overall manufacturing yield and the functionality of the final package assembly is assured. The material developed for this program will outline current environmental expectations for multiple function packaging for hand-held and portable electronic applications and detail the qualification test results for a number of memory variations using this unique,vertically-stacked package technology.

The continued drive for more compact and lightweight handheld mobile devices has forcibly pushed the electronics assembly industry to look for novel packaging and assembly technologies. One of the newest advances in recent years is for semiconductors to be stacked,one on top of the other,in a single package. This die stacking allows system designers to take advantage of the often more readily available “Z” axis of the cubic area while saving on the valuable “X” and “Y” square dimensional space on PCB layouts.
Stacking chips in a package is one method to realize this concept,forming the Stacked Chip Scale Package (SCSP) (Figure 1) and the Integrated Devices Circuit (IDC) manufacturers are responsible for building these units.
Figure 1. Stacked Chip Scale Package
As can be seen from the above diagram,this package is simply another area array package to the PCB assembly house,which requires no changes to existing assembly technology.
This paper focuses on a newer alternative to stacked chip scale packages. This technology involves the novel design of a bottom package containing a high performance logic device to receive a mating top package typically containing high capacity or combination memory devices to form the PoP structure (Figure 2). The key difference here is from the assembly perspective,as the assembler will inherit the assembly process. The driver in adopting this application is cost-effective miniaturization for logic & memory integration.

This paper discusses laser micromachining of thin films. In particular,recent developments on high capacitance,large area,thin,flexible/rollable embedded capacitors are highlighted. A variety of flexible nanocomposite thin films ranging from 2 microns to 25 microns thick were processed on copper or organic substrates by large area (330 mm × 470 mm,or 495 mm X 607 mm) liquid coating processes. SEM micrographs showed uniform particle distribution in the coatings. Nanocomposites resulted in high capacitance density (10-100 nF/inch2) and low loss (0.02-0.04) at 1 MHz. The remarkably increased flexibility of the nanocomposite is due to uniform mixing of nanoparticles in the polymer matrix,resulting in an improved polymer-ceramic interface. BaTiO3-epoxy polymer nanocomposites modified with nanomaterials were also fabricated and were investigated with SEM analysis. Capacitance density of nanomaterial-modified films was increased up to 500 nF/inch2,about 5-10 times higher than BaTiO3-epoxy nanocomposites. A frequency-tripled Nd:YAG laser operating at a wavelength of 355 nm was used for the micromachining study. The micromachining was used to generate arrays of variable-thickness capacitors from the nanocomposites. The resultant thickness of the capacitors depends on the number of laser pulses applied. Laser micromachining was also used to make discrete capacitors from a capacitance layer. In the case of sol-gel thin films,micromachining results in various surface morphologies. It can make a sharp step,cavity-based wavy structure,or can make individual capacitors by complete ablation. Altogether,this is a new direction for development of multifunctional embedded capacitors.