This paper will present seven different materials used for the production of both wave solder and reflow solder pallets. The goal of this study will be for the purpose of depicting machining capabilities for depth,wall thickness,and
accuracy of machining for each of the seven materials presented. Additionally,a lead free wave pallet (used for a high running Printed Circuit Board (PCB) product) will be built out of each of the materials being tested. Each pallet will be
tested for the purpose of showing long-term wear effects over multiple heat cycle run times; monitoring pallet flatness for heat warping of the pallet; wall thickness changes; and,overall changes in surface condition. For the purposes of
this study,each of the materials used is listed in terms of basic material properties.

As the electronics assembly industry adjusts to building boards with 0201 components,the next level of shrinkage for chip components is just around the corner with the emergence of 01005s. A key objective of this work is to demonstrate assembly success using common 0201 build parameters of Type 3 solder paste and 4-mil stencil thickness. Stencil artwork strategies are implemented across 27 different pad designs to determine how assembly yield is influenced by aperture area ratio,component termination overlap level in paste,and tolerance to stencil defined misregistration levels. A pad design of 9 mils
wide by 11 mils long and separated from the opposite pad by 6 mils is recommended when printed with 9 mil wide by 10 mil long apertures to achieve acceptable print quality and high assembly yield results. A direct comparison of tombstone ratios for 0201 and 01005 resistor components assembled together shows that 01005s are more stable across a variety of profile atmospheres compared to 0201s.

For some years now,an area ratio of 0.66 or greater has been the criterion for stencil apertures to achieve acceptable volume control in the printed solder paste “brick,” for small apertures Meeting this criterion,in the stencil printing process,has been a constant concern as the volume consistency of the solder paste brick is among the most critical metrics in determining high yields in the assembly process.
With the advent of 0201 and most recently 01005 passives components,meeting the area ratio target of 0.66 is a challenging task; especially with a 5 mil thick stencil and a Type 3 powder solder paste. These tiny passive technologies and minimalist IC packages like 0.4mm CSPs have created a need to re-evaluate the area ratio criterion of 0.66 and other related issues. In light of this need,we developed a series of designed experiments (DOEs) evaluating Type 3 and Type 4 solder pastes,varying aperture designs for 0201,01005 and 0.4 mm CSPs,and 3 and 4 mil thick laser cut and E-Fab stencils. In these experiments we determined optimum print parameters for the various combinations of pastes,components,aperture design,and stencil fabrication mentioned above. Our results also suggested new criteria for area ratios. We believe that with the concurrent implementation of lead-free assembly,this work could not be timelier.

During the development of a new medical imaging system,via quality was identified as a potentially source of infantile failures. Premature via failures were precipitated in a critical 14 layer board,specifically in the 0.8 mm BGA vias with an
aspect ratio of approximately 9:1. Failure analysis indicated two dominant failure mechanisms: dry film lock-in,and drill debris in the via barrel causing insufficient plating of the via sidewall. Dry-film lock-in was corrected by process control
improvements at the fab supplier. The fab material was identified as a major driver in the presence of drill debris in the via barrel.
To address these infant mortality issues and to demonstrate long term via reliability,IST testing was identified as an industry recognized tool to quickly assess fab reliability. Three parameters were identified as key variables in fine-pitch via quality and reliability: fab resin material,inclusion of non-functional pads (NFP),and type of drill machine at the fab supplier. A DOE was developed to understand the influence of these factors on overall via reliability. The following conclusions were observed. The lower CTE fab material outperformed the other fab materials in mean cycles to failure (CTF). In addition,an interesting result with NFPs was found. Contradictory to industry recommendations,the
presence of NFPs actually improved the mean CTF for the same material and process. The drill machine had little to no influence on CTF for the same material and design. In addition,at the lead-free preconditioning temperature,separation of the glass fiber bundles was observed in most of the materials tested. An understanding of this phenomenon and the other failure modes is critical to developing a robust lead-free fab.

This paper continues work by Sun Microsystems and the University of Maryland,CALCE[1] to predict plated through via life using laminate material properties,plated copper material properties,and the physical via geometry to model via life. The new method presented in this paper uses non-linear laminate material properties and a damage-fatigue model to predict the accumulated damage to a plated through via as it is thermally cycled through assembly and field life conditions.
Copper is a ductile metal so it is possible to construct a Log-Stress versus Log-Life plot that follows an Inverse Power Law (IPL).[2] The key to doing a Log-Stress versus Log-Life plot is developing the relationship of stress versus temperature of the laminate material. Use of a Log-Stress versus Log-Life plot allows increased testing efficiency since you can perform an accurate life analysis by testing at only the high and low temperature extremes. Once the Log-S versus Log-N plot is
constructed,it is possible to predict plated through via life over a wide range of temperatures. For this paper,we will use thermal cycle to failure test data obtained from Interconnect Stress Test (IST),[3] but the analytical methods developed apply equally to other thermal cycle methods like Highly Accelerated Thermal Shock (HATS)[4] and Air-to-Air Thermal Shock (AATS).
Last,a Finite Element Model simulation is conducted that uses material properties that are easy to obtain and is then validated against the large database from IST testing at multiple temperatures. Once the Finite Element Model validation is complete,the model is used to make assembly and field life predictions for two case studies involving thick,complex printed wiring boards.

With the implementation of RoHS directives,pure tin plating is replacing lead in the tin-alloy used in the printed circuit boards and other worldwide electronics. Although use of tin provides a safer environment for electronic manufacturers and
helps meet the regulatory requirements,it is known to form tin whiskers,odd shape eruptions and dendrites that cause printed circuit boards or devices to fail. Research has been ongoing for decades in an attempt to understand and control the whisker formation with limited successes to date. Because of the RoHS requirements,efforts to find an appropriate solution to the tin whisker problem have increased significantly in the past couple of years. This paper reviews various options and presents a practical solution utilizing Parylene coating technology for suppressing the formation of metallic whiskers,OSEs and dendrites.
Parylenes are solvent and catalyst-free thin organic coatings that offer solutions to many existing protective,packaging and reliability challenges of electronic industry in part because of their excellent electrical,mechanical and barrier properties and chemical inertness. In addition,Parylenes truly conform to the parts due to their molecular level deposition characteristics. It has been observed that Parylene conformal coatings are more suitable for suppressing metallic whiskers than other conformal coatings or other proposed solutions.
This paper also highlights some key attributes of a recently commercialized Parylene HT that help mitigate the risk of metallic whiskers even further,particularly for electronics or PCBs used at higher temperature and high frequencies. Parylene HT offers long-term thermal stability at temperature exposures in excess of 350oC.

Our industry is slowly coming to the realization that many fluxes containing low molecular weight carboxylic acids cannot be adequately tested for surface insulation resistance and electrochemical migration at high temperatures. This paper describes the use of thermal gravimetric analysis (TGA) to look at the sublimation of succinic acid and glutaric acid from a paste flux formulation.

The widespread use of SAC-based (SnAgCu) lead-free solder paste drives the industry toward a smaller process window. This is due to higher reflow temperatures as well as the limited thermal resistance of the current generation of electronic components. Furthermore,differences in the wetting performance of Pb-free surfaces not only require reduced variation in all process steps,but also in the soldering materials.
SPC data has shown that the solder paste printing process is the primary source of soldering defects in SMT assembly. Consequently,verification of the specified printing properties of solder paste is of paramount importance in the pursuit of
higher quality goals and higher overall yields. Process variations such as temperature fluctuations in the printing area,changing printing speeds,and varying stencil life have been recognized as important factors in the characterization of solder paste.
In recent years,quality management standards such as ISO/TS 16949 have been driving the development of a reproducible rheometric methodology to characterize and quantify the aforementioned solder paste properties.
In the course of this development,we have learned that the thixotropic history of a solder paste has a major impact on the repeatability and reproducibility of its rheometric characterization. This paper describes the differences in this respect between the various measuring principles such as the spindle,spiral pump and plate/plate method. It also introduces the development and implementation of a sample preparation method to reduce the impact of the thixotropy of a solder paste in conjunction with enhanced plate/plate rheometry.

Wafer bumping using thin electroformed nickel stencils with ultra fine powder solder paste continues to gain popularity as a cost effective alternative to ball drop and electroplated technologies. This paper describes the results of an extensive study involving 120,000 bumps conducted using eutectic and lead free water soluble wafer bumping solder pastes to achieve high bump height to pitch ratios down to 150 micron pitch. The printing process,stencil designs and bump measurement methods are described in full detail. Additionally,results from the most recent work on a 200mm test wafer with pitches down to 100 microns defining the effect of various squeegee materials on bump height for lead free solder pastes is discussed. Lead free wafer bumping solder pastes with powder types 5,6,7 & 8 are also compared and contrasted for their bump height capability to bump pitches below 200 microns. In addition to the material deposition tools and techniques,the reflow and cleaning processes are described. Finally,preliminary results on UBM pad size effects on bump height are presented.

A family of SACX alloys has been developed with significant improvement in drop test performance on NiAu surface finish. Dopants such as Mn,Bi,Ti,Ce,and to a less extent Y for SAC105 have been observed to show very positive effect when used alone or in combination,with Mn exhibiting the most profound effect. SAC+Mn outperformed not only SAC alloys,but also Sn63,thus completely altered the shaky position of SAC systems caused by fragility of solder joints. The melting and intermetallic formation properties are not affected by the dopants. Mn tends to migrate toward MC and accumulate near IMC layer in the form of MnSn2 particles. Thermal aging results in further improvement of drop test performance.A family of SACX alloys has been developed with significant improvement in drop test performance on NiAu surface finish. Dopants such as Mn,Bi,Ti,Ce,and to a less extent Y for SAC105 have been observed to show very positive effect when used alone or in combination,with Mn exhibiting the most profound effect. SAC+Mn outperformed not only SAC alloys,but also Sn63,thus completely altered the shaky position of SAC systems caused by fragility of solder
joints. The melting and intermetallic formation properties are not affected by the dopants. Mn tends to migrate toward IMC and accumulate near IMC layer in the form of MnSn2 particles. Thermal aging results in further improvement of drop test performance.