The global electronics industry is exhibiting a widespread and growing interest in the technology of embedded passives. This interest can be attributed to three primary benefits. First,embedded passives have far less parasitic inductance than discrete components,which enables electrical performance advantages in high speed digital applications. Second,embedding saves surface real estate,which allows for board size reductions. Third,the incremental cost of embedding additional passive components is typically negligible,which suggests the potential for system cost reduction in designs with high passive component counts.
The material we describe here is a high performance embedded passive material intended for embedded capacitor applications. It is a copper-clad laminate which utilizes an ultra-thin,high K-value dielectric material between the copper planes to deliver a capacitance density of over 6 nF/in2.
This presentation will focus on this laminate material and how it can be used to improve electrical performance and reduce board size (by replacing discrete capacitors),and will also address the impact on PCB reliability and system cost.

New interconnect technologies continue to shrink feature size,increase routing complexity and component density in multilayer rigid and rigid-flex printed circuits. Printed circuit fabricators have choices on the technology required to build the multilayer circuits based on the level of the technology required. One innovative technology is sequential lamination where multilayer boards are formed by laminating together plated double-sided or multilayers with blind and buried via interconnections. The sequential lamination manufacturing technique can yield even more significant benefits in performance and circuit processing when combined with embedded resistor features within the printed board. Embedded passive technology allows the resistors to be placed on the same layer as the routed traces reducing the need for microvias. This technology also enables resistors to be placed at an optimum location to reduce the inductance impact of pads,stubs,and coupling. The sequential lamination process in combination with thin film embedded resistors requires a different processing
sequence than conventional multilayer manufacturing with thin film embedded resistors. Materials for embedded resistor can be either stand-alone resistor foil or a resistor laminate. For sequential lamination applications copper foil with a resistive alloy is preferred rather than a resistor laminate material. The copper/resistor foil has very low profile,and small circuit features can be achieved. Consequently,resistors can be fabricated in signal or power ground layers with multiple resistor values and good finished tolerances. The resistor alloys are robust and have low thermal coefficient of resistivity. The resistors maintain their initial values and reliability through the multiple lamination steps and subsequent thermal excursions required by the sequential lamination process.

New interconnect technologies continue to shrink feature size,increase routing complexity and component density in multilayer rigid and rigid-flex printed circuits. Printed circuit fabricators have choices on the technology required to build the multilayer circuits based on the level of the technology required. One innovative technology is sequential lamination where multilayer boards are formed by laminating together plated double-sided or multilayers with blind and buried via interconnections. The sequential lamination manufacturing technique can yield even more significant benefits in performance and circuit processing when combined with embedded resistor features within the printed board. Embedded passive technology allows the resistors to be placed on the same layer as the routed traces reducing the need for microvias. This technology also enables resistors to be placed at an optimum location to reduce the inductance impact of pads,stubs,and coupling. The sequential lamination process in combination with thin film embedded resistors requires a different processing
sequence than conventional multilayer manufacturing with thin film embedded resistors. Materials for embedded resistor can be either stand-alone resistor foil or a resistor laminate. For sequential lamination applications copper foil with a resistive alloy is preferred rather than a resistor laminate material. The copper/resistor foil has very low profile,and small circuit features can be achieved. Consequently,resistors can be fabricated in signal or power ground layers with multiple resistor values and good finished tolerances. The resistor alloys are robust and have low thermal coefficient of resistivity. The resistors maintain their initial values and reliability through the multiple lamination steps and subsequent thermal excursions required by the sequential lamination process.

The reliability of aged and repaired lead-free and mixed lead-free/lead-based solder interconnects is an important issue for electronic equipment manufacturers. As a result of the global transition away from lead driven by government legislation and market pressure,maintained lead-based electronic equipment may need to be repaired with lead-free parts and materials
due to improper labeling or inability to obtain proper replacement materials. An experimental study to examine the reliability of aged and repaired solder interconnects was conducted. Test specimens included thermally aged and non-aged lead-free and lead-based printed wiring assemblies with surface- mount components,including ball grid arrays (BGAs),leadless resistors,and quad flat packages (QFPs). Test specimens were subjected to aging and repair where lead-free and lead-based components and materials were intentionally mixed. Temperature cycle loading was used to examine the reliability of the solder interconnects. Test results show that thermal aging is more detrimental to lead-free solder interconnects than to leadbased interconnects for PBGAs. Further,the failure distribution of the lead-free assembled PBGAs was found to be wider
than the distribution of the lead-based failures.

The reliability of aged and repaired lead-free and mixed lead-free/lead-based solder interconnects is an important issue for electronic equipment manufacturers. As a result of the global transition away from lead driven by government legislation and market pressure,maintained lead-based electronic equipment may need to be repaired with lead-free parts and materials
due to improper labeling or inability to obtain proper replacement materials. An experimental study to examine the reliability of aged and repaired solder interconnects was conducted. Test specimens included thermally aged and non-aged lead-free and lead-based printed wiring assemblies with surface- mount components,including ball grid arrays (BGAs),leadless resistors,and quad flat packages (QFPs). Test specimens were subjected to aging and repair where lead-free and lead-based components and materials were intentionally mixed. Temperature cycle loading was used to examine the reliability of the solder interconnects. Test results show that thermal aging is more detrimental to lead-free solder interconnects than to leadbased interconnects for PBGAs. Further,the failure distribution of the lead-free assembled PBGAs was found to be wider
than the distribution of the lead-based failures.

The purpose of this program was to evaluate the solder joint reliability,using the IPC-9701 standard as a guideline,of PCBAs that were assembled with conventional leaded and ROHS compliant lead free processes and to evaluate the
capabilities of multiple PCBA assembly houses. 6 sample groups of 26 samples each from 3 different suppliers were subjected to a full qualification plan,SEM,cross-sectional imaging and EDX analysis. The groups consisted of lead free
(SAC) test coupons and standard leaded (SnPb) test coupons. The test coupons were populated with surface mount daisy chained dummy components. The component finishes were SnCu and the board finishes were immersion Ag. The coupons were subjected to mechanical strength (lead pull testing,vibration and impact tests),long term reliability (damp heat,temperature cycling and whisker growth tests) and solder joint quality (cross-sectioning,SEM imaging and EDX of
components). The test results were analyzed to compare the capabilities of the 3 PCBA assembly houses and to evaluate the relative differences between the conventional leaded and ROHS compliant lead free processes.

During the solder reflow processes many reactions occur. There is the reduction of oxides on the metal surfaces,metal dissolution,wetting to different surfaces,and intermetallic compound formation between the bulk solder and the metals being soldering. The intermetallic compound (IMC) is necessary for good solder interconnections. However an excessive IMC may raise solder joint reliability concerns due to its brittle nature. Therefore,a proper IMC thickness is critical for solder joint integrity. The amount of IMC formation is a function of reflow time (Time above Liquidus) and temperature (Peak Temperature). In a Pb-free process,both reflow temperature and time can increase,possibly increasing the thickness of intermetallic formed. During thermal shock,thermal aging or thermal cycling,IMC will grow as well.
The purpose of this study was to investigate the effects of reflow time,reflow peak temperature,and thermal shock on IMC thickness. Four different sizes of chip resistor (1206,0805,0603,and 0402) were attached to OSP surface finish boards with Sn-3.0Ag-0.5Cu (SAC305) solder alloy paste. Traditional Sn-37Pb eutectic solder paste was used as the control in this study. Nine reflow profiles for SAC 305 and nine reflow profiles for SnPb were developed with three levels of peak temperature (12°C,22°C,and 32°C above solder liquidus temperature,or 230°C,240°C,and 250°C for SAC 305; and 195°C,205°C,and 215°C for SnPb) and three levels of time above solder liquidus temperature (30 sec.,60 sec.,and 90 sec.). Half of the test vehicles were then subjected to air-to-air thermal shock conditioning from -40 to 125°C for 500 cycles. IMC thickness was measured using Scanning Electron Microscopy (SEM) with Energy Dispersive Spectroscopy (EDS). The results show that the IMC thickness increases with higher reflow peak temperature and longer time above liquidus together with thermal shock testing.

The pressure on manufacturers of electronic devices to continually reduce the cost of products has continued,despite the challenges of higher cost lead-free production. In many cases assemblers have been forced to attempt to build the new leadfree assemblies using the same equipment,and without increasing the cost of components and laminates. While many manufacturers have considered reliability data from materials suppliers and independent test houses,many have not considered the reliability impact on their own particular assemblies. This paper discusses the potential effect on the reliability of a lead-free assembly in relation to the laminate used and the process parameters.

The pressure on manufacturers of electronic devices to continually reduce the cost of products has continued,despite the challenges of higher cost lead-free production. In many cases assemblers have been forced to attempt to build the new leadfree assemblies using the same equipment,and without increasing the cost of components and laminates. While many manufacturers have considered reliability data from materials suppliers and independent test houses,many have not considered the reliability impact on their own particular assemblies. This paper discusses the potential effect on the reliability of a lead-free assembly in relation to the laminate used and the process parameters.

Work on assisting China's Ministry of Information Industry (MII) to assess the performance of a solder paste using the China alloy Sn3.0Ag0.5Cu0.019Ce (SACCe) was completed. Two Indium fluxes were incorporated as controls. Ce showed no effect on paste printing,slump,or probe testability on flux residue for SAC system. The difference between SACCe and SAC mainly resides in soldering. SACCe exhibits a slightly lower solder beading rate,comparable voiding,a considerably higher tombstoning rate,and is more prone to oxidation hence wets poorer under harsh reflow conditions. No difference in IMC structure or growth rate can be discerned for joints formed on either Cu or NiAu. Overall,China alloy is acceptable in reflow applications. The paste made from the China alloy exhibits a poorer print and a considerably narrower reflow window than
the two paste controls.