The implementation of both RoHS and WEEE Directives by the European Union (EU) mandate that electrical and electronic
products put on the market within the EU shall contain restrictive amounts of lead. Bright tin-lead plating has been used for
decades for electronic components and suitable alternatives have been investigated. One candidate that appears to meet most
of the required criteria,such as corrosion resistance,solderability and low cost,is pure tin,however,the use of pure tin
inevitably raises the specter of tin whiskers. The mechanism of tin whisker growth,despite the very significant amount of
research effort devoted to investigating this phenomenon,remains incomplete. It is understood that compressive stress,
introduced into the tin deposit and sometimes inherent within it,is a significant cause of whiskering. Likewise,methods of
whisker growth mitigation such as the use of a nickel pre-plate are also well documented. On reviewing the literature it
quickly becomes clear that there is a strong bias towards the use of matte tin plating processes. This is at least partially
attributable to some basic characteristics of matte and bright processes. Matte tin electrolytes are generally less chemically
“complex” than bright ones,and the resultant deposits normally contain less organic materials. Our recent research has
characterized the whisker growth propensity of multiple matte and bright plating formulations utilizing recently accepted
whisker test methods. We have found that the choice of organic additives used in both matte and bright tin electrolytes can
have a profound effect on their respective tendency to initiate whisker growth. We will outline our whisker results in detail
and examine key process and coating characteristics which may explain this preferred whisker performance.

A comparison study was carried out with Sn3.5Ag and Sn3.8Ag0.7Cu solder balls on Ball Grid Array (BGA) components
with Cu/Ni/Au pad finishing. This study shows that Sn3.5Ag C5 solder system performs better than Sn3.8Ag0.7Cu in terms
of joint strength and brittle mode failure. Experimental works were carried out to observe the melting properties of the solder
alloys by Differential Scanning Calorimetry (DSC). Solder ball shear and cold pull strength after ball attach,high
temperature storage (HTS) and multiple reflow were measured by Dage to gauge the solder joint strength and intermettalic
compound (IMC) thicknesses were measured after cross-sectioning,. Drop Tests were done per ASE & Freescale methods to
study the solder joint performance against vibration and impact shock. Liquid-liquid thermal shock was done to assess Board
Level Reliability. A comprehensive study was done using SEM and EDX to study the effect of microstructure and interface
intermetallics of both solder system at ambient,HTS at 150ºC for 168 hours and 6x multiple reflow towards the joint
integrity. Microstructure studies on SnAg solder reveals that formation of rod shape Ag3Sn IMC distributed across the solder
surface helps to act as dispersion hardening that increases the mechanical strength for the Sn3.5Ag solder. EDX analysis
confirmed that in SnAgCu solder/Ni interface,Cu-rich IMC formed on top of the Ni-rich IMC. For SnAg system,only Nirich
IMC is found. Therefore,it is highly suspected that the presence of Cu-rich IMC posed a detrimental effect on the joint
strength and tends to cause brittle joint failure. Both of the effect is then showed in ball pull result that after HTS,SnAgCu
solder has 99.5% brittle mode failure,where SnAg solder has 0%. This result correlates with missing ball responses after
packing drop tests as well as liquid-liquid thermal shock result. Thus,despite having 4ºC higher melting temperature than
SnAgCu,improvement on SnAg was obtained using the SnAgCu reflow profile. Thus,SnAg eutectic solder is a potential
candidate for lead-free solder joint improvement for overall lead-free package robustness.

Many existing and some new laminate material test methods that are being proven useful for determining a laminate material's suitability for use in higher temperature lead-free assembly processing. Most notable of these is the new "Laminate Material Temperature of Decomposition" test method (IPC TM-650,2.4.24.6) which will be listed as a parameter for the more thermally robust material classifications listed in the new IPC-4101B,Specification for Base Materials for Rigid and Multilayer Printed Boards. However many OEMs are finding that larger,thicker multilayer boards (MLBs) are more prone to delaminate during higher temperature assembly processing and rework.

Several large OEMs (IBM,HP,CISCO,etc.) have been working together as a group to develop a new test method for evaluating the thermal robustness of multilayer boards. This test would to be primarily used for initial qualification and occasional on-going process/material monitoring. After developing a product history and a well populated database,this could lead to the specification of a minimum requirement for acceptance. This new multilayer board (MLB) delamination and laminate integrity test method should detect improper press lamination (cycle time too short or peak temperature not reached in center of stack-up/press opening),dry weave or excessive voids between fibers within a glass reinforcement bundle,delamination,and/or poor quality prepreg in prepreg layers. This "MLB Laminate Integrity" test should also detect "tail cracks" and "eyebrow" type localized delamination
(example: cracks in annular pad area of blind vias). Similar to T260 testing,labs should use the same "bumps" and starting points for determining test failure. A standard test board / test coupon containing the worst case design features should be used for using this new "MLB Laminate Integrity" test method to evaluate laminate materials.

Participants in this effort are needed to provide "good" multilayer boards and "bad" multilayer boards for a given preheat profile and peak solder reflow temperature. These will be used to evaluate the sensitivity of the new test method using a range of test parameters. Both the IPC and iNEMI are considering forming subcommittees that may take on this project of developing an industry standard MLB Delamination Test Method.

The debate on the effect of voiding on BGA reliability has continued for years. Many PWB assemblers strive to minimize
voiding,particularly with the advent of lead-free processing and in fine feature area array devices. Although solder pastes
have been designed to minimize voiding,and processing guidelines exist to mitigate void formation during reflow processing,
the presence of a microvia in a PWB pad can contribute significantly to void formation. It is believed that the depression in
the pad caused by the microvia traps air during the stencil printing process,and the air cannot fully escape during reflow.
A process of filling the vias with copper at the board fabrication phase,thereby eliminating the depression that contributes to
voids,was tested for its effectiveness in void mitigation during assembly. The test compares the voiding results of filled vias
with those of unfilled vias and flat pads with no vias at all. The test vehicle and methods,as well as the results of the tests are
presented and discussed in detail.

Nitrogen inerting has been widely reported to reduce defects in lead-free reflow soldering. However,many solder pastes
available claim that they either do not need nitrogen or work equally well in air. While some of these pastes can produce an
acceptable joint quality,they are very susceptible to any narrowing of the process window and some cannot produce high
quality joints even under the most advantageous conditions.
At a leading consumer electronics manufacturer in Asia,three pastes from major producers were compared. Commercial
boards were reflowed in air,and in nitrogen at two purity levels. The boards were then visually inspected for joint quality
using the manufacturer’s standards. The results showed that even the joint quality produced by the best paste could be
improved using nitrogen and the highest nitrogen purity tested could bring the worst paste up to the standard of the best.

(not available)

The industry is in full transition towards lead-free assembly. Due to the different physical,mechanical and chemical
properties of lead-free solder alloys,transitioning lead-free soldering without creating defects or reducing yields has been a
challenge to some.
This paper summarizes the findings coming from customer experiences and details ways these defects may be caused and
how to prevent additional costs due to added repairs or reduction in production yields. The alloys of focus are the popular tinsilver-
copper (SAC305); this solder has experienced the most use in the industry at this time.
The present experiences with lead-free solders seem to indicate that a properly selected alloy,flux chemistry,equipment
selection and process optimization can give reliable assemblies with lead-free SAC. This paper will focus on the SMT
process although similar analysis has been done at the customer level with wave,selective and hand-assembly.

Although in Europe and North America wave soldering is widely regarded as a process that is being rendered obsolete by reflow processes the proliferation of electronic circuitry has more than compensated for that trend. The reality is that globally there are probably more wave soldering machines in operation now than there have ever been. Wave soldering provides a reliable method of affecting a large number of joints quickly and cost effectively and can handle a wide range of surface mount as well as through whole components. With good equipment,good soldering materials and a printed board assembly properly designed for wave soldering zero defects is a realistically achievable target. Because the 2001 legislation that drove the move to lead free in the Japanese market was directed at consumer electronics where wave soldering was the dominant assembly method experience with the process extends back to 1999. In the seven years since mass production by lead-free wave soldering began,and as the number of lead-free lines in operation grew to the thousands a considerable database of experience has been accumulated. Although regarded as a simple process compared with reflow soldering wave soldering has its own unique set of challenges. One distinguishing feature of the process is,for example,the need to manage up to 1000 lb of molten solder and that has economic as well as technical considerations. In this paper the authors report the lesson’s learned during company’s experience of wave soldering in commercial mass production since 1999 and explain how the data collected can be applied to the design and operation of wave soldering equipment and the assemblies soldered on that equipment to achieve reliable solder joints cost effectively.

There are various C4 (Controlled Collapse Chip Connection) solder bumping technologies used in volume production. These
include electroplating,solder paste printing,evaporation and the direct attach of preformed solder spheres. FlipChip in
Package (FCiP) demands many small bumps on tight pitch whereas Wafer Level Chip Scale Package (WLCSP) typically
requires much larger solder bumps. All these technologies have limitations for fine pitch bumping. The most commonly used
method of generating fine-pitch solder bumps is by electroplating the solder. This process can be costly,especially when it
comes to lead-free solder alloys. These challenges in the transition to lead-free solder bumping has led the European Union to
grant exemptions from the ban of lead in certain solder bumping applications. However,the second level assembly cost of
Lead-Free and Leaded line in parallel is driving for a commonality to move to lead-free for the entire industry.
The terminal metals process forms C4 (Controlled Collapse Chip Connection) solder bumps and the associated bump limiting
metallurgy pads on the surface of silicon integrated circuit wafers. The Bump Limiting Metallurgy (BLM) or Under Bump
Mettalurgy (UBM) pads are located between each solder bump and the surface of the wafer. Typically,the wafers contain a
replicating pattern of chips / die. The UBM and C4 solder bumps provide an electrical and mechanical connection for the
chip to its first level package
C4NP (C4-New Process) is a novel solder bumping technology developed by IBM and commercialized by Suss MicroTec.
C4NP addresses the limitations of existing bumping technologies by enabling low-cost,fine pitch bumping using a variety of
solder alloys. C4NP is a solder transfer technology where molten solder is injected into pre-fabricated and reusable glass
templates (molds). Mold and wafer are brought into close proximity and solder bumps are transferred onto the entire 300mm
(or smaller) wafer in a single process step. C4NP technology is capable of fine pitch bumping while offering the same alloy
selection flexibility as solder paste printing. The simplicity of the C4NP process makes it a low cost solution for both,finepitch
FC in package as well as large pitch / large ball WLCSP bumping applications.
This paper provides a summary of manufacturing and reliability results of C4NP Lead-Free bumps and compares it with the
Electroplated High Lead solder bumped high-end logic devices. We also discuss the relevant process equipment technology
and the requirements to run a HVM (high volume manufacturing) C4NP process. We will also describe the C4NP
manufacturing cost model and elaborates on the cost comparison to alternative bumping techniques. The data in this paper is
provided by IBM’s packaging operation at the Hudson Valley Research Park in East Fishkill,NY

A designed experiment evaluated the influence of several variables on visual appearance and strength of Pb-free solder joints.
Components,with leads finished with nickel-palladium-gold (NiPdAu),were used from Texas Instruments (TI) and two
other integrated circuit suppliers. Pb-free solder paste used was tin-silver-copper (SnAgCu) alloy. Variables were printed
wiring board (PWB) pad size/stencil aperture (the pad finish was consistent; electroless Ni/immersion Au),reflow
atmosphere,reflow temperature,Pd thickness in the NiPdAu finish,and thermal aging. Height of solder wetting to
component lead sides was measured for both ceramic plate and PWB soldering. A third response was solder joint strength; a
“lead pull” test determined the maximum force needed to pull the component lead from the PWB.
This paper presents a statistical analysis of the designed experiment. Reflow atmosphere and pad size/stencil aperture have
the greatest contribution to the heights of lead side wetting. Reflow temperature,palladium thickness,and preconditioning
had very little impact on side wetting height. For lead pull,variance in the data was relatively small and the factors tested
had little impact on lead pull results.