For the purpose of mask-less manufacturing for Printed Circuit Board (PCB),a new process using electrophotography
technology,principle of copy machines,has been proposed and evaluated. Wiring patterns can be formed by electroless
plating on the seeding patterns printed with the novel toner that is made of thermosetting resin and metal fine particles.
Insulating layer can be also patterned by printing with resin toner. To build up multi-layered structure of PCB,these two
processes are repeated in turns. This new method has some big potential to simplify manufacturing process for wiring and
reduce the cost of PCB.
The first technical issues were to control electrostatic charge of toner including metal particles and to get enough quality of
printed seeding patterns for electroless plating. We started to develop the novel toner from investigating about the relationship
between metal contents,electrostatic charge of toner,and plating ability. And it was established that new wiring process using
electrophotography is available for PCB tracing. Similarly,insulating single slayer and multi-layered structure were formed
by new process and appraised. Additionally,some trial samples by this new process were evaluated by some basic reliability
tests. For demonstration,flip chip assembly was carried out and antenna substrates for RFID tags were fabricated.

In order to satisfy the ever-increasing demand for smaller and lighter electronic devices,a drastic miniaturization is making
rapid progresses for even circuit features on printed wiring boards (PWBs). Compared with a subtractive method which is
traditional PWBs manufacturing process,a semi-additive method is regarded as a more favorable process for these
miniaturization requirements,whereas it has a problem that surface insulation reliability deteriorates due to palladium (Pd)
catalyst remaining on insulating resin between conductors. In order to overcome this drawback,various methods have been
attempted to remove Pd catalyst so far,but they have some sort of problem and it is still difficult to obtain satisfactory results.
Now,novel chemical solution,a remover for Pd catalyst residue,has been developed to deal with the problems. This paper
demonstrates a comparative study of the newly developed remover and conventional methods as for the surface insulation
reliability. It is finally confirmed how this Pd remover contributes to the successful materialization of high surface insulation
reliability in fine-line PWBs fabricated by the semi-additive process.

We have developed a new resin-coated-foil (RCF) material named MCF-HD-45 to be embedded in PWBs to constitute
capacitors. The material is composed of a thermosetting resin and a high dielectric constant (Dk) filler. The filler has a
multimodal size distribution to attain high loading; a specific surfactant is also essential to preserve the stability of filler
dispersion in varnish. These technologies give this material a high Dk of 45 and excellent reliability. In this paper are
described the test results for the material applied to a power amplifier module and a low pass filter of cellular phones,as well
as the benefit of the database for high frequency circuit simulation.

In this study,we developed the thin film embedded decoupling capacitors and experimentally investigated its electrical
behavior in terms of power-ground impedance and simultaneous switching noise (SSN). Several test vehicles and network
system boards were fabricated and the effectiveness of embedded decoupling capacitors was compared with that of discrete
surface mounted (SMT) ceramic capacitors. For the test vehicles,five types of embedded capacitance materials were used,
with various capacitance densities ranging from 0.45 to 12nF/in2. According to the frequency and time domain measurement
of power-ground impedance and SSN,the better performance was obtained as the distance of power-ground decreases while
capacitance value increases. In the high-speed system boards evaluation,the embedded capacitor board showed lower
radiated electromagnetic interference (EMI) by about 10dB µV/m compared with the conventional board with SMT ceramic
capacitors especially in the higher frequency range over 1GHz. The construction design for the embedded capacitance board
and reliability guideline will be also presented.

Embedding discrete capacitors right into printed circuit boards (PWB),although not new,is part of a pivotal technology for
the PWB industry. For example,the ability to locate decoupling capacitors within a couple hundred microns of
semiconductor I/Os can greatly improve response time and signal integrity. One crucial packaging need,however,is high
capacitance density. High capacitance density can only be readily achieved by ceramic capacitor technology. Therefore,the
focus of this work has been to develop materials and methodologies to embed high capacitance ceramic capacitor layers
inside the layers of the printed wiring board.
Most research in embedding high capacitance ceramic capacitors layers directly into printed wiring boards has focused on
forming capacitors on metal foil at high temperatures. It has generally been assumed that demonstration of good properties of
these “fired-on-foil” capacitors is all that is necessary to be successful. However,in our experience,the greatest challenges to
reliably embedding ceramic capacitor layers inside printed wiring boards reside in the design of the circuit containing
embedded capacitors and the PWB embedding process. Not only does the PWB process have to contend with additional
tolerance issues but,depending upon design,the capacitor may be subjected to aggressive processes and chemicals that may
affect its mechanical or chemical integrity. It is,therefore,incumbent upon the designer to design circuits that can be reliably
made by a PWB shop. This paper discusses these issues and gives some guidelines for design for manufacturing.

The miniaturization of mobile electronic devices continues,market trends toward lighter and thinner printed circuit boards (PWB) have been accelerating. At the same time,the demand for increased functionality of mobile devices has required the
PWB to realize higher density patterning to accommodate more and narrower pitch CSPs on a smaller and thinner PWB. In
order to meet these market demands,IBIDEN has developed a stacked-via structure PWB called “FVSS” (Free Via Stacked-
up Structure). This structure is achieved by filled-via technology,a core technology that fills a laser-drilled hole with copper
plating. The mass production of this technology started in 1st quarter of 2004,and it has proved that,compared to a
conventional type of PWB,design flexibility and total board thickness can be significantly improved. More details regarding the design flexibility,electric characteristics,and reliability will follow.

This article summarises how a copper metallization process for simultaneous via filling and through hole plating was
developed on a laboratory scale and the challenges encountered by scale-up to larger industrial like electrolyte volumes.
Uniform filling and through hole plating on large PWBs was successfully achieved by combining various technologies for
achieving uniform current distribution,hence good via filling efficiency and PTH metallization,independent of sizes and
location on the board surface. Both panel and patterned boards were treated.

This paper describes Advanced Filled Via Plating Methodology for stacked via technology. In this paper,via bottom crevice,
via bottom land etching and electroless copper plating coverage is focused to achieve filled via plating enhancement.

A high-power-SMD-LED (HL-LED) outline 3,3 x 2,9 mm² was developed,with chip-size up to 1 mm² and power dissipation
up to 1.500 mW (400 mA for UV-InGaN) in a corresponding thermal ambient. The thermal resistance is 12 K/W. For high
integrated applications (spotlights,general lighting) special PCBs with isolating layers thinner than 10 µm (commercial solutions:
75 µm) was developed also. Modules on 1 mm copper,area 40 x 40 mm² with 100 HL-LEDs,Ptot = 50 W,Popt = 8 W
in amber (592 nm) and thermal resistant 6 K/W were demonstrated.

In high speed digital interconnects; signal attenuation is a result of both dielectric losses and conductor losses. Previous
works have showed in detail,the characterization and modeling efforts regarding the impact of dielectric loss in PCBs and
the differences between various dielectric materials. Most high speed characterization modeling efforts have not
encompassed the variations in conductor losses due to variations in copper foil roughness or treatments of copper foil for
adhesion. Several recent publications have reported frequency dependent copper losses that do not follow the classical square
root relationship. This paper presents the results for a set of high frequency loss characterizations across various copper foils
and the impact of the copper roughness on the relationship between conductor loss and frequency. Also discussed in this
paper are the implications in high frequency modeling resulting from non-classical conductor losses and the requirements to
ensure causality in simulation results.