As designers strive to extract ever more performance from high speed transmission lines on FR4 substrates and their high speed derivatives,a requirement has arisen for a practical and robust “Go / No Go” test technique for loss to be deployed on the PCB production floor. The intent of this paper is to propose that RIE (Root Impulse Energy) testing is a practical and achievable test method. It is easily deployed and offers repeatable,reliable discrimination between PCBs fabricated with a range of varying base material loss characteristics.
Until recently digital signals on PCB transmission lines operated at sub gigabit data rates. Consequently,losses were safely ignored while characteristic impedance was the major transmission factor. Today loss is a major consideration when pushing the limits of transmission lines on PCB boards. A board may be designed to take advantage of the transmission capabilities of a high specification dielectric,but an inadvertent substitution of an inferior specification core or prepreg during the manufacturing cycle,which may easily go unnoticed,could be fatal to the electrical performance of the system.
This test is designed to give fabricators a first indication of a change in loss characteristic on a given transmission line structure / layer stackup. This change in characteristic loss may be due to a number of factors including incorrect material used in a stackup. It may also be used in conjunction with other techniques (more suited to lab / QA use) to flag the need to escalate problem builds for more detailed laboratory analysis.
The RIE method has been presented in previous papers and presentations [1]. This paper looks at some of the more practical implementations of deploying this method in a conventional production environment. TDRs from two manufacturers were used for the acquisition of results in this paper.

More and more circuit board designs require signals paths that can handle multi-gigahertz frequencies. The challenges for organic circuit boards,in meeting these electrical requirements,include using high-speed,low-loss materials,manufacturing precise structures and making a reliable finished product. A new circuit board HDI technology,using Z-interconnect,is presented that addresses these challenges. The Z-interconnect technology involves building mini-circuit boards of 3 or 4 layers each,then assembling several thin circuit boards together to make the finished product. Designing and manufacturing the thin circuit boards separately,then assembling them together,makes it possible to reliably manufacture circuit boards with no via stubs,very low-loss materials,nearly arbitrary transmission line structures and a lot of flexibility in tuning features to reduce signal loss. In the present paper,we have designed and built a circuit board test vehicle (TV) to make new RF structures,using Z-axis interconnection (Z-interconnect) building blocks. A typical 50-ohm stripline was designed with a
ground-signal-ground structure. The stack-up had 23 metal layers,including 5 0S1P joining cores and 6 2S1P signals cores. Teflon-based Taconic materials TPG30 and TLG30 were used for the dielectric layers. Laminated conducting joints show low resistance in the range of 1 milliohm for a 0.3mm diameter,250um length joint. Electrically,S-parameter measurements showed very low loss at multi-gigahertz frequencies. The losses were low enough to support typical SERDES links up to 15 Gbps over 30” net length. This effort is an integrated approach on three fronts: materials development and characterization,fabrication,and design and electrical characterization at the board level.

Typical PCB materials have inherent properties (the “Fiberweave Effect”) which can be detrimental to the Signal Integrity of the physical link. This presentation describes the effect and a means to mitigate for it (image rotation). The possible effects on PCB fabrication and manufacturing include: dimensional; SMT solder joint; mechanical properties (elastic modulus,warpage,and CTE); and impact to Solder Joint Reliability. A study of those effects is summarized and presented. INTRODUCTION Image Rotation was outlined as a mitigation technique for the Fiberweave problem in an earlier Intel White Paper [5]. This paper represents follow-on efforts to analyze the viability of that strategy for High Volume Manufacturing. The intent was to answer the following questions regarding Image Rotation:
1) Are features distorted? E.G..,are trace widths affected?
2) Are features’ locations distorted?
3) Are Surface Mount Technology (SMT) structures (solder joints) negatively affected?
4) How are PCB mechanical properties (elasticity,warpage) affected?

Failure analysis was performed on fourteen thermally cycled or vibration tested PDIP components from the JCAA-JG-PP Lead-Free Joint Test Project. The components differed in component finish,solder alloy used for assembly,test vehicle/circuit board type,rework (yes or no),and rework alloy (if relevant). Components were either vibration or thermally tested. A qualitative comparison was made between the extent of damage visible using 3D digital microscope images of the solder joint surfaces and the damage seen in optical microscopy cross-sectioned joints. It was found that use of a digital microscope,in conjunction with resistance measurements,made the decision of which joints to cross-section easier. However,it was not found that the digital microscope can be used exclusively,without cross-sectioning samples,to reveal the important damage features on stressed solder joints.

As the use of area array connectors has become more widespread in electronic assemblies,the need to evaluate their reliability has increased. There is,however,limited information on how best to perform accelerated thermal cycle testing of area array connectors. Though specifications such as IPC-9701A can serve as useful guidelines in assessing second level reliability of these components,area array connector test vehicles are more complicated than test vehicles designed for testing traditional area array packages,as they require the use of daughter cards to allow the daisy chain to be completed and to properly emulate a real-world implementation of the connectors. While IPC-9701A can provide useful guidance in designing the motherboard,it offers no insight on the design of the daughter card,nor does it provide assistance in determining which version of a connector to test in cases where there are several variations within a connector product family. As accelerated thermal cycling tests can be expensive and time consuming,there is a need to assess the impact of these variables on the reliability of a connector to provide guidance in choosing the best way to test,and to assist in understanding how changes in the design between the test vehicle and the final product design may be expected to change the reliability. The “Metro2” test vehicle was used to help generate data on these issues. In addition to providing manufacturability and reliability data on a selection of lead free area array connectors,three variations on one of the mezzanine connectors were studied to help assess the impact of design variables. The first comparison focused on the impact of changing the daughter card thickness from 0.062” to 0.093”. Previous work on a tin/lead version of this connector indicated that the flexure of the 0.062” thick daughter card during thermal cycling played a role in the location of the solder joint failures observed,and as a result,it is expected that the increase in thickness may change the location of the failures and could also affect the reliability of the connector. The second comparison focused on the stack height of the connector. A 4mm stack height version of the connector was compared with a 6mm stack height version. The results of accelerated thermal cycling will be presented for the variations of this mezzanine connector along with the failure analysis results. Results will also be compared to those obtained on the tin/lead version of the same connector.

Solder joints tend to crack after extended thermal cycling,if the component and the circuit board are CTE mis-matched. Predicting t-cycle lifetime is a crucial first step in optimizing product design and/or in-service conditions. Predictor models embody cyclic fatigue physics and math,and require inputs of the materials and geometry of the hardware as well as the thermal conditions of the environment. The output is the predicted number of t-cycles to fail (i.e. to develop electrical-open cracks thru the solder-fillet). Several predictor models are in use within the industry. This paper describes a comparison among several predictor models,rating them for ease of use,and for accuracy against known actual test results and against each other. The study uses a round-robin approach; wherein each participant was given the same input data for ten different components,but the actuals were withheld until the respective predictor results were in. Also,this paper describes a related study on the ability of each model to perform parametric analyses: i.e. to define the effect of variations in hardware and environmental conditions on t-cycle life. The results offer guidance on t-cycle life prediction,as well as on improving t-cycle life

A series of advanced screen-printing processes have been developed to build functional high density flexible electronic circuits. Not only do the single layer circuits have fine conductor traces,but double and multi-layer circuits are connected by micro via holes with embedded passives. Utilizing the whole process,an entire electronic circuit system can be built on a flexible substrate.

The peel test will be reviewed,with special attention given to deposited adhesiveless copperclads. Details of the specification are reviewed The relevance of the title subject will be addressed from the perspective that a vendor and a customer of a flexible material can head off disaster if they spend time communicating on what the requirements of that substrate material are.
We will consider the mechanics of the test,IPC specifications,will be reviewed with specific case histories in which the choice of peel method was critical to problem resolution.
We will discuss the many influences on peel strength values by presenting data on variables such as conductor thickness,conductor width,and copper treatment,as well as more subtle things such as surface finish and even simple choice of test method. Details such as the effect of surface finish will receive comment. Data concerning ENIG-plating will serve as the backdrop for this segment.
Audience members will be encouraged to participate by asking the “expert” to answer questions such as,“which test is most important,” and “how much peel strength is enough?” This will be used as a teaching opportunity to exemplify the value of close communication between customer and supplier.
Failure modes will be described for deposited clad flexible substrates. The value of investigation of this characteristic will be stressed,together with other investigational techniques for the engineer who may be new to the industry. Among these nuggets will be the exhortation to learn to write good English,which will permit a partial answer to the question posed in the title.
Choice of substrate material with respect to the tiecoat will be clarified by discussion of processing and product characteristics.
A brief mention will be made of alternative methods of adhesion measurement,including shear testing and tensile testing. Again,with the author?s own data on adhesiveless FCCLs,a picture will be provided of the relative strengths and weaknesses of each method.

Flexible electronics is the future trend of the worldwide electronic industry. The RFID tag is one of the main applications in flexible electronics currently. This paper presents a flexible HF RFID tag which is manufactured by a low cost screen printing technique. The inductive coupling antenna is constructed by printing conductive silver paste on PET substrate to achieve good flexibility. The inductance and quality factor value of the antenna were designed using an EM simulator tool. Several design issues such as metal thickness,line width,and spacing between conductive coils related to the performance of inductive coupled antenna have also been analyzed carefully. The optimized antenna structure is properly chosen based on EM simulation results and measurements of several prototypes. A Philips I-CODE label IC was mounted on the inlay after being thinned. (The details of the manufacturing process flow will be examined in this paper later.) Finally,a half-wave rectifier circuit is proposed in this paper to demonstrate the potential of designing flexible circuitry using a screen printing process. In this design,one special High-DK material (with DK=20) which was developed by ITRI MCL was adopted to manufacture the capacitors in rectifier circuit. The experimental results shows that the rectifier which is powered by general RFID reader can be used to light up one typical SMD type LED successfully. The whole circuit size is about 16 cm2.

The recent use of lead free alloys has made the wave solder process more challenging in terms of achieving acceptable solder joints for both SMT and PTH components. It has been found that the Design for Manufacturability (DFM) guidelines,which were established for tin lead processes,in many cases do not result in the same level of quality joints when soldering with lead free alloy. Therefore,in order to improve the process yields and reduce manufacturing costs when converting to lead free,it is essential to establish DFM guidelines specifically for lead free soldering. The effect of pin to hole ratio,quantity of large copper planes connected to a pin through hole barrel,connection types for PTH and land patterns for glue and wave chip components are some of the main features which require further investigation for design optimization.
As there are a variety of lead free alloys available on the market today,each with differing properties,it is also important to determine if a set of DFM guidelines result in similar results among these various alloys.
This paper will discuss the outcome of a project which studied several DFM features incorporated on an internally designed wave test vehicle,which was created to evaluate alternative lead free alloys. The DFM features included in this study were: land pattern design and varying component spacing for chip components,pin to hole ratio and its interaction with the quantity of large copper planes connected to a PTH,quantity of large copper planes connected to a PTH and its interaction with the type of connection either solid or four spokes. The test vehicle was assembled with four Pb-free alloys: Sn-Cu-Ni,Sn-Ag-Cu-Bi,Sn-Cu-X & SAC405 as the baseline. The quality level of each of the described DFM features will be discussed. In addition to this,a detailed barrel fill analysis for the PTH components will be shown.