PTFE-FR4 hybrid laminated multi-layer PCB technology is being applied more and more widely. This technology requires blind via fabrication in a PTFE core. This paper gives a picture of the manufacturing process for multi-layer PCBs with PTFE
focusing on material specifications of anti-overflow and surface treatment techniques,thereby addresses the feasibility of this
technology.

In the past the use of filling pastes in PCB production was largely limited to via hole fillers. These materials with a solids
content of 100% are still successfully employed today to close via holes and thus ensure their proper sealing for vacuum
adaptation during incircuit testing. Furthermore,they are used to avoid the deposition of flux residues that may create critical
microclimates in the holes and/or under components. However,there is only limited use for these products in newer fields of
pcb manufacturing.
The latest filling materials (also referred to as plugging pastes) are largely used in Sequential Build-Up technology. Due to
their specific properties,these materials enable the manufacturing of buried and blind via holes.
Thick film fillers are of growing importance in case of extremely high copper build-up (also termed 400 µm technology) in
order to allow a leveling of the traces before a solder mask can be applied.
All of the discussed materials belong to the electrically non-conductive type.

Factory simulation has been used extensively to optimize and reduce costs across many manufacturing disciplines.
Unfortunately,general purpose factory simulators do not effectively model the special needs of electronic assembly. For
example,the wide variations in rework time on different boards can create a significant bottleneck for the boards with low
first pass yield. This bottleneck delays product shipment,and results in higher costs and lower customer satisfaction. Since
time differences due to variations in first pass yield are not effectively modeled by general discrete event based
manufacturing simulators,this problem will not be caught if that is the only simulator used.
This paper presents a comprehensive approach to manufacturing simulation that includes detailed analysis of the boards to be
built coupled with a general manufacturing simulator to accurately predict the time,cost,and throughput for board assembly.

A tier one supplier to the automotive industry has determined that a key to staying competitive in the electronics
manufacturing industry is to adopt open standards for the exchange of data. Specifically,adopting the Computer Aided
Manufacturing using eXtensionable markup language data exchange standards,which are being developed and maintained by
the IPC as an open based standard. By making use of open standards,the cost and complexity of exchanging data on the
factory floor between various machines can be significantly reduced. In addition,it prevents competitive lockout,enables
portable processes,and facilitates reuse and redeployment.
Through open standards,this manufacturer of automotive components feels it can more closely monitor and correct out-ofcontrol
conditions and respond more quickly to part outages and other various negative variables that effect manufacturing.
To reduce the cost of implementing CAMX,a project has been started among 9 companies to produce an application program
interface (API),which can be embedded into various equipment manufacturer’s software programs or equipment control
programs. This will allow remote machine process interaction to reduce downtime,improve efficiency,and help eliminate
manual data collection and data crunching.
Since all the assembly equipment will now be sending out the same data format,they will collect this data in a Message
Broker. The message broker acts like a mailbox,collecting information from various machines that publish their run time
data. Sending out information like alarms,process parametric data,cycle time and other production and process information
depending on the application. The message broker has built in redundancy encase the network goes down. It will continue
collecting and storing this critical manufacturing data. Now other applications will subscribe to this information residing in
the message broker for real-time data analysis,trend analysis,and bottleneck analysis. We also store the historical data into a
database for further analysis such as root cause analysis or comparing efficiencies across different shifts and even facilities.

OEE (Overall Equipment Effectiveness) is commonly used in a wide range of businesses when it comes to measuring and
monitoring manufacturing performance. Even though OEE has been applied in various areas of businesses for a while,it has
gained less traction in the electronics-manufacturing arena,despite the fact that it is an excellent tool to compare overall
performance between production lines and manufacturing sites.
OEE is defined as Availability x Performance x Quality,which means that it is the first tool that provides a true picture of the
total performance ratio taking also the quality aspect into full consideration. The overall objective of implementing OEE is to
obtain a reliable measurement of the production performance across factories,production lines,work groups,etc.,while still
being able to compare performance ratios across different products as well as across different equipment types from various
machine vendors.
The goal is of course to use OEE as a tool to continuously improve the throughput and quality of production cycles. In this
respect,it is essential to have exact and reliable background data,and a good tool-set to drilldown on the actual causes of
performance loss or deterioration.
It is basically quite easy to calculate OEE by simply counting the number of produced boards and the accumulated number of
defects. However,without detailed drilldown capabilities to capture relevant production data OEE lacks the information
depth to provide an accurate reflection of the current production process to suggest measures leading to improvements in
performance and end product quality.
The best way to assure that detailed and accurate data is available is by automatically capturing it from the production
equipment and embedded systems. Operator involvement in the data collection process is not only time consuming,but
always leads to impaired data accuracy and timing deviations.
This article will elaborate on best practices how to obtain the necessary production data,extract the relevant information and
properly evaluate it before implementing into the OEE model for results generation.
Overall Equipment Effectiveness (OEE) is a new tool for measuring and improving overall production performance,and
makes it possible to compare performance across factories,production lines and even production teams. OEE is widely used
across different industries,and is now also introduced into electronic production. This article specifically deals with OEE in
the PCB assembly industry.

Lead free implementation will present new challenges for PCB manufacturers from a design,soldering process,and QC
standpoint. The higher reflow process temperatures will cause greater thermal stress to the PCB substrate as well as to the
components. The smaller soldering process window,which lies between the higher lead free alloy melting point and the
maximum allowable component temperature,will make the soldering task more difficult. Specific challenges,however,
must be considered in order to guarantee required DPM levels and a minimum of in-field PCB failures. In particular,the
very small solder joints found on Flip Chips (FCs) and Chip Scale Packages (CSPs) will see a great deal more thermal
stress during the lead free soldering process,which can result in fatal defects. This paper will discuss the existing
problem of topside ball delamination for the area array packages FCs and CSPs by highlighting passages from recent
research publications. The research shown presents important failure analysis data relating to FC and CSP reliability in
both a tin-lead and a lea d free soldering process. Finally,an introduction of a new optical inspection technology designed
to detect such defects in a non-destructive manner will be made.

While the Ni-stabilized Sn-0.7Cu alloy is now well established as a viable lead-free solder in large scale commercial printed
circuit board assembly the effect of Ni is not yet fully understood. It is likely that the effect is related to the preferential
incorporation of the Ni into the crystal structure of the Cu6Sn5 intermetallic but this effect needs to be further quantified and
related to the observed behaviour in production soldering. In this paper the results of DSC and microstructural analysis are
reported and the possible connection with the performance of the solder proposed. These results suggest that the Ni
influences the nucleation and growth of the intermetallic with consequential impacts on solder flow and joint appearance.

There are compelling reasons to study the relationship between oxidation and the topography of solder powder; these
include the following:
?? Customer requirements to reflow SAC-based (SnAgCu) lead-free solder paste with profiles that are considerably
longer than those used for lead-bearing products. The ultimate challenge in this requirement is to reflow using these
longer profiles without a nitrogen blanket;
?? Early developments with more reactive lead-free products such as Sn/Zn solder paste revealed the fact that some of
these materials not only showed a lower wetting potential but also an inferior mobility when compared to traditional
solder paste;
?? As an ISO-TS-16949 certified company,one of our main goals is the continuing quest for further reduction in the
variation of our products.
Qualification studies and field experience by major end users of Pb-free solder paste have uncovered significant issues
with the material; these include surprisingly short shelf life of several types of Pb-free solder paste and significantly
variable results regarding voiding. We are of the opinion that both phenomena have a potentially common root,and that
is oxidation of the solder powder during production. It is common knowledge that oxidation appears to be selfpropagating.
So,when solder paste is manufactured with powder that is relatively oxidized,it will further deteriorate
once it is in suspension with specific flux systems. Thus,shelf life may become surprisingly short,evidenced by a solder
paste that,for example,has unexpectedly become as hard as concrete.

For the purpose of mask-less manufacturing for Printed Circuit Board (PCB),a new process using electrophotography
technology,principle of copy machines,has been proposed and evaluated. Wiring patterns can be formed by electroless
plating on the seeding patterns printed with the novel toner that is made of thermosetting resin and metal fine particles.
Insulating layer can be also patterned by printing with resin toner. To build up multi-layered structure of PCB,these two
processes are repeated in turns. This new method has some big potential to simplify manufacturing process for wiring and
reduce the cost of PCB.
The first technical issues were to control electrostatic charge of toner including metal particles and to get enough quality of
printed seeding patterns for electroless plating. We started to develop the novel toner from investigating about the relationship
between metal contents,electrostatic charge of toner,and plating ability. And it was established that new wiring process using
electrophotography is available for PCB tracing. Similarly,insulating single slayer and multi-layered structure were formed
by new process and appraised. Additionally,some trial samples by this new process were evaluated by some basic reliability
tests. For demonstration,flip chip assembly was carried out and antenna substrates for RFID tags were fabricated.

In order to satisfy the ever-increasing demand for smaller and lighter electronic devices,a drastic miniaturization is making
rapid progresses for even circuit features on printed wiring boards (PWBs). Compared with a subtractive method which is
traditional PWBs manufacturing process,a semi-additive method is regarded as a more favorable process for these
miniaturization requirements,whereas it has a problem that surface insulation reliability deteriorates due to palladium (Pd)
catalyst remaining on insulating resin between conductors. In order to overcome this drawback,various methods have been
attempted to remove Pd catalyst so far,but they have some sort of problem and it is still difficult to obtain satisfactory results.
Now,novel chemical solution,a remover for Pd catalyst residue,has been developed to deal with the problems. This paper
demonstrates a comparative study of the newly developed remover and conventional methods as for the surface insulation
reliability. It is finally confirmed how this Pd remover contributes to the successful materialization of high surface insulation
reliability in fine-line PWBs fabricated by the semi-additive process.