As IC technology advances,electronic packaging for the ICs has had to advance as well. The package methodology has become technically more sophisticated and physically more complex. For many IC package applications,the lead-frame package technology of the past is not adequate. The Ball Grid Array (BGA) and Chip-Scale Package (CSP),on the other hand,are seen by many as the most viable solution for improving both functionality and performance. Array package technology is well established in the industry and the market growth for the BGA families has exceeded forecast. The array package technology and methodology has evolved throughout the past decade and many of the newer generations of BGA and CSP devices have become smaller and adapted finer contact pitch than their predecessors. The finer contact pitch BGA package enables the IC manufacture to meet the demand for higher I/O need for the mo re complex applications while maintaining a relatively small package outline. By adapting a finer contact pitch,however,can dramatically affect the methodology used in board design and assembly. Because of the higher contact density made possible by array type packaging,design specialists have realized that the higher density land pattern geometry significantly effects PC board routing efficiency and can definitely impact fabrication cost. When adapting BGA and chip-scale BGA packaging in particular,one must consider board fabrication tolerances and provide the necessary physical features needed for assembly machine processing. For assembly process control,land pattern geometry is of primary concern because it is directly related to solder attachment uniformity. This paper will review BGA/CSP applications,packaging standards and package assembly methodology,furnish circuit routing guidelines for array packaged devices and review recommendations for design defined in IPC-7095A,the Standard Guideline for Design and Assembly Process Implementation for BGAs.
