As more electronic assemblers move to lead free SMT production,concerns are raised over reflow cooling slopes and effects
on solder joints. Due to the higher peak temperatures,cooling slopes are naturally more aggressive if not controlled properly.
Impacts of variable cooling slopes should be considered for the transition to lead free assembly.
This paper evaluates the effect of variable cooling slopes on lead free solder joints. Controlled testing of lead free assemblies
subjected to various cooling slopes in both air and nitrogen environments is also discussed. Solder joints will be inspected for
solder joint grain structure under differing conditions of aggressive,medium,and mild cooling slopes. Data will be presented on the findings of this study along with suggestions of desirable cooling slopes and reflow system options to best support the
reflow cooling profile.

As lead free assembly is ramping up,wetting of lead free solder pastes is surfacing as the major paste performance tradeoff.
Global efforts to significantly increase lead free wetting chemically have proven unproductive to date. The “drop in” lead free
paste with respect to wetting looks to be improbable. This paper reports the findings of numerous studies using quantitative wetting gauges to measure solder paste wetting to the PCB surfaces. Wetting results with various lead free profiles,reflow
atmosphere oxygen concentrations and lead free PCB surface metallizations are compared and contrasted for their
contribution to maximizing lead free wetting. Although numerous lead free alloys are on the market today,this paper concentrates on the popular SAC (Sn/Ag/Cu) alloy specifically 95.5/4/0.5 in a no clean paste. In addition to wetting,solder
defects and voiding are included in the comparisons to reveal the best overall lead free reflow process.

Traditional reflow profiles for lead-free soldering typically require longer processing times due to elevated peak temperatures
and flux activation times defined by solder paste suppliers. These profiles become particularly challenging when a wide
variety of packaging types are integrated within a single circuit design. Further difficulty is presented when product designs
with high thermal mass,such as heat slugs and metal substrates,are processed. These designs create large thermal gradients
throughout a circuit assembly and add further complexity to finding an “optimal” profile window. All of these issues create a
significant increase in reflow processing times for lead-free soldering.
This paper investigates these increased processing times required for high volume manufacturing of lead-free electronics. A
study of typical process capacity and real throughput capacity is presented. The study evaluates high volume electronics
manufacturing ranging from small circuit assemblies (e.g. cell phone) to large circuit assemblies (e.g. automotive and
computers) and investigates a series of “best” reflow profiles to accelerate the standard lead-free process window to meet a
targeted manufacturing capacity using an automated profiling system. A test vehicle is then fabricated using this defined
process window and tested for quality (solder voiding and appearance) and solder joint reliability (accelerated life testing).
The designed test vehicle includes components from a large physical distribution including: small and large BGAs,QFNs,
and any type discrete components. During assembly,virtual profiling is used to document any deviations to the process
profile window. The quality and reliability data are presented within this publication and failure analysis is included to
determine the capability of this proposed profile.
When employed,this profiling strategy allows many manufacturers to reduce the processing time for reflowing lead-free
circuit assemblies without significant lost in manufacturing quality or reliability. Furthermore,this study provides a sound
understanding and limitations for using accelerated profiling speeds for lead-free soldering applications.

The copper plating process is one of the most critical steps in the high end PCB manufacturing process. Although the
deposition inside through holes and blind holes is the key factor for reducing the fall out fraction,the thickness distribution
over the entire layout is also critical,in particular for multiplayer designs. A performance plating simulation tool (P2ST) for
the prediction of layer thickness distributions over PCB's is presented. This tool takes into account the bath characteristics
(conductivity,electrode polarization),the PCB layout,the electrical signal parameters (DC current or bipolar current
amplitudes and duty cycle),and the PCB positioning in the plating tank.
This tool allows us to perform a fast prediction of the layer thickness distribution over tracks,pads,ground planes,robbers
etc. The tool can be used by any PCB manufacturer either in the cost estimation phase and/or as an auxiliary tool in the CAM
work flow. In the latter case,the tools represents a powerful asset for the optimization of pulse signal and/or background
patters (copper balancing) towards layer uniformity specifications.

Horizontal and vertical pulse plating have been widely used for panel plating in PCB industry,but rarely used for pattern
plating. This article analyzes and reviews the crystal structure,throwing power,surface distribution,elongation,appearance,
thermal shock,temperature cycling and IST test of copper plating after pattern plating. The article also describes some
problems and their resolution in production.

Two important aspects concerning optimum performance of a (reverse) pulse plating line are (i) the uniform and correct pulse
shapes anywhere on the PCB and (ii) the uniformity of the plating current density (thickness distribution) over the whole
plating window of a vertical line or the entire width of a PCB in a horizontal line. To measure both precisely,comfortably,
and quickly the island method was enhanced to Optipulse 80. Special test boards with measurement islands and calibrated
shunts on both sides are used to check site-specifically the cathodic plating current density as close as possible to production
conditions. Sampling frequencies up to 20 kHz precisely resolve pulses as short as 0.5 ms. Up to 80 channels are sufficient to
obtain a well resolved overview over the plating window of most vertical lines within less than ten minutes. Statistical data
evaluation and visualization features make this a powerful tool for optimization of pulse plating lines (also applicable to DC
plating,of course). The system now has been successfully in use for more than three years. This paper presents a short review
of its history and the actual features as well as some examples from recent data.

The upcoming European Union RoHS and WEEE directives are driving new requirements for the management and exchange
of information,both across the extended electronics manufacturing value chain,and across the product lifecycle. The
Restriction of Certain Hazardous Substances in electrical and electronic equipment (RoHS) bans or severely restricts the use
of certain substances in the manufacture and assembly of electronics products to be marketed in the EU. The regulation of
Waste from Electrical and Electronic Equipment (WEEE) places strict requirements on the handling and disposition of
electronic products at their end of life. All electronics OEMs that sell products into the EU states will have to comply or they
will lose access to these markets. Information on the material composition of all components and bulk materials that go into
the manufacturing of products will have to be available and shared,across multiple tiers of the supply chain,to support RoHS
compliance. Information on substances of concern and the location of any hazardous substances,along with disassembly
instructions,will have to be available to recyclers to support WEEE. Additional information will likely be required to support
the upcoming directive on Design for Energy Using Products. Some estimates1 place the cost of enhancing and updating IT
systems to support environmental compliance for an average electronics producer at $2-$3 million over the next 3 years.

System in package (SiP) technology has grown significantly in the past several years. It was barely mentioned in the National
Electronics Manufacturing Initiative’s (NEMI’s) 2000 roadmap,but by the 2002 roadmap,SiP was one of the fastest growing
packaging technologies. Even though,at that time,SiP represented a relatively small percentage of the total unit volume,the
2002 NEMI roadmap noted that SIP was becoming a common technology in the high-growth Bluetooth,WLAN (wireless
local area network) and mobile phone applications. By 2004,SiP had grown so significantly that it was added to the roadmap
as a new product emulator group (one of seven),which are used to define future manufacturing needs across the entire
electronics supply chain.

For four decades,the semiconductor industry has distinguished itself by the rapid pace of improvement in its products. The
principal categories of improvement trends are shown in Table 1 with examples of each. Most of these trends have resulted
principally from the industry’s ability to exponentially decrease the minimum feature sizes used to fabricate integrated
circuits. Of course,the most frequently cited trend is in integration level,which is usually expressed as Moore’s Law. (i.e.,
the number of components per chip doubles every 24 months). The most significant trend for society is the decreasing costper-
function,which has led to significant improvements of productivity and quality of life through proliferation of computers,
electronic communication,and consumer electronics.

A new multi-layer PCB (printed circuit board) having low transmission loss and low thermal expansion that meets up-coming
further high speed and high volume data transmission demands was developed. New modified polyphenylene ether (PPE)
resin that posses excellent dielectric as well as thermal properties (Tg>200ºC) has been successfully designed and developed
in house. The selection of a PPE backbone structure let us realize low Dk and low Df of the PCB,resulting in lower
transmission loss. Low CTE of the PCB was achieved by incorporating inorganic fillers,while keeping low Df. By using
special VLP copper foil,high-speed data transmission performance was improved significantly. The Dk,and Df of the
developed PCB is 3.4-3.6,<0.002(1GHz) respectively and CTE in z direction is 45-50ppm. These are the basis of our
development. We demonstrated about 50 % reduction in transmission loss in comparison to FR-4. Because of its low CTE,
the PCB indicated excellent through-hole reliability. Over 2000 cycles of reliability were observed in its heat cycle (T/C;
-65ºC to 125ºC) test. It was 4 times better performance than that of FR-4. The PCB showed high CAF resistance as well. No
distinct failure was observed within 300 hours in its HAST (110ºC/85%/50V). Accordingly,newly developed our PCB has
reliable performance. The PCB is compatible with the conventional PCB manufacturing process. Thus,we believe our newly
developed PCB will offer one of the most promising solutions to achieve ultra high speed signal transmission technology that
will play a very important role in the emerging era.