Beginning July 2006,the electronic industry will enter the age of lead –free assembly and products in Europe. The removal
of lead from electronics brings massive changes for all companies in the supply chain,OEMs and contract manufacturers.
Lead Free SMT assembly poses many challenges for soldering and reflow processes. It requires significant process
optimization efforts to perform high volume manufacturing successfully and get good,reliable solder joints. Migration to
lead free assembly requires careful balancing of bill of materials with reflow profile. Double sided reflow requires careful
balancing of delta T from Side A to Side B reflow.
Cellphone assembly requires the use of thin form factor PWBs to meet the drive for miniaturization and thin,light products.
This is accomplished by using HDI- high density interconnect boards or build up technology boards. [1]. These PWBs have
stacked microvias,which are laser drilled and plated. The switch to lead free assembly requires the use of higher reflow
temperatures,so evaluation of the microvia connections after reflow is critical after assembly.
Solder joint reliability evaluations have to focus on Ball Grid array solder joint integrity,SMT packages,passive components
and connector solder joints. Rework processes are an essential part of the reliability evaluations as higher peak temperatures
for rework may affect PWB laminate,near neighbor components and package integrity.
This paper presents the results of lead free solderability qualification conducted at Kyocera-Wireless Corporation. The report
summarizes the results of X-sectional analysis,shear testing,thermal shock and temperature humidity testing of lead free
assemblies using a HDI board.
The paper summarizes the surface mount assembly evaluation conducted to ensure the stability of the laminate and microvias
through the double-sided reflow process and rework. This was evaluated as a part of the phone product qualification build.

The challenges for today’s PCBs are many,including higher assembly temperatures and higher device heat transfer
temperatures; faster clock cycles and higher bandwidths; higher component density; lower noise margins and high current
carrying requirements; while maintaining or improving cost/performance ratios and increasing assembly yields and field life.
This paper presents the work in Teradyne to characterize and qualify new printed circuit board (“PCB”) dielectric substrates
(a.k.a. “laminates”) to meet the requirements of lead-free assembly,while providing more reliability and flexibility to design
engineering. The paper provides details on: A) the drivers and the objectives of the program; B) some key properties of the
laminates selected for testing; C) the tests and the results; and D) some discussion and conclusions.

Dross generation has always been a costly issue for the electronics assembly industry. At least half,and in many cases,more
than half of the metal (solder) purchased for electronic manufacture is wasted as it becomes tied up in dross. With the advent
of lead free solders the moderate economic pain of dross generation becomes acute. A new process recently introduced to the
industry cures virtually all problems caused by dross.
This paper will show the true cost of dross,including metal replacement,loss of efficiency,and safety as well as
environmental issues clearly demonstrate a need for a solution to this problem. In addition to dross elimination the process
has been shown in the lab to reduce temperatures for wave and selective soldering and to improve wetting. Collaborating beta
test as well as lab test data will be presented along with initial actual production results.
In addition to answering the technical questions,why and how the “economics of dross” will be examined and a specific and
significant cost savings scenario will be presented.

Today,there exists a major push towards lead free soldering in the international electronics industry. It has presented a
number of challenges in both the surface mount and wave soldering processes. The conversion of assembly processes to lead
free from conventional tin/lead has put a strain on the smaller contract manufacturers in North America due to the perceived
need for improved production equipment. This includes recommendations for wave solder upgrades,reflow ovens with
seven or more heating zones,and repair equipment with improved preheating capabilities. These improvements require
capital investment that many smaller contract manufacturers cannot afford in the current electronic economic climate. This
paper details the development of a no clean lead free solder paste designed to be used with small reflow ovens with four to
six reflow zones. The paper will review flux chemistry,and recommended oven settings and modifications. The conclusion
is that there are viable lead free reflow soldering options that can be implemented with existing equipment and the process
will continue to improve as companies gain more experience in the subtle differences between soldering with tin lead and
lead free alloys.

During the design phase of a project,distribution of metal on the external layers of printed circuit boards is not a
consideration. System designers concentrate on implementing the required logic. PCB designers have to satisfy many
electrical and mechanical constraints and they do not lay out boards to provide an even distribution of metal on external
layers. This creates a difficult problem for the fabricator,who tries to evenly plate a board with uneven metal distribution. In
high-speed boards,uneven plating creates uneven impedance and circuit timing margins are decreased,negatively affecting a
circuit board’s performance.
In a plating tank,plating current is essentially constant across an entire panel being plated and all of the plating current must
be absorbed. Pads and tracks in an area of a board with low metal density will be plated more than the same pads and tracks
in an area of high metal density.
If a track originates in an area of high metal density and traverses an area of low metal density,its cross-section area will
change due to uneven plating. A change in cross-section area will produce a change in impedance and part of a signal
traveling along the track will be reflected. Reflections will cause a reduction in pulse amplitude,plus an increase in rise- and
fall-times. This will reduce circuit timing margins and may be the difference between a high-speed board working or not
working.
The best method of avoiding tracks with varying impedance is to equalize the metal distribution on external layers. Using
statistical analysis,the mean metal distribution is computed and thieving only added to areas below the mean to bring them
up to the mean. This provides a more even distribution of metal across a board,which will lead to better performance of highspeed
boards. Equalized plating will also make a board flatter,improving assembly yields.

Layout designers play a critical role in the design of high-speed circuits. In an optimized process,they take constraints
defined by engineering and create a layout that adheres to those design rules. Typically,however,the process is more ad hoc
with constraints being transferred via paper or voice,putting more responsibility on the layout designer to translate the
requirements and implement a functional design. In some organizations,engineering has taken over layout of high-speed
signals to ensure accurate implementation of constraints. Unfortunately,this often results in designs that are impossible to
complete or are un-manufacturable.
Today's complex designs can have advanced constraints on 80-90% of the board's signals,significantly increasing the layout
difficulty and design cycle time. To appropriately manage and implement these constraints,layout designers must
understand concepts such as differential impedance/signaling,star net topologies,interconnect delay and crosstalk coupling.
This paper will address:
• High-speed constraint categories in “electrical” and “physical” incarnations
• An optimized design process focusing on collaboration between engineering and layout departments
• Routing best practices to adhere to advanced high-speed constraints
• The impact/benefit of advanced fabrication technologies like HDI and embedded passives on high-speed design.

Whether based on good science or not,the elimination of lead from electronic equipment as a result of the European RoHS
legislation is a reality. Even those market segments with exemptions meant to last several years are being pushed towards
Lead Free assembly sooner than expected due to component availability concerns and constraints within the electronics
manufacturing services industry. The most common question asked of base material suppliers is ‘what laminate can I use?’
From the standpoint of ‘compliance,’ most laminate materials are acceptable. Most materials do not contain lead or the other
restricted metals. The brominated flame retardant used in most laminates is NOT restricted either. However,in terms of
‘compatibility,’ the answer is very complex. This is the result of several factors. First,PWB design and construction will
have a significant impact on the base material properties required. Thin,low layer count PWBs may have different
requirements than very thick,high layer count PWBs. Copper weights,aspect ratios and other design features will also have
an impact. End use application and the associated requirement for long-term reliability will also impact the decision-making
process. The requirements for a cell phone,video game or even a computer motherboard will be very different than those for
high-end servers,telecommunications gear,avionics,and critical medical and automotive electronics. Last,not all Lead Free
assembly processes are the same. Some designs will experience peak temperatures of 245oC while others will experience
peak temperatures of 260oC. Some PWBs may experience 2-3 thermal cycles,others up to 5-6,or even more depending on
how many reworks are allowed. All of this makes it impossible to recommend one base material for all applications without
either under specifying the laminate material and risking defects during assembly or later on in the field,or over specifying
the material and paying too much for the material or limiting availability. The purpose of this paper is to summarize the
critical laminate properties,present test data showing the impact of higher temperatures,and introduce a laminate material
selection approach designed to help answer the question regarding what laminate material should be considered for a given
application.

Supply chain readiness and compatibility are critical to a smooth transition to environmental compliance for the worldwide
electronics industry. This paper reviews the status of Lead Free soldering and RoHS compliance,supply chain readiness,key
compatibility issues and future challenges.

Meeting RoHS requirements is confusing at best. Currently,RoHS bans the presence of 6 substances,: Lead (Pb),Cadmium
(Cd),Mercury (Hg),Hexavalent Chromium (Cr6+),Polybrominated biphenyl (PBB) and Polybrominated diphenylether
(PBDE). As of 18 August 2005,the European Union (EU) amended the RoHS document with maximum concentration
values (MCVs) of 1000 ppm for 5 of the substances; Pb,Hg,Cr6+,PBB & PBDE and 100 ppm for the 6th substance; Cd at
the homogenous level. Other documents within the EU and member states have defined MCVs,but there is not total
agreement between EU Directives and the member states on the maximum threshold values. With the delay of defined RoHS
thresholds,other regions of the world are defining MCVs,but without universal agreement. Companies in the electrical and
electronics equipment (EEE) industry are subsequently incorporating their understanding of MCVs into company
specifications and requiring the suppliers to meet them.
What are the existing EU Directive requirements? How do they apply and what thresholds should be used for electrical and
electronic products? This paper will discuss the RoHS 6 substances,thresholds as stated in the EU,common company
defined threshold differences and the issues they cause. It is not all inclusive since laws and directives are constantly
changing,evolving or being released.

Portable electronic device circuit packs were ground up to more than meet EPA sieving criteria and were then subjected to
the well known EPA Method 1311 leaching protocol. Based on work from the previous study,mainly Fe,Ni,Cu,Zn,and Pb
were investigated. Leachate was also separately treated with egg whites and cardboard and the dissolved metal
concentrations were found to be significantly reduced. Individual spikes of 500mg Fe,Ni,Cu,Zn,and Pb (artificial leachate)
were run through columns of topsoil,sand,gravel,vermiculite and perlite to compare to the earlier work using topsoil,in a
continuing effort to show what might happen if leachate were to escape from a landfill.