The number of applications using Embedded capacitor technology on Printed Wiring Boards (PWBs) is increasing. One of the increasing applications using embedded capacitor is high-speed digital application and another is module for hand held devices.
For high-speed applications,design of Power Distribution System (PDS) is becoming challenging and solution for EMI is becoming more difficult. Traditional method to cope with these challenges was to use discrete capacitor components by optimizing component type,amount and location. As LSI technology scales to faster transistors and lower voltage,this traditional method is becoming ineffective,inefficient and costly. Embedded Capacitor technology has proven to be effective to overcome these issues by contributing to provide low impedance PDS and reduce EMI. In this paper,we have studied effectiveness of Embedded Capacitor using commercially available simulation software.
For module for hand held devices,the demand for higher HDI is endless. One of solution for higher HDI is to embed capacitor function inside PWB. Although there are various embedded capacitor materials proposed,the challenge still lies in the PWB fabrication to form uniform and reliable capacitor cost effectively. In this paper,we propose practical method of forming embedded capacitor and discuss what can affect tolerance of capacitance value.

This paper is the second concerning the use of existing electrical test equipment being programmed to first measure the values of plated additive resistors manufactured on circuit board inner layers. Next,this value information is programmed into the software of a laser routinely used to drill microvias for circuit boards. A computer routine calculates the amount of the resistor that needs to be removed to adjust each resistor to the required design value. The trimming is then conducted on the actual inner layer.
Advantages of this technology include eliminating the manufacture of probe cards for each new circuit design,and utilizing existing machines for this new technology task. While accuracy of trim with this “off-line” machine may not be quite as precise as active trimming with probe cards,the accuracy is sufficient for many of the 5-10% resistor values needed for such design applications as digital signal termination. Plated additive resistors,with their uniform thickness across each resistor,are particularly easy for this technology combination to trim.

This work initially started with some research into ink jet technology materials for legend printing. Our company in Hong Kong was working at the time with a Japanese company with the end goal being the development of a new machine for PCB legend printing. As part of that project,we were developing a new TiO2 based ink for white legend printing.
As part of the total process,we wanted to obtain electrical data on the materials we had developed,and included capacitance as one of those items. This was accomplished by coating the materials between two copper plates. We were quite surprised to find reasonable and repeatable values. Please note from Figure 1 that this was really quite a sloppy initial test.
For a number of years it has been technologically feasible to place distributive capacitors as layers within an MLB,but I felt that the ability to lay down individual capacitors of different values within the same circuit layer was infinitely more valuable. Thus started our work that is described in this paper.

Pure and doped barium titanate thin films have been prepared by chemical solution deposition on 18 µm thick,industry standard copper foils. Films are approximately 0.6 µm thickness and exhibit randomly oriented equiaxed BaTiO3 grains. The BaTiO3 films are sintered in a high temperature nitrogen-based atmosphere such that copper oxidation is avoided. The high sintering temperature,as compared to typical thin-film processing,provides for large grained films with properties consistent with bulk barium titanate-based capacitors. Grain diameters are between 0.05 and 0.2 µm depending on sintering temperature,dopant level and type. The dielectric constant ranges between 800 and 2000,representing capacitance densities in excess of 1µF/cm2. Loss tangents are less than 2.5%. Temperature dependent measurements on pure barium titanate films indicate a ferroelectric transition near 100 °C with a very diffuse character. The Curie point may be depressed to lower temperatures with dopants. This early work on BaTiO3 based films on copper foil represents an important first step towards very high capacitance density embedded passive components.

Last spring at EXPO,embedded passives came into its own by being escalated from a sub-committee with 4 task groups to a general committee with 4 sub-committees. Dave McGregor of Dupont now chairs the new general committee D-50 with Richard Snogren of Bristlecone as vice chair. Under that we have:
D-51 Embedded Devices Design Sub-committee
Chair – Kim Fjeldsted of Arrowsmith
Chair – Richard Snogren of Bristlecone
D-52 Embedded Component Materials Sub-committee
Chair – Dave McGregor of Dupont
Vice chair – Rocky Hilburn of Gould
D-53 Embedded Devices Performance Sub-committee
Chair – Michael Luke of Raytheon
Vice chair – Sidney Cox of Dupont
D-54 Embedded Devices Test Methods Sub-committee
Chair – Jan Obrzut of NIST
Chair – Robert Croswell of Motorola
Sub-committee progress to date has been significant.
The D-51 design sub-committee had decided some time ago to start with a design guideline which is now known as IPC 2316,“Design Guide for Embedded Passive Device Printed Boards”. It follows the path of the HDI and microvia standards development of a few years ago. The design guideline is in its final “working draft” stage,ready to be submitted for “final draft for review” at the Fall 2005 Works meeting and will soon be sent out for “proposal for ballot”. The design standard activity will start up soon after the guideline goes for ballot.
The D-52 materials sub-committee has created two documents. IPC 4811 “Resistor Materials for Rigid and Multilayer Printed Circuit Boards” is currently in its 5th working draft status and IPC 4821 “Capacitor Materials for Rigid and Multilayer Printed Circuit Boards” is in the “proposal for ballot” status.
The D-53 performance sub-committee has in the early working draft stage,IPC 6017 “Qualification and Performance Specification for Printed Boards Utilizing Embedded Devices”.
Finally,the D-54 test methods sub-committee has created and received approval for IPC TM650 Test Method 2.5.5.10 “High Frequency Testing to Determine Permittivity and Loss Tangent of Embedded Passive Materials”.
Test Method 2.5.7.2 “Dielectric withstanding Voltage for Thin Embedded Capacitor Layers for Printed Circuit Boards (PCBs)” is in working draft number 3 status.
Underwriters Laboratories has continued its participation in committee and sub-committee activities.

x

Traditionally microvias have been considered to be the most reliable interconnect structure within a printed wiring board (PWB). With the advent of lead free assembly the vulnerability of high density interconnects to fail has increased,due to the elevated temperatures experienced during surface mount assembly and rework. Throughout the past 18 months microvias have been found to fail during assembly and in their end use environment. This paper outlines a case study of microvia failure; reliability test methods,failure analysis,fabrication process considerations,and assembly process considerations for tin/lead and lead free application and problem resolution of microvia reliability issues.

The following report is fundamentally focused on how three popular lead-free alloys react in a wave solder application. The alloys were SAC305,SAC405 and a proprietary,low silver SAC alloy. In the process of attaining that goal,a flux selection methodology,and a study of top convection pre-heat were required. These three subjects are included in this report. Existing wave solder machines,materials,and methods were modified and tested over this study. The study used only Bellcore approved no-clean fluxes. Statistical analysis of the alloy study data was completed. The conclusions drawn suggest that except for one point,at least the defect of excess solder shows that there was no significant difference between those alloys. The main effect plots of the process defects used in the study would be very valuable in directing effective corrective action. In the flux selection methodology,a large test population was reduced to a few final candidates at low cost with little machine time or expensive test vehicles. A very detailed and extensive study on top-side convection pre-heat,by itself and used with infra-red panels,proved the system superior to alternatives. The minimal thermal stress and exceptional uniformity in the pre-heat of the machine have significant effect in providing uniform and efficient product preparation for solder. While not part of the study,a potential issue with minor flaws from bare board fabrication,or possibly a moisture sensitivity issue in the board was discovered. The issue causes large voids.

x

x