Recent advances in chip technologies have prompted a rapid increase in the density of solder joints in electronic components. Further reductions in pitch are likely,leading to joint structures exhibiting sub 0.100mm (100µm) dimensions. EC legislation from mid 2006 bans the use of Pb,for most applications,in solders which means that next generation solder pastes will have to be Pb-free. One low cost assembly solution is stencil printing/wafer bumping of fine particle solder pastes. For ultra fine pitch applications this will present significant challenges and there is a requirement to understand the sub processes in stencil printing at ultra fine pitch. Paste roll; aperture filling/release; post print behavior and paste open time have been examined using fine particle Pb-free solder pastes,and solder paste rheology,particle size distribution,metal content,flux type and stencil aperture attributes have been investigated to provide ultra fine pitch solutions. In this paper we report that solder paste printing has been achieved at sub 100µm pitch using Pb-free solder paste with IPC type-6 (15-5µm) and type-7 (12-2µm) particle size distributions. For the type-6 paste,full array printing was achieved with 50µm deposits at 110µm pitch,and for peripheral printing patterns,60µm sized deposits at 90µm pitch. For type-7 paste sub 100µm pitch printing was achieved for full array patterns. The results satisfy the criterion that paste deposits can be produced at ultra fine pitch. Furthermore,subtle differences in the performance of type-6 and type-7 suggest that each is suitable for different specific application geometries. Reflow trials indicated that solderability of the small volumes depended heavily on reflow profile ramp rates and reflow atmosphere. Process models for introducing inert nitrogen reflow atmospheres are presented.

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A flexible circuit is more than just thin materials made into an interconnecting device. Understanding the characteristics of the materials and their properties versus circuit design type and requirements,are variables that circuit designers and fabricators should understand in order to build the best performing and cost effective alternatives for their customers. Sometimes the requirements of a design are only vaguely identified and the information requested from a materials supplier is not always the most applicable for the desired design and application. Over or under performance is designed in,requiring several iterations of building and testing to get to the most desired cost effective end result. Prototyping with one material type and then going to production with another material type also is cause of concern for the end user. Not all materials are the same,even when they are “generically” lump ed into groups for convenience sake.

Two emerging board technologies,embedded passives and embedded optical waveguides,have the potential to change the way that printed wiring boards operate. No longer will interconnects be relegated to copper,but true passive electrical functionality will be incorporated into the board. Some high speed electrical interconnects may actually be replaced with pulses of light guided through transparent optical materials built into the board. These technologies are reviewed in simplified form,and the implications for board designers are examined.

Embedding resistors right into the printed circuit board substrate is not new,but it is gaining momentum as a rapidly
emerging and pivotal technology for the PCB industry,perhaps preceded only by the plated thru hole in the 50s and
microvias in the 80s. Embedding resistors requires designing resistors. Designing resistors requires understanding the resistor manufacturing process. Resistor materials are available in a wide range of values and technologies. This paper is written from a design for manufacturing perspective and includes guidelines for designing resistors with commercially available materials and manufacturing technologies to embed directly into the PCB substrate.

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As IC technology advances,electronic packaging for the ICs has had to advance as well. The package methodology has become technically more sophisticated and physically more complex. For many IC package applications,the lead-frame package technology of the past is not adequate. The Ball Grid Array (BGA) and Chip-Scale Package (CSP),on the other hand,are seen by many as the most viable solution for improving both functionality and performance. Array package technology is well established in the industry and the market growth for the BGA families has exceeded forecast. The array package technology and methodology has evolved throughout the past decade and many of the newer generations of BGA and CSP devices have become smaller and adapted finer contact pitch than their predecessors. The finer contact pitch BGA package enables the IC manufacture to meet the demand for higher I/O need for the mo re complex applications while maintaining a relatively small package outline. By adapting a finer contact pitch,however,can dramatically affect the methodology used in board design and assembly. Because of the higher contact density made possible by array type packaging,design specialists have realized that the higher density land pattern geometry significantly effects PC board routing efficiency and can definitely impact fabrication cost. When adapting BGA and chip-scale BGA packaging in particular,one must consider board fabrication tolerances and provide the necessary physical features needed for assembly machine processing. For assembly process control,land pattern geometry is of primary concern because it is directly related to solder attachment uniformity. This paper will review BGA/CSP applications,packaging standards and package assembly methodology,furnish circuit routing guidelines for array packaged devices and review recommendations for design defined in IPC-7095A,the Standard Guideline for Design and Assembly Process Implementation for BGAs.

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With the advent of CAD and CAM tools,the need arose for a more complete method of data transfer. As layer count
increased,the number of files increased. As trace size and spacing began to decrease,the Gerber file size increased. The need
for a better method of Data Transfer was recognized. The search for the Data Transfer Solution began.
IPC develop the GenCAM Initiative with a program to address the Data Transfer Solutions (DTS) with DTS ’97,DTS’98,
DTS’99,DTS’00,DTS ’01,DTS ’02… The idea behind the DTS was to parse large data files into an ASCII formatted,
process oriented segmented file. At the same time,Valor was developing the ODB+ format for its tools. And the industry
used Gerber because it was okay.