With the advent of CAD and CAM tools,the need arose for a more complete method of data transfer. As layer count
increased,the number of files increased. As trace size and spacing began to decrease,the Gerber file size increased. The need
for a better method of Data Transfer was recognized. The search for the Data Transfer Solution began.
IPC develop the GenCAM Initiative with a program to address the Data Transfer Solutions (DTS) with DTS ’97,DTS’98,
DTS’99,DTS’00,DTS ’01,DTS ’02… The idea behind the DTS was to parse large data files into an ASCII formatted,
process oriented segmented file. At the same time,Valor was developing the ODB+ format for its tools. And the industry
used Gerber because it was okay.

X

The migration to Lead Free raw materials in the Electronics Industry will happen faster than the date proposed in the original
draft of the legislation. A true Pb-free solution for product such as high end and volume server and desktop requires printed
circuit boards and electronic packages to be totally free of lead and compatible with the higher processing temperatures.
Raw materials such as solder paste are under stringent characteristic assessment to fulfill optimal solder joint quality and
reliability in mechanical strength and lower ionic and organic residue contamination. Characteristics such as printability,
stencil life & cleaning,tackiness,slump,viscosity,wetting,solderability,copper mirror corrosion,thermal optimization,
SIR/EM,ionic and organic contamination etc of both no-clean and aqueous solder pastes will be studied.

The Lead-free electronics manufacturing has become a reality. As of this writing,a few manufacturers have rightfully
reported their total completion to Lead-free production across all facilities,and some have reached partial implementation.
This paper focuses on replacing63Sn37Pb (or its equivalent) solder joint material and crucial manufacturing practices without
using a higher process temperature. The paper also presents some exemplary real-world production results of the drop-in
manufacturing by using the properly selected Lead-free solder alloys that are able to perform as a direct replacement for
63Sn37Pb solder joint material. Based on the 14-year systematic and sustained study of Lead-free solder materials in
conjunction with the 23-year SMT manufacturing establishment,the fundamental material properties and mechanical
behavior of the drop-in materials in relation to production and reliability will also be briefly summarized.

This paper will demonstrate the effect high reflow temperatures in lead free processes will have on the reliability of printed
circuit boards from a broad range of laminate materials for both traditional and lead-free processes. The focus will be on 24
layer boards of high thickness (3.2 mm) and high aspect ratios (5.21:1 and 10.42:1). The test boards were preconditioned
through six reflow cycles to simulate assembly and rework processes for both traditional and lead-free processes and then
tested using IST.
The results showed that raising the reflow temperatures from standard tin-lead to lead-free had a significant effect on the
reliability of PTVs,regardless of the laminate materials used. The results also showed that traditional and even some leadfree
materials did not survive the temperature increase when measured against industry standards.

Motorola has been using embedded polymer thick film resistors on immersion silver-plated copper terminations in products
for four years,and in the past year other firms have begun using this technology in their products. It is available to any
electronic equipment maker from multiple board suppliers. Highly reliable resistors with values ranging from ohms to megaohms
can be embedded in conventional HDI/FR-4 multilayer boards,providing cost savings and product size reduction. In
this paper we present recent improvements in resistor materials and design. Resistor value predictability is improved with a
simple innovation in termination design and the segmenting of low aspect ratio resistors. Resistor value distributions are
improved with more thixotropic inks. Combined,these improvements allow 10-20% untrimmed tolerances (depending on ink
resistance and production volume) for 0.25-mm-wide resistors. Tighter tolerances are possible with laser trimming.

Novel configurations of decoupling capacitors were formed by anodizing Ta,resulting in Ta2O5 films 2000 Å thick and k =
23,giving about 110 nF/cm2. Since the dielectric is very thin,the parasitic inductance is almost unmeasurable,and is shown
by simulation to be less than 1 pH/square. Breakdown voltages are around 30 V and leakage at 5 V is less than 0.1 µA/cm2.
The total ESR is dependent on the plate thickness,but can be less than 10 mO. Since the material is paraelectric,there is no
significant falloff of dielectric behavior at frequencies well over 10 GHz. The capacitors are formed on flex with closespaced,
alternating contacts to minimize contact inductance. The assemblies are designed to be included in a polymer-based
BGA stack to provide ultra-low inductance as close to the chip as possible. In this presentation,the reasons for using these
materials and configurations are presented from the point of view of electronic performance,reliability,and
manufacturability.

We have previously published our work on developing thin substrates for use as embedded capacitor layers. Based on this
work we have continued to characterize the performance and reliability of these materials.
We will discuss the experiences of PCB shops in processing the material and review the results of the various reliability
studies. Also,additional test vehicles have been processed for testing at high frequencies.
Customers have requested even higher capacitance values. We continue to work on making thinner dielectrics,and thus raise
capacitance,but it is believed that loading the polymer with high dielectric (Ferroelectric) particles will provide the best
values for this type of capacitor. We will exam the effect of loading the polymer with High Dk particles and compare the
positive and negative aspects of using filler.
The results of our internal and external testing (and a comparison to existing and developing capacitor materials) will help
determine what benefit(s),if any,a high speed system would get by using a high Dk filler polymer substrate.

The newly developed Ohmega-Ply “Resistor-Built-in-Trace” technology uses low-ohmic resistive materials for embedded
resistors congruent to the circuitry in a multilayer PCB or HDI substrate. High frequencies and miniaturization has created
the need for miniature resistors. Until now,the paradigm of the shape of an embedded resistor was the same as an SMT
resistor,a discrete-like component having a definite width and length and occupying space. The new “built-in-trace”
technology uses the signal path itself for the resistor and,therefore,requires no additional board area,thereby enabling higher
I/O and component densities and reduced form factors. A “virtual component” is created by the gap in the conducting trace
crossed only by the thin-film low ohmic resistive layer. No terminating conductive pads are required,the trace merely
continues along its path. The CAD layout is simplified by the elimination of the resistor footprint. Low ohmic materials of 10
ohms per square or less yield tight tolerance of 3% or less so that the tolerance of the resistive element is equal to or better
than the tolerance of the characteristic impedance of the circuit trace thereby improving signal integrity. The equivalency of
the resistor width and trace width tolerances means that any manufacturing process capable of producing a controlled
impedance PCB will be capable of producing the built-in-trace resistors to the required tolerance without resistor trim.

This paper will discuss the use of thin film buried resistors and thin core plane pairs in high layer count high reliability
printed wiring boards used in single and double sided surface mount assemblies. Very high thermal stress durability is
required for assembly and component repair/replacement. The high density multilayer and sequential built designs of 14-26
layers use a combination of buried vias,blind vias,thin cores,several layers of buried resistors and thin core plane pairs to
meet controlled impedance and circuit performance. The design of the resistors for BGA pull down terminations and for incircuit
resistors contain various values and tolerances. Overall thermal performance of the board is critical to the product
reliability requiring the buried resistors and thin core plane pairs to also survive extreme thermal exposure. Thermal stress
testing,as required by the applicable standard,was extended to multiple times in order to determine product robustness for
laminate defects,plating integrity and inner plane connection durability. In addition,Current Induced Thermal Cycling
Testing can be performed for comparative analysis. Special test coupons can be designed that duplicate the actual conditions
of the board and allow the buried resistor layer to be present in the microsection for evaluation during the required
inspections. As with conventional printed wiring technology,failures do occur,but typically only after extreme thermal stress
or rework. Failure analysis was performed to identify the cause. Pictorial views of the component density,resistor designs,
layer stackup,and failure analysis activity are contained in the paper. This paper will show that embedded passive technology
can be implemented with success for high density,high layer count and high reliability printed wiring boards.