Conductive Anodic Filament (CAF) is a failure mode in printed wiring boards (PWBs) which occurs under high humidity and
high voltage gradient conditions. The filament,a copper salt,grows from anode to cathode along the epoxy -glass interface.
First identified by Bell Labs in 1976,this failure mode had also been investigated by Der Marderosian at Raytheon who termed
it the "punch through" phenomenon. Early studies of CAF were confined to unprocessed PWBs,but in the 1990's Jachim
identified the effect of solder fluxes in enhancing this failure mode. This presentation will review the history of CAF from its
identification in the 1970's,to the statistical analysis of its failure mode and the factors that enhance its formation.

Area Array Packages (AAPs) with 1.27 mm pitch have been the packages of choice for commercial applications; they are now
starting to be implemented for use in military and aerospace applications. Thermal cycling characteristics of plastic ball grid
array (PBGA) and chip scale package (CSP) assemblies,because of their wide usage for commercial applications,have been
extensively reported on in literature. Thermal cycling represents the on-off environmental condition for most electronic
products and therefore is a key factor that defines reliability.
However,very limited data is available for thermal cycling behavior of ceramic packages commonly used for the aerospace
applications. Thermal cycles and vibration test results for ceramic ball grid array (CBGA) with 361 and 625 I/Os were reported
previously by this author and the trends for cycles-to-failures for four different temperature ranges were established. This paper
presents thermal cycle test results for a ceramic column grid array (CCGA) and its PBGA version,both having 560 I/Os,
exposed to two different thermal cycle regimes. One of the thermal cycles was that specified by IPC 9701,i.e. –55 to 125°C; the
other was in the range of –50 to 75°C representing the qualification for the specific mission. Per IPC 9701,test vehicles were
built using daisy chain package and were continuously monitored. The effects of many processing and assembly variables
including corner staking,commonly used for improving resistance to mechanical loading such as drop and vibration loads,
were also considered as part of the DOE test matrix. Optical photomicrographs were taken at various thermal cycle intervals to
document damage progress and behavior. A representative samples of these along with cross-sectional photomicrographs at
higher magnification taken by scanning electron microscopy (SEM) to determine crack propagation and failure analyses for
packages with and without corner staking are also presented.

Plastic IC Packages are generally considered to be not as reliable as their ceramic counterparts. One of the major reasons is
the question of hermeticity. Plastic materials generally allow moisture/ humidity to penetrate through the body of the
package. When moisture reaches the chip,the chip gets damaged and fails. With ceramic packages,moisture is kept out and
the chips last much longer.
However,if we analyze the problem more closely,we would find that the penetration of the moisture into the package is
accelerated by “Micro-Cracks” that occur at the interface between the metal leads and the plastic encapsulation,where the
plastic material hugs and wraps around the leads. The tiny cracks,in essence,separate the plastic material from the lead
metal. The cracks start at the edge of the plastic body and then propagate gradually inwards. Moisture gets into the cracks and
follows them until it reaches the chip and damages it.
Moisture penetration via the cracks is much faster than through the solid plastic body. So,if we reduce or eliminate the
chance of the occurrence of these micro cracks,then we would prolong the life of the plastic packages.
The author believes that the present design of plastic packages contributes largely to the creation of the micro-cracks,
especially in the presence of thermal cycling and similar environmental conditions.
The author has arrived at a solution that would reduce the occurrence of such cracks,thus improving the reliability of plastic
packages. This paper will describe the proposed solution.

The assembly of thinned silicon die (25-100µm) onto flex substrates provides options for ultra thin,flexible electronics for
applications ranging from smart cards to space-based radars. For high density applications,3-D modules can be fabricated by
stacking and laminating preassembled and tested flex layers then processing vertical interconnections. This paper describes
processes for flip chip assembly of thinned die to polyimide and liquid crystal polymer (LCP) flex substrates.
Two assembly approaches have been developed for use with polyimide and LCP flex substrates. In the first approach,the
solder bumped die are reflow soldered to the patterned flex. A fixture is required to maintain the flex substrate flat during
reflow. Reflow is followed by underfill dispense and cure. The underfill dispense process is critical to avoid underfill flowing
onto the top of the thin silicon die and will be discussed. In the second approach,vias are etched through the polyimide or
LCP,exposing the underside of the contact pads. Solder paste is squeegeed into the vias,reflowed and cleaned,creating
solder ’bumps’ in the via. Die with low profile solder bumps created by immersion soldering are fluxed,placed and reflowed.
The die is then underfilled. This approach produces a lower total assembly thickness.

Thermoset epoxies,discovered nearly 80 years ago,remain the workhorse materials for electronic packaging and printed
circuit boards,but this may change with increasing technical,economic and regulatory demands. Modern halogen-free
thermoplastics boast superior properties and automated high-efficiency high-volume processes. Injection molding can readily
produce intricate 3D structures suitable for packaging and 3D molded circuits. Although there is a well-established packaging
infrastructure geared to thermoset epoxies there is a much larger world-wide manufacturing base that excels in thermoplastics.
Nearly 16-billion pounds of thermoplastics are molded into parts each year in the USA alone; 30 times higher than for
epoxies. The time may be right for adding thermoplastic packages,interconnects and circuitry to 21st century electronics.
This paper will discuss concepts,novel designs,new processes and the advancements for injection molded packaging and
highlight their impressive attributes; the lowest moisture uptake,the fastest processing and the highest stability in the world
of polymers. While MEMS packaging will be a central theme,general component packaging will also be discussed including
power packages and camera modules. The discussion will include the development of new BGA concepts that utilize
automatic insert-molding of tiny metal balls to create the 1st and 2nd level interconnect system. Assembly topics will cover
package sealing methods that include laser welding.
New Multi-Chip Package (MCP) ideas based on insert-molded flex will be described that could find use in stackable designs.
Hermeticity is discussed using data to show that plastics are near-hermetic but do not yet pass MIL-STD levels. But,future
work with barrier coatings may eventually lead to a low cost full hermetic plastic package. And finally we’ll look at 3D
molded circuits,now called MID (Molded Interconnect Devices),and search for new applications. Conductor patterning
methods include molding with plating-catalyzed resin and direct laser writing. We will also consider the idea of combining
molded circuitry and packaging for maximum synergy.

Hand-held communication and entertainment products continue to dominate the consumer markets worldwide,and with each
generation,companies are offering more and more features and/or capability. Even though the actual functionality of the new
product offering expands,the customer is expecting each generation to be smaller and lighter that its predecessor. More
functionality typically requires additional or more complex electronics and greater memory capacity. Increasing functional
capability,however,can adversely impact the products size as well as manufacturing cost. The challenge manufactures face
when competing in the world marketplace is to offer a product that will meet all performance and functionality expectations
within budget and without increasing product size.
This paper will explores a number of system level applications developed within Tessera’s Package Engineering Service
Laboratories and examine the results of extensive computer modeling as well as review the data compiled from electrical
performance and physical stress testing.

Meeting RoHS requirements is confusing at best. Currently,RoHS bans the presence of 6 substances,: Lead (Pb),Cadmium (Cd),Mercury (Hg),Hexavalent Chromium (Cr6+),Polybrominated biphenyl (PBB) and Polybrominated diphenylether (PBDE). As of 18 August 2005,the European Union (EU) amended the RoHS document with maximum concentration values (MCVs) of 1000 ppm for 5 of the substances; Pb,Hg,Cr6+,PBB & PBDE and 100 ppm for the 6th substance; Cd at the homogenous level. Other documents within the EU and member states have defined MCVs,but there is not total agreement between EU Directives and the member states on the maximum threshold values. With the delay of defined RoHS thresholds,other regions of the world are defining MCVs,but without universal agreement. Companies in the electrical and electronics equipment (EEE) industry are subsequently incorporating their understanding of MCVs into company specifications and requiring the suppliers to meet them.
What are the existing EU Directive requirements? How do they apply and what thresholds should be used for electrical and electronic products? This paper will discuss the RoHS 6 substances,thresholds as stated in the EU,common company defined threshold differences and the issues they cause. It is not all inclusive since laws and directives are constantly changing,evolving or being released.

This paper describes flexible printed circuit boards,used as “Product Boards” or “Interposers”,chip mounting structures. Traditionally,flexible circuit boards are made with polyimide dielectric cores. These are made either by lamination processes of a foil with adhesive,or the build-up of the copper from an “adhesiveless” process

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Hand-held communication and entertainment products continue to dominate the consumer markets worldwide and,with each generation,offering more and more features and/or capability. And even though the actual functionality of the new product offering expands,the customer is expecting each generation to be smaller and lighter that its predecessor. More functionality typically requires additional or more complex electronics and greater memory capacity. Increasing functional capability,however,can adversely impact the products size as well as manufacturing cost. The challenge manufactures face when competing in the world marketplace is to offer a product that will meet all performance and functionality expectations within budget and without increasing product size. Increased electronic functionality can be achieved through the development of more complex silicon integration (system-on-chip) but that route generally requires a great deal of capital resources and time. With the rapid deployment of new products from an ever growing number of competing companies’,time-to-market can be the difference between leading and following. For that reason,many manufacturers will rely heavily on more innovative IC package solutions,solutions for integrating a number of already proven functional elements within a single-package outline. When adapting multiple die configurations,each package becomes a fully tested subsystem that can be certified by the supplier before board or module level assembly. To achieve system level integration and miniaturization goals,companies’ can now rely on a combination of multiple-die package solutions and high-density flexible film based substrate methodology. For many applications,the multiple-die package is actually proving superior to the system-on-chip alternative because it minimizes risk and economically integrates several different but complementary functions. In the case of memory for example,multiples of the same function can be vertically stacked for increased density. This paper will explore three flexible film based multiple die system level applications developed within Tessera’s Package Engineering Service Laboratories.