The overall mission and foundation of business today,as it was yesterday and undoubtedly will be tomorrow,is to maximize
customer service. Customer Relationship Management (CRM),although a relatively new term in the world of Information
Technology and Enterprise Wide Systems,has always been the foundation for business success. The basic premise of CRM
is giving the customer what they want,when they want it and how it should be; for business nothing different yet a remaining
challenge. With the ever-expanding use of technology,there is an overabundance of data and a challenge to disseminate this
data into information.
It is almost daily that we read or hear of Information Systems not fulfilling the expectations established at the time of
acquisition. In fact,despite the most diligent efforts in defining requirements,evaluating options and selecting systems,the
probability of system implementation and utilization issues and higher than expected cost investments is extremely high.
Accepting the premise that the customer is the reason for a business to exist,the justification for CRM is thereby validated.
However,incongruent departmental goals and objectives make the probability of a successful CRM strategy difficult. The
balancing and integrating of company and departmental goals with the capabilities of Information Systems and the
organizational infrastructure,is the topic of this discussion.

Today,there are only three certainties in a circuit board market that for the last three years has proven anything but certain:
death,taxes,and military business. As the overall North American electronics market has declined and manufacturing
continues to shift to lower cost geographies,circuit board manufacturers have been searching for answers. Should North
American manufacturers give up and concede defeat or is there a sustainable,growing business model that justifies the
attention of U.S. manufacturers? The answer is simple; it’s the circuit board market for military products,which over time is
taking on an increasingly important role in our industry.

To estimate the ability of a process to perform according to the product’s design (i.e.,specification),process capability
indices (Cp,Cpk,etc.) are used. What most people fail to realize,however,is that the actual process capability indices should
be based on population parameters (e.g.,mean and variance),but we rarely,if ever,have that information. In fact,it is almost
always the case that samples from the population are chosen to estimate the process’s parameters and,therefore,the process
capability indices that are typically reported are actually process capability estimates.
This paper will introduce (to the new reader) or refresh (to the learned reader) the basic concepts and formulas for process
capability estimation. Subsequent to this,formulas for process capability confidence intervals (CIs) will be provided. An
experiment is presented to highlight the effect of sample size on the process capability estimates and CIs.
This paper does not intend to introduce new formulas for process capability CI generation. In fact,these formulas have been
around for quite a number of years. Surprisingly,however,most of the applied work in electronics manufacturing articles that
is mentioned with regard to process capability fail to use these formulas. The purpose of this paper is not to highlight the
many practitioners and researchers that have failed to mention process capability confidence intervals in their work (we also
would be included in that list),but it serves to bring to a wider audience (in particular,the electronics manufacturing
audience) the suggestion to utilize these formulas so that they and their customers (or suppliers) can get a broader picture of
process capability.

We often hear or use the terms “World Class Manufacturing” or “Best in Class Manufacturing” in reference to our
manufacturing operation or perhaps a competitor’s or supplier’s manufacturing operation. However no formal industry
recognized definition of “world class” or “best in class” manufacturing exists. There certainly are numerous industry
recognized evaluation and certification programs such as ISO and the Malcolm Baldrige Award,but do any of these
evaluations and certifications anoint a particular manufacturing operation as “World Class” and/or “Best in Class”? If not
what is the true measure of a world class manufacturing operation? Of course our customers are the final judges of our
performance,but what should we be doing to maximize the satisfaction of our customers?
One of the key factors if not THE KEY FACTOR in attaining world class or best in class manufacturing status is the
approach to developing,controlling,and improving the manufacturing process. A true world class manufacturing operation
must have a Proactive Manufacturing Operation Culture.
This paper will detail how a manufacturing operation can transition from a reactive manufacturing culture to a proactive
manufacturing culture.
Specific issues discussed will be:
o How to recognize a proactive manufacturing culture
o The specific training,management,and organizational issues that can make this transition successful.
o Who must be involved?
o How to get started?
o What are the specific actions that must be completed to achieve the transformation?
o How to institutionalize (maintain) a proactive manufacturing culture?
o What are the process performance benefits of a proactive manufacturing culture?

Epoxy molding compounds are used extensively in the electronics industry to encapsulate surface mount Integrated Circuits
(ICs). The primary purpose of encapsulating the SMT package using these molding compounds is to protect them from
adverse conditions. Though the mechanical and electrical properties of epoxy make it suitable for electrical and electronic
applications,epoxy is not a hermetic encapsulant and will allow moisture to diffuse into the components. The absorbed
moisture affects the properties of the material especially when the components are reflowed and can lead to failures like pop
corning and package cracking. Moisture induced reflow failures due to pop corning and delamination in plastic encapsulated
SMT packages has been a significant issue in the assembly of PCB’s. The impending transition to Printed Circuit Board
(PCB) assembly involving more rigorous reflow conditions,accentuates the need for study on the integrity of such packages
during and after assembly. This research involves the study of moisture and reflow sensitive behavior of an array of plastic
encapsulated packages to assess their performance at both eutectic and lead free reflow conditions

Successful reflow soldering is a key to productivity and profitability,yet many assemblers may be using a nonoptimized
reflow profile.
Years ago,when IR ovens were the norm and solder pastes were relatively unsophisticated,initial reflow profiles were
developed (Figure 1). These profiles were called “ramp to dwell – ramp to peak.” Since then,IR technology has bowed to the
superior capabilities of convection technology,with its dramatically different heating mechanisms. Additionally,solder paste
formulation technology has evolved significantly in the same time.
Recent work by Lee1 indicates that these IR reflow profiles are not optimum for convection ovens and modern solder pastes.
Through the analysis of defect mechanisms,his work reveals that a gentle ramp to about 175°C,and a very gradual rise
above liquidus,followed by a ramp to a peak temperature of 215°C will result in the highest yields. An example of the “Lee
Profile” is shown in Figure 2. When one considers that almost all ovens used in SMT assembly are convection ovens,this
distinction in reflow profiles is very significant.

When transitioning to lead-free reflow,consideration should be given to the additional costs of operation,above and beyond
material costs.1 Impacts to the overall reflow process should be carefully reviewed. Due to the higher operating temperatures
required for lead-free processing,and the suggested use of nitrogen,equipment cost of ownership could dramatically
increase.2
This paper evaluates power consumption rates for both lead-free and traditional leaded reflow processing along with
reviewing a unique,closed-loop nitrogen control design that automatically varies the flow of nitrogen to maintain ppm levels
and reduces nitrogen flow during idle states. Data obtained under loaded/unloaded conditions will be presented in relation to
varying power consumption results. A cost of ownership model is also used to predict additional expenses over time,along
with suggestions on equipment feature/option considerations for lead-free reflow processing.

The impedance and electrical property variation resulting from spatial patterns in woven glass reinforced laminate materials
are greatly impacting high speed interconnect designs. As the transfer rates of PCB interconnects increase,the allowable
timing tolerance between different nets on the PCB is shrinking to a point where the resulting local variations in dielectric
constant due to variations in woven fabric density are becoming a limiting factor. These local variations place limits on
transfer rates of PCB interconnects and are shown to be a constituent of impedance control within a PCB layer. The spatial
properties are shown to be dependent on the glass cloth and resin system selection,design layout rules,and pcb stack-up
parameters. This paper details the electrical property variations that exist in common laminate material and glass styles and
discusses the impact on IO bus modeling and lay-out design.

This paper will discuss the two primary transmission components that concern designers today. These components affect the
signal integrity of all high-speed transmissions in printed circuit boards (PCBs).
The dissipation factor (Df) is a laminate material parameter that determines the losses assigned to the laminate surrounding
the transmission line. For a good dielectric,the conductivity,which determines Df,should approach zero. Signal processing
at high speed requires that the dielectric constant (Dk) that is perceived static and the effective dielectric constant (Er') that is
perceived active,be measured so that the designers have an accurate model to predict delays and impedances. For these highspeed
signals,the delay (phase or propagation) is critical to the success of any high-speed transmission path. Delays through
the transmission line can affect skew,influence noise immunity and may reduce eye widths. An accurately measured Er'
obtained from signal delay is needed to ensure that no impedance mismatches associated with laminates are found along the
transmission path.

Efforts to reduce high frequency signal losses associated with dielectric materials have driven development and
commercialization of more cost effective low loss laminate materials. These developments have been facilitated by the use of
a variety of standardized dielectric test methods.
As dielectric losses are reduced,the relative contribution of conductor materials to overall loss increases. In order to better
understand the implications of conductor material and surface finish choices,efforts have been made to quantify the impacts
of these factors on loss.
While conductor material and surface finish influences may be directly measured using printed wiring board test structures,
interpretation of the results are complicated by the influence of both the laminate material and the particular geometry
selected for the test structure (microstrip versus stripline versus differential pair). The results of such measurements
accurately reflect the specific test geometry examined,but are difficult to extrapolate to different systems.
An alternative test approach has been identified which provides a measure of conductor performance,decoupled from both
system geometry and the influence of laminate material.
The basic test method described in IPC TM-650 2.5.5.5.1. (Stripline Test for Complex Relative Permittivity of Circuit Board
Materials to 14 GHz) has been modified by comparing the results obtained using ideal smooth copper conductors and with
those obtained with samples of alternative conductor materials,while maintaining a constant dielectric material. Changes in
the resonator loss factor between the two tests allow calculation of the relative performance of the alternative material versus
the ideal conductor.
Using this test method,the performance of a number of surface finishes,PWB foil treatments and inner-layer adhesionpromotion
processes relative to a control smooth copper surface are reported.