Boeing Commercial Electronics (BCE),a subsidiary of The Boeing Company,is a leading supplier of avionics and
cabin management systems for the Boeing family of commercial airplanes. Boeing specifications require conformal
coating on electronic assemblies to protect them from moisture and contamination. To meet this requirement,BCE
sprays a solvent-based acrylic (AR) conformal coating on their printed wiring assembles (PWAs). In anticipation of
further EPA spray coating restrictions,BCE launched an extensive test program to select a low VOC (volatile
organic compound) conformal coating. BCE customers require a coating that is easily repaired. The selection of the
low VOC coating is further constrained by a Federal Aviation Administration (FAA) flammability requirement for
materials used on commercial aircraft. In order to systematically select the best conformal coating,a phased
approach was adopted: Phase I - Industry Survey,Phase II -Evaluation of Factory Acceptance,Rework and
Flammability Testing,Phase III - Engineering Reliability Testing,Phase IV - Qualification,Implementation and
Optimization. The scope of this paper encompasses Phase I through Phase III.
In Phase I,a comprehensive industry survey of available conformal coatings was completed. Fifty-five potential
coatings were ranked based on the following attributes: (1) material type (2) percent solvent (3) Underwriters
Laboratory (UL) flammability recognition (4) ease of repair (5) 1 or 2 part coating system (6) viscosity (7) cure (8)
impact to production,customers and service centers (9) equipment compatibility and (10) cost. Based on these
attributes,the list of coatings was down selected to eleven coatings [one water-based acrylic (AR),three UV curable
acrylated urethanes (AR/UR),and seven silicones (SR)] to advance to Phase II.
The objectives of Phase II were accomplished by breaking the testing into three smaller parallel efforts. In Part A,
populated test boards were coated at the suppliers’ facilities and then used to determine the rework operator’s
acceptability of removal and rework. In Part B,test boards were coated on-site to provide BCE’s conformal coating
operators an opportunity to evaluate the coating for ease of use and human factors. In Part C,flammability tests were
completed. Based on the combined results from Parts A,B,and C,six coatings (1 water-based acrylic,2 UV curable
acrylated urethanes,and 3 silicones) were selected to advance to Phase III.
Phase III was broken in two parts. In Part A,coatings were tested for compatibility with materials utilized in
production of PWAs. In Part B,the following engineering reliability tests were conducted: (1) Fluorescence (2)
Appearance (3) Moisture and Insulation Resistance (4) Thermal Shock (5) Temperature & Humidity Aging
(Hydrolytic Stability) (6) Tape Adhesion (7) Surface Insulation Resistance (SIR).
Based on the combination of evaluation completed in Phase II and III,a 100% solids (0% VOCs) UV curable
acrylated urethane was down selected for Phase IV (qualification,implementation and optimization). Currently,
BCE is continuing the effort by examining implementation options. Several other low VOC conformal coatings
were qualified and added to the BCE specification for use on special applications.

The use of no-clean solder paste and flux has become widely accepted as a cost saver in the SMT assembly process.
The presence of solder flux residues,solder mask,underfill or any SMT material not accounted for in the design can
have a deleterious effect on the performance of a circuit at high frequency. It is possible though to build a low loss
RF circuit by judicious choice and/or application of SMT materials or by accounting for their presence in the design
stage.1 A further question arises as to the effects of these materials on the long term performance of high frequency
circuits. For low frequency circuits flux residues need only remain non-conductive when exposed to the harsh
environments of accelerated aging tests. High frequency circuits,though,are much more sensitive to their
surrounding environment than DC circuits. Moisture absorption,flux migration/volatilization,and metal oxidation
can all have a dramatic effect on the dielectric properties of a circuit. This in turn will change the characteristic
impedance of the circuit causing it to be “out of tune”.
We have investigated this subject by building and characterizing simple high frequency circuits that have been
processed with a variety of solder pastes and fluxes. These boards were then conditioned at elevated temperature and
humidity to ascertain if this has a measurable effect on high frequency performance.

The ability of a solder paste particles to coalesce and wet the Printed Wiring Board (PWB) and component lead is
key to proper solder joint formation. Robust solder paste performance is needed over a range of typical
manufacturing conditions. The following factors have been varied; 1) ambient temp and humidity,2) exposure time
prior to reflow,3) reflow dwell time above liquidus and 4) peak temperature and 5) number of reflow cycles prior to
soldering. The wetting of a paste onto the copper pads/lands is affected by the solderability of the copper surface and
the reflow temperature settings that control the thermal profile. The main reflow parameters associated are the peak
temperature and dwell time above liquidus (183C for near-eutectic 63WT%Sn/37Wt%Pb). The solder balling
tendency is best characterized on a non- wettable substrate and is dependent on both the time of ambient exposure
and the ambient humidity level,with potential problems at both high and low humidity. The performance of the
solder paste could be associated with the individual main effects of changing one factor,as well as the interaction
effects of changing two factors at once. The Institute for Interconnecting and Packaging Electronic Circuits (IPC)
specifies test methods that allow subjective evaluation of individual effects under near optimum processing
conditions.1 This research involves a quantitative statistical approach for the evaluation of wetting and solderballing
behavior of solder pastes using a Design of Experiments (DOE) and ANalysis Of VAriance (ANOVA).2 The test
conditions were based on a combination of IPC test methods and realistic manufacturing process conditions. The
quantitative main and interaction effects of the factors effecting solder wetting and solder balling were identified for
each paste considered.

Solderability testing is carried out at the IC (Integrated Circuit) manufacturer’s end to evaluate the quality of the IC
package terminals in terms of solder wetting ability. Current industrial standard procedures for solderability
testing—such as MIL-STD-883E and EIA/JESD22-B102-C—cover testing procedures for peripheral leaded
package types only. With the electronics industry’s recent moves towards lead-less packages and Pb-free soldering
processes,solderability issues of package terminals have become even more prominent,and universally accepted
procedures and standards of solderability testing for BGA (Ball Grid Array) packages even more urgent.
This paper describes process methodologies and their qualifications for solder joint strength and solderability tests
for BGA packages at PCB (Printed Circuit Board) level. These methodologies focus especially on BGA package
types with eutectic solder ball input/output terminals—e.g.,PBGA,Micro-BGA,FBGA,CSP,etc. Criteria taken
into account when developing the respective test methodologies included that they be practical and could be carried
out using standard SMT (Surface Mount Technology) processes and equipment. This paper concludes with
recommendations for 2 particular methodologies that proved to be the two most effective and reliable methods of
solderability testing of BGA packages on PCB board level.

National Electronics Manufacturing Initiative (NEMI) initiated six projects in late 2001 and 2002 addressing key
issues identified by the industry. These cover the areas of Fiber Management,Signal Integrity,Splicing,Selective
Soldering,Adhesives and Substrates. The objectives of the groups included structuring the key issues,collecting
data and presenting them in a form useful to members and to the IPC and other optoelectronics standards initiatives.
An update on the progress of each of these projects will be given.

High speed systems operating at speeds of 2GHz and above are placing increasing demands on the
specifications of substrates and packaging of
components used within these systems. BPA has
reviewed those systems that are driving technology
developments
These are:
• High end router
• Enterprise server – high end and blade
• Wireless base station
• Military and Aerospace control and
communication

We have organized in JPCA a committee for the standardization of optoelectronic assembly technology in
collaboration with JIEP (Japan Institute of Electronics Packaging) with cooperation of JEITA (Japan Electronics and
Information Technology Association),OITDA (Optoelectronic Industry and Technology Development Association
– Japan) and ACET (Association of Super-Advanced Electronics Technologies). We consider that our effort is to
compliment the similar effort to prepare IPC0040,the basic document in this area,and necessary specific
specifications. We are in contact with the IPC 5-25 Committee. The available information/documents we generate
may be shared with IPC and JPCA.
We will concentrate our effort to specify interface technology of packages and boards that may constitute the
standardization item 318,stated in IPC0040,“Methods for optoelectronic component attachment and alignment”,
including 1) Optical printed board (include optical Interface in the board) 2) Connector of board edge (Include
optical interface) and 3) Optical package (Include optical interface). The very details of the contents are to be
finalized,however,our schedule is to prepare relevant drafts within a half year time. This presentation is a status
summary prepared for IPC APEX 2003.

The OEM desires identified in the 2002 – 2003
roadmap clearly identify,through their emulators,the
present and future needs of the products that the
emulators represent. There are a total of eight
emulators. Each emulator is broken down into the
technical drivers that help identify the OEM needs
for the different time frames established for this
Technology Roadmap. The emulator technical driver
information is organized into four major areas. These
are:
• Design Issues
• Printed Board Technology Issues
• Board Assembly Technology Issues
• Printed Board Purchasing Issues
The emulator attributes in design include such drivers
as on-chip rise time,minimum voltages,thermal
dissipation factors,reliability issues,and maximum
board temperature requirements. Printed board
technology attributes deal with materials,board size,
layer count,etc.; board assembly technology
attributes consider number of components,number of
solder joints,and type of assembly; purchasing issues
deal with the cost per interconnect and if assembly is
recyclable.
The emulators represent a quantitative summary of
the expected changes in board,component,and
assembly technology from 2002 to 2012. These
changes are addressed in two different product
categories: Revenue Center of Gravity (RCG) and
State of the Art (SoA). Revenue center of gravity
products represent the bulk of revenue and are
considered to be conventional technology; state of the
art technology is in production by only a few
manufacturers. SoA technology represents less than
5% of the world’s production. Table 1 is the Mid Size
System emulator for this new roadmap.

Tin whiskers found in electroplated deposits are known to be single crystals which spontaneously grow. Thus
whisker growth can be regarded as a grain growth phenomenon. In this paper we examine whisker grain growth in
the context of the well-developed principles of recrystallization process as applied to bulk metals that have
undergone deformation and annealing. As a grain grows in whisker form,recrystallization process must take place
as tin atoms rearrange in to the lattice structure of the elongating grain. Peculiarities of tin deposit structure that may
cause whisker growth are discussed. Frank-Read source of dislocations is proposed as a possible mechanism for
whisker formation. The effect of various factors on whiskering is analyzed.
Recrystallization theory postulates that shear strain introduced by plastic deformation is stored in the metal in the
form of dislocations (lattice defects). In bulk metals,produced metallurgically from the molten phase,these lattice
defects usually are not present in noticeable quantity unless the material is subjected to cold work (plastic
deformation at temperatures significantly below melting point). In electroplated tin,however,the metal is formed at
the temperatures much below melting point. During plating,energy is stored in the deposit in the form of crystal
defects such as vacancies and dislocations. This causes the crystal structure of metal deposits to resemble the
structure of cold worked metals,and thus forms the starting point for application of recrystallization principles.
The second important factor that justifies the application of recrystallization/grain growth principles to whisker
formation is related to the low recrystallization temperature of tin. Recrystallization temperature is defined as the
temperature at which a particular metal with particular amount of cold deformation will completely recrystallize
within one hour. Typically,it can be estimated as between 0.4 and 0.7 Tm (where Tm is the melting temperature). It
is a well-known fact that in most metals,recrystallization occurs at elevated temperatures. For tin,however,the
recrystallization temperature is approximately 30°C,which means that recrystallization will spontaneously occur
around room temperature (above and below 30°C),reforming a strain-free structure.1
These two factors – strain stored in the deposits in the form of dislocations and recrystallization at room
temperature,substantiate the application of recrystallization process principles to whisker formation. But before we
elaborate on this hypothesis,let us briefly summarize the principles of recrystallization process.

Over the past years there has been consistent growth in the use of electroless nickel/immersion gold (ENIG) as a
final finish. The finish is now frequently being used for PBGA,CSP,QFP and COB and more recently gathered
considerable interest as a low cost under-bump metallization for flip chip bumping application.
One of the largest users for this finish has been the telecommunication industry,were millions of square meters
of PCBs with ENIG have been successfully used.
The nickel layer offers advantages such as multiple soldering cycles and hand reworks without copper
dissolution being a factor. The nickel also acts as a reinforcement to improve through-hole and blind micro via
thermal integrity. In addition the nickel layer offers advantages such as co-planarity,Al-wire bondability and the
use as contact surface for keypads or contact switching. Especially those pads,which are not covered by solder
need a protective coating in corrosive environment – such as high humidity or pollutant gas.
This paper describes the influence of co-deposited Phosphorus within the Nickel layer,regarding the influence
to the ENIG process itself (especially the corrosive attack of the immersion gold reaction) and the survivability
of PCBs in corrosive atmosphere.
Within this paper,different test methods are described and discussed to check the protective performance of a
high Phosphorus ENIG layer.