The hypothesis that the “whisker growth phenomenon” in electrodeposited tin is a re-crystallization process driven by stress
has gained popularity among leading research institutes and industrial laboratories. However,there exist varying opinions as
to the type of stress responsible for this phenomenon. Recently,various studies have demonstrated that compressive stress,
whether intrinsic or externally applied,is most likely the cause of whisker growth.
There are three main sources of compressive stress that a component finish experiences after plating. They are: stress
generated by intermetallic compound formation between the tin finish and the copper alloy substrate; mechanical stress such
as trim-and-form introduced in current manufacturing practice; and thermal stress generated by temperature cycling and
propagated into tin layer due to CTE mismatch among the constituent materials of a component.
It is well recognized that both IMC formation and CTE mismatch are largely affected by the substrate material and
underlayer/barrier between Sn and substrates,as well as aging conditions. In this paper,we attempted to understand the
relative contribution of stress generated from IMC and from CTE mismatch on various leadframe and connector substrates at
both isothermal and temperature cycling conditions. Ultimately,we hope to delineate the whisker accelerating factors to
provide input for the industry to derive a set of standard yet realistic whisker test methods.

Tombstoning of SnAgCu is affected by the solder composition. At vapor phase soldering,both wetting force and wetting
time at a temperature well above the melting point have no correlation with the tombstoning behavior. Since tombstoning is
caused by unbalanced wetting force,the results suggest that the tombstoning maybe dictated by the wetting at the onset of
paste melting stage. A maximal tombstoning rate is observed at 95.5Sn3.5Ag1Cu. The tombstoning rate decreases with
increasing deviation in Ag content from this composition. DSC study indicates that this is mainly due to the increasing
presence of pasty phase in the solders,which is expected to result in a slower wetting speed at the onset of solder paste
melting stage. Surface tension plays a minor role,with lower surface tension correlates with a higher tombstoning rate.
SnAgCu composition with a Ag content lower than 3.5%,such as 2.5Ag,is more favorable in terms of reducing tombstoning
rate with minimal risk of forming Ag3Sn intermetallic platelet.

Whilst the number of new ASIC designs has decreased over the last couple of years,there has been a dramatic increase in the
number of FPGA designs implemented. Not only have the number of designs increased rapidly,the complexity and also the
size of these devices have grown over this period. In the early 1980s,the first PLD devices had around 300 gates,while
today’s FPGAs exceed two million gates. Along with the increasing FPGA gate count there has been a corresponding
increase in the number of available I/O pins such that there are over 2000 pins available on the largest BGA packaged FPGA
today. As FPGAs continue to grow larger and more complex,it seems that the design tools used by the design engineers
become increasingly unsophisticated. Which begs the question: How are designers going to place these large components on
to a PCB in an automated and consistent way?
Since the problem spans the two processes of FPGA and PCB design,it is difficult to decide where a solution should be
created. Central to this discussion are the problems of symbol creation and I/O assignment,and given the fact that it concerns
the two processes,how to keep the information consistent between them. This paper discusses the problems and possible
solutions to integrate today’s large FPGAs on a PCB,where subjects like scalability to larger/smaller devices,corporate
library structures and the origin of the I/O constraints will be discussed. This paper also addresses some ways to help
overcome these FPGA integration problems by using the right tools.

As digital data rates reach 5Gb/s,10Gb/s and beyond,digital designers are finding it increasingly difficult to meet their
design constraints using FR4. While there are a host of alternative materials available,cost constraints often prohibit the use
of these materials as their increased performance brings a proportional increase in price. An often overlooked compromise
solution is available which gives substantial improvements to the loss characteristics of high speed layers by using a mixed
stripline construction which pairs FR4 with a high performance material such as those available from Nelco,Rogers,and
W.L. Gore. This paper addresses the question of the potential benefits of mixed dielectric stripline construction by comparing
the crosstalk and insertion loss performance of hybrid (mixed dielectric) stripline constructions to industry standard,
homogeneous PCB stackups. Data is obtained both via direct measurement of test traces and via simulated results. Finished
PCB cost-performance considerations are also presented for the constructions evaluated in this study.

The electrical properties of PCB substrates are one of the primary factors used in designing high-frequency printed circuit
boards. The loss tangent is the electrical property used by material suppliers to characterize the signal integrity of the PCB
substrate. OEMs will perform additional electrical tests to characterize the performance of a PCB substrate before deciding to
approve it for use in a design. This paper will discuss one technique used to characterize signal integrity by an OEM.
Additionally,this test will be compared to values provided by material suppliers to determine the degree of correlation.

The need for dynamic compact models for Integrated Circuits (ICs) is a well-recognized problem in electronics cooling
simulations of electronic systems. Simplified thermal models have been reported in literature to simulate steady-state and
transient thermal behavior of IC devices. Most of the simplification approaches require a pre-determined topology of a
resistance-capacitance (RC) network. Multigrid technique allows for automatically constructing both the topology and
characteristics of the reduced-order or compact models of devices (primarily IC packages) for use in system-level
simulations. In this study,we report an approach where the topology of RC networks is automatically generated. The
topology of the RC network is not predetermined and can be automatically changed to meet the modeling accuracy
requirement. The procedure is robust for packages with various degrees of complexity in both automatic construction of RC
network topology and automatic extraction of nodal RC values. The procedure is also applicable for complex IC sub-systems
or systems like multi-chip modules,stacked die package,system-in-package,and CPU module,and hard drives.
In the study report herein,the method is applied to a 196-pin fine pitch ball grid array (FBGA15x15_196L) package. An RC
network is created for the package and then used in a transient CFD simulation under single phase natural convective cooling
in JEDEC chamber. The simulation results using the RC network model are compared to the corresponding detailed package
simulation.

Microvias are the fastest growing new technology for printed circuits. Once you understand the basics,the advanced topics
bring the real advantage to light. This talk will highlight the procedures and conditions that designers needs to consider
making microvias the most productive and profitable architecture for their designs. These ideas go beyond the IPC standards,
but are essential for any designer using microvias. The talk will cover: Vendor Qualification,Component / Assembly issues,
Planning the Design,Signal Integrity concerns and Channel Routing procedures.

In most of today's high speed digital interconnects,the signal loss associated with the printed circuit board (PCB) is the
dominate factor. Material selection,trace geometry,and choice of copper foil all play a role in establishing the signal loss
associated with the PCB interconnect. Silicon and system designers have techniques for dealing with signal loss and
compensating for lossy interconnects; but,these techniques require accurate modeling and characterization of each source of
interconnect loss. Previous work has shown the impact of dielectric material selection on loss,as well as conductor loss due
to high frequency skin effects associated with copper roughness,copper foil tooth structures,and surface finish selection. For
innerlayer stripline traces,surface preparation processes such as oxide and oxide alternative alter the conductor surface to
improve adhesion. This alteration to the conductor surface geometry affects conductor loss and can influence suppliersupplier
variation. Furthermore oxide processing can affect lot to lot variation of impedance and line loss. This paper
investigates the differences between several oxide and oxide alternative processes on high frequency conductor loss and the
impact of process parameters such as rework.

Traditional reduced black oxide processes for inner layer bonding have been superseded by a newer generation of peroxidesulfuric
texturing processes. These lower cost processes,based on an organically controlled microetch,have proven to be
simpler,faster,and more energy efficient. They have eliminated traditional problems such as: re-oxidation caused by baking
and storage,high resistance shorts and pink ring defects.
However,the relentless trend of miniaturization and the inexorable pressures for cost reduction continue to push the
envelope. Lower etch factors are necessary for controlled impedance and fine line applications,and higher copper loadings
are a prerequisite for increased capacity / reduced cost of ownership. The paper describes the major challenges faced,and the
resulting technical progression which has been achieved,to evolve the next generation of high performance processes capable
of meeting this target.

PTFE material is very hydrophobic and among the most difficult to deposit electroless copper or direct metallization. These
materials have very low friction,which makes a surface non-wettable. Plasma technology has the ability to create wettable
through holes by removing fluorines from the surface,leaving the hole walls activated for metallizing. There are several
process gases used to treat PTFE material. Each gas has a different effect on surface wettability. Chemical etching also
changes the wettability of PTFE material by activating the surface.
Although both plasma technology and chemical etching render a wettable surface,there is a recovery time in which the PTFE
material returns to its original state due to fluorine migration. This paper evaluates the results of a DOE comparing three
plasma processes and chemical etching in relationship to wettability,recovery time and plating adhesion.