Embedded passives,i.e.,resistors and capacitors built right into the printed circuit board substrate,is a rapidly emerging and
pivotal technology for the PCB industry preceded only by the plated thru hole in the 50s and microvias in the 80s.
This paper is a presentation of the design process for embedding discrete resistors and capacitors into circuit board substrates.
Materials are available in a wide range of values and technologies. The paper includes a step-by-step process for designing
resistors and capacitors with a variety of materials and embedded passive technologies.
Performance,miniaturization,and cost are the drivers. The average cell phone has 445 SMT passive components at a 25:1
ratio to ICs. Embedding many of these will improve performance,enable more functionality and reduce cost per function.
Embedded passives are not limited to cell phones. Many other applications will benefit from improved performance. Several
materials are commercially available today and many new materials are in development. The paper also includes a brief
review of these materials.

This paper discusses the work and testing performed to obtain extreme high reliability performance from high layer count,
large panel format multilayer printed wiring boards that are used for backplanes in surface mount technology applications.
High density I/O surface mount connectors require fine lines,spacing and small vias. Couple this with a very large amount of
connectors and with a Printed Circuit Board (PCB) of 330mm (13”) by 990mm (39”),it results in very high layer count
Printed Circuit Board (PCB) that can be thirty seven layers and with resulting thickness of approximately 5.3mm (0.210”)
having aspect ratios up to 11:1. Surface mount assembly on a double-sided board requires two reflows which thermally stress
the product and have caused classic plated through hole failures (i.e. barrel fatigue) during initial assembly operations.
Additionally rework of connectors is a requirement that applies additional stress and can cause more failures. This paper will
show information on routing requirements that employ several layers of buried vias and thin 0.1mm (.004") cores and
multiple ground power planes used for voltage and impedance control. Early failures caused by thermal exposure lead to an
intensive development program to consider all aspects and variables in building a high reliability product. Material with
varying Tg and Z-axis properties were included in the tests along with variables in lamination adhesion,etchback,and
plating. A testing program was set up to include multiple thermal stress solder floats,a special plated through hole coupon for
thermal cycle testing and then Current Induced Thermal Cycling preceded by multiple assembly simulation thermal
exposures. Data accumulated will be reviewed with correlation made to the key items that produce the high reliability printed
wiring board. Supplier and user cooperation was key to making the result a successful product that is now in small volume
production. This knowledge can be useful to others who are considering high layer count large panel formats that required
assembly reflow soldering as an alternative to compliant pin technology.

Driving factors for the use of via in pad technology include the growing trend towards more dense and complex printed
circuit board designs as well as the need to minimize parasitic capacitance and inductance on high speed digital circuits.
These two driving factors are accompanied by the enhanced capability of printed circuit board suppliers to fabricate smaller
via diameters without increased fabrication cost. In this study via in pad technology is referring to the use of standard vias,
not microvia technology or blind via technology. Via diameters considered in this study include a range from 0.008” finished
hole diameter up to a 0.012” finished hole diameter. Reduced via hole size enhances the use of via in pad technology,
especially on smaller devices such as 0402 components. Via in pad technology creates increased printed circuit board (PCB)
routing space on the outer layers,which aids in the routing of complex printed circuit board designs. Via in pad technology
also reduces parasitic capacitance and inductance which are typically found in high speed digital circuits.1 This is
accomplished by eliminating the “stub trace” which is typically created by placing a second pad adjacent to the component
pad just to have a land for the via to be drilled.

This paper will describe the method used to automate drawing note creation at Lockheed Martin. It will discuss the reasons
for the automation and some of the decisions that needed to be made before automation could take place. This paper will
compare common methods of creating drawing notes and document the reasoning for writing the Note Generator. The
Lockheed Martin Note Generator will be demonstrated as part of the presentation.

The outlook for optical PCBs is unclear for mainly three reasons: 1) today's limits for copper boards can be stretched with
design and manufacturing improvements,2) the market demand for next generation,higher bandwidth telecom systems (in
the 40Gbps range) won't be clearly known for years,and 3) the point at which optical backplanes cost less than copper
backplanes depends on many unknowns,including the type of optical technology,the design issues (such as layer count),and
the ever-important manufacturing yields. Focusing on issue number three,a NEMI project seeks the answer to the question,
"Under what conditions does optical cost less?" This paper reviews the analysis so far,including major cost model
manufacturing assumptions,design factors,and choices of optical technologies.

The lack of consistency and compatibility in process carrier designs was cited as an early barrier to automation in the
nascent fiber-optics industry. Under the auspices of the National Electronics Manufacturing Initiative (NEMI),a working
group comprised of companies from both the equipment and OEM sectors banded together to address this important
technical area. As the group began work,the IPC brought an established standards development and deployment process to
the table,which greatly enhanced the group's productivity and accelerated the eventual publication of the standard.
This paper will document the standards creation process as viewed from one of the working group authors,highlighting
both the challenges and solutions derived during the development of IPC-8413-1.

Results from a National Electronics Manufacturing Initiative (NEMI) project,formed to improve aspects of fiber optic fusion
splicing,are reported. The focus of this paper is ultra low loss splicing for telecommunications product assembly,with
typical loss of <0.05 dB per splice for standard SMF-SMF. A detailed review and gap analysis of available industry
standards,relevant to splice loss acceptance criteria and loss test procedures,revealed the standards are generally inadequate
for low loss splicing. Various project participants using different equipment and procedures performed fiber preparation,
splicing,splicer loss estimation,and actual loss measurements. Sets of data spanning three loss ranges,obtained with three
measurement methods were compared using an industry standard gage repeatability and reproducibility (GR&R) analysis. A
subsequent comparison of loss measurement set-ups based on a cut-back method for dissimilar fiber (SMF-EDF) splices
showed significant directionality in some cases,and root cause was identified using a round robin approach. A future activity
of this project will be to draft a new loss measurement standard for dissimilar fiber splices,to address an important gap in the
current standards.

When we think of optoelectronics in the USA,we automatically think of telecom applications. These fueled huge growth at
the turn of the millennium,and even after the bubble burst in 2001-2,telecom represented a significant business and the
future of telecommunications. Meanwhile,a number of consumer,medical,automotive,and other applications have
developed rapidly,ranging from imaging,displays,biological analysis,and video gaming to lighting. Worldwide nontelecom
optoelectronics is now more than 50% of the optoelectronics market. Many issues being tackled by organizations,
such as NEMI,are relevant to this area where low-cost packaging has critical technical demands. This paper reviews these
applications,the packaging and assembly challenges they present,and the standardization opportunities worldwide.

A cyclic board-bending technique has been developed to ensure a reproducible multiaxial stress state at the Chip
Size Package (CSP) solder fillet. Mechanically stressing the package serves as a valuable tool to quickly determine
and provide feedback on design and assembly weaknesses,20-30 times faster than less comprehensive data can be
obtained using temperature cycling.
The bending technique allows controlled strain application rate,peak strain,and dwell time as experienced by a
population of ten components per each of ten board positions. Board surface strain for each of these positions is
characterized using strain gages. The plastic,transition,and elastic regions of the PCB are determined
experimentally according to peak strain and correlated with failure mechanism. Two main failure modes are made
manifest through Weibull techniques: board-level failures (plastic board response region),and solder joint failures
(elastic board response region). Cyclic bending results compare different CSP architectures thus demonstrating the
utility of the test technique.

The miniaturization trend in electronics has proliferated the use of Chip Scale Packages (CSPs) in electronics assembly. CSPs
used in portable devices are subjected to harsh mechanical and thermal conditions and underfill provides a dramatic
improvement in their thermo-mechanical reliability. This paper provides a comparison of thermo-mechanical reliability
performance of CSPs underfilled using different methods such as capillary underfill and corner-fill. The evaluation is based
on drop test,liquid-to-liquid thermal shock (LLTS) and air-to-air thermal cycling (AATC).