As an EMS provider of high complexity backpanel assemblies,traceability of components with performance issues found at
system test,functional test and in the field was limited to the ability to trace the raw board or fab defects and not much more.
As more and more technology was being integrated into these complex backpanel assemblies,customers began in earnest to
require EMS providers to provide traceability of components as well as fabs. Endicott Interconnect Technologies attempted
to track a few critical components,such as ASIC modules and power supplies manually. This quickly became unmanageable
logistically and the manual process of logging data in notebooks was unreliable. It was apparent that an automated system
needed to be developed,that could integrate with automated manufacturing equipment,in particular the pick and place
equipment. Utilizing the central processor and employing the on board software and some available industry software,data
generated during component placement would be used to develop the component traceability database. Modifications to all
portions of hard and soft tools would have to be made to integrate them into our server database so we could offer a reliable,
dependable and economic solution to this problem. This paper will describe the solution that was developed to solve this
challenging problem.

Fabricators,and the copper plating process they choose,can have considerable influence on their customers' solder joint
reliability. In the case of high density assemblies,via-in-pad designs often cause solder joint void formation due to the
trapping of air and/or other contaminants. If large enough,these voids can compromise reliability in the end systems they
inhabit. This paper helps the board fabricator and the contract assembler understand how the copper plating process affects
voiding levels in solder joints,for via-in-pad Printed Circuit Boards (PCBs). We compare three different plating methods for
filling microvias,and then study the impact of these methods on the occurrence frequency and size of these voids. Three
types of plating processes were analyzed: conformal plate (no via-fill),a one-step via-fill,and a two-step via-fill. Voiding
frequency and size were determined from sample cross-sections and X-ray inspection. It is observed that even "low success"
in filling the vias can significantly reduce the void size and occurrence in the solder joints.

In the United States,focus turns toward enabling technology for quick-turn printed circuit board and laminate package
manufacturing. The current corporate mandate is to develop advanced,enabling technology,and to integrate it rapidly.
Reduced via diameter,and higher layer count at lower cost for laminate packages and printed circuit boards continue to be
pursued,as they are key elements for higher density products. Filling vias with increased aspect ratios (depth/hole diameter)
had become a poser,and inefficient squeegee print methods were replaced to a great extent by injection methods. Novel via
fill injection and or vacuum applications,along with peripheral devices for post-fill processing enable the manufacturer to fill
higher aspect ratio vias having diameter to depth ratios greater than 10:1,with reduced cycle time.
Hold the phone! Are all the necessary elements in place? As with any new technology,we discover missing pieces as we go,
and new demands are placed on any given process that must be dealt with in turn. As via protection becomes more defined,
hole-fill tolerances are made more stringent and correspondingly,more difficult to measure. How do we now inspect the
product as efficiently as we process it? Other questions emerge. How are higher Tg laminate materials affecting both board
and process? How well do the laminate and via fill materials compare regarding Z expansion? What are materials suppliers
doing to address the disparity of x and y thermal expansion in ppm vs. z expansion in the percentile range.
Studies regarding various paste materials,their behavior,and integration into advanced production applications from the
printed circuit board,to hybrid microelectronics materials and others,have afforded an opportunity to observe and assess
current capabilities,as well as to gain insight into issues that have cropped up in terms of via protection. This paper will (in
common-sense terms),attempt to look at pertinent issues regarding via fill paste and laminate material properties,general
process enhancements,perhaps some novel approaches to inspection of post-via fill panels and repair methods,with a
smattering of selective via process concepts,and paste rheology contribution to that process as well.

Optomec is developing an aerosol-based technology for high-precision,maskless deposition of a wide variety of
materials. The system functions by atomizing commercial inks and pastes,and then depositing the droplets under
CAD/CAM control. Feature sizes of 25 microns and smaller are achieved and millimeter-scale tool standoff allows
non-contact deposition into vias,trenches,and three-dimensional geometries. The compatible materials include a
variety of commercial metals,resistors,dielectrics,and polymers as well as custom specialty materials. The
materials can be laser sintered or thermally cured and are compatible with ceramic and glass substrate as well as
various low-temperature substrates such as epoxy circuit board and flexible polymer film. This technology is called
Maskless Mesoscale Materials Deposition (M3D).

x

A vertically configured package technology developed by Tessera is proving to be a practical multi-die solution for any
number of single and multiple functional combinations. The enabling technology for this stacking approach allows different
sub-structures individually assembled,tested and joined together electrically and mechanically in a secondary process while
still maintaining a small,single die footprint. This combining of several die sizes with varying functions within a single finepitch,
low profile BGA package outline is achieved using thin flexible polyimide substrate as a base and adapting a unique
combination of folding and package stacking methodology. In addition to the folded and stacked combinations,individual die
can be configured for vertical stacking. In the case of memory for example,the single die can be packaged,tested,and
marketed as unique sub-structures,allowing each die type to be sourced separately from multiple silicon vendors. This
“layered” approach to packaging is designed to improve yield,resolve test concerns and overcome the business issues
hindering the wide-scale adoption of multi-die solutions. The paper examines several alternative 3D multiple-die package
solutions that solve many of the multiple die source problems while delivering the expected performance and cost benefits.

The adoption of three-dimensional System-in-Package (3D-SiP) is progressing rapidly,driven primarily my mobile electronic
applications such as mobile phones,PDAs,digital still cameras,and digital video recorders. The underlying,enabling Chip
Size Packaging (CSP) technologies can be broadly classified into two types: chip-stacking and package-stacking. In Japan,
both of these stacking methods have reached maturation in terms of the fundamental manufacturing processes required for
cost-effective mass production. Meanwhile,chaos reigns on issues such as supply logistics and IP ownership.
This paper and presentation will focus on the examples of increasingly high-function mobile electronics applications enabled
by 3D-SiP being developed and released into Japanese and overseas markets,as well as the accompanying demand for
continued 3D-SiP technology development based upon industry-wide standards in order to encourage and support rapid
adoption in the marketplace.

Buried Capacitance1 (BC) laminates products have been in use in many high-speed applications for more than ten
years. BC products are a significant contributor to complex multi-layer printed circuit board construction and also a
major element in power distribution circuit design. The principle features of thin laminate BC technology are high
frequency by-pass decoupling capacitance,very low loop inductance and EMI shielding. The newly developed,less
than 2 mil thick,BC laminates shall allowed circuit designers to make significant advances in electronic systems
speed,performance and reduce overall product cost. Manufacturability and reliability of the advanced.

Electronic devices with high performance are becoming smaller and lighter. The passive components required to
enable high performance consume premium space on the surface of the printed circuit board. Integrating the resistor
function into the laminate substrate frees up the PCB surface area consumed by the discrete component,enabling
increased device functionality by the placement of more active components. When the typical 5 to 20 % tolerance of
embedded resistors can be allowed,the resistors satisfy the device requirements. The resistive materials and the PCB
fabrication processes used to fabricate the resistors are currently not able to achieve precision of 1 % or less.
Laser trim technology achieves < 1 % tolerance on thin film embedded resistor panels. The resistive material has an
effect on the efficacy the laser trim. Thin resistive films are laser trimmed to a high degree of precision. Thin film
alloys of nickel and chromium,due to the good thermal stability of the alloy,are trimmed to high accuracy at high
speed.
The printed circuit board manufacturing processes may induce a shift in the resistor value as well as widen the
tolerance. Environmental stress during use may also widen the tolerance. The resistance value and tolerance of laser
trimmed thin film nickel-chromium alloy selective etched embedded resistors was measured after PCB process steps,
and after environmental stress tests. Thin film embedded resistor tolerance is quantified after multilayer lamination,
humidity exposure,convection reflow,solder heat,and thermal cycles.

Lower cost is frequently listed as the main driver for moving to embedded passives. Unfortunately,understanding
the true cost difference between a design using embedded passives and the same design using discrete passives is
complicated. These discrepancies span design,board fabrication,materials,and assembly. While a variety of factors
influence the cost difference,one of the major cost drivers involves layer count and board size. Designs with
embedded passives often fit on smaller boards when compared to designs with discrete passives. However,although
the cost per square inch of the embedded passives board is higher than the discrete alternative,the total cost of the
smaller board may be less.
This paper analyzes drivers that influence the design size and layer count. A methodology is presented for
accurately predicting the final size and cost of designs with embedded passives as well as with discrete passives.
This methodology includes design routing analysis,escape routing analysis for BGA’s,board surface area analysis,
and panelization details. The cost impact of these size differences is also analyzed using activity based cost models
for board fabrication and assembly.