X

The growing use of high density interconnect (HDI) substrates in the microelectronics packaging industry has brought along a broad range of yield issues. Many of these issues are associated with surface defects in the interconnect terminals and solder mask areas of the finished substrates. Detecting such defects requires a different set of capabilities than that of traditional Automated Optical Inspection (AOI) tools used for in-process inspection. These differences result in particular from the surface integrity specifications of the interconnect terminals,and the subjectivity of defect severity. This paper presents examples of defects and discusses inspection capabilities required to detect and classify them correctly. It examines the factors affecting detection capability and false alarms,and proposes a simplified method for system performance evaluation and setup optimization.

X

It is becoming impossible to realize the latest mobile phones and other mobile equipment without Chip Size Packages (CSP) and other high-density semiconductor package technology. At present,the most advanced mobile phones in the world are being made in Japan with a compact size and lightweight,but these rely for the most part on chip stacked CSP technology. This paper describes how mobile phone packaging technology has changed in Japan,from 1996 to 2001-2002,and how packaging is being done in the most recent mobile phones. In preparation for the coming era of 3-D System In Package (3-D SIP),this paper also describes the kind of technologies that are possible today,and how they will develop in the future.

Liquid crystalline polymer (LCP) substrates offer a number of advantages for high-density packaging. These properties include high temperature capability (>250oC),low coefficient of thermal expansion (8ppm/ oC),low moisture permeability (comparable to glass),smooth surface,and good high frequency characteristics. LCP substrates can be fabricated as flexible films (2mil thick) or as rigid multilayer substrates. In this paper the processing of rigid and flexible LCP substrates are first discussed including etching,drilling,and plating. Next,the compatibility of LCP substrates with wire bond and flip chip assembly processes and materials are examined. Specific tests include solderability with eutectic Sn/Pb and lead-free alloys,surface insulation resistance with no clean fluxes,gold wire bondability and flow/wetting of underfills for flip chip assembly. The high temperature capability of the LCP is compatible with the higher reflow temperatures associated with lead–free solders and also allows thermosonic gold wire bonding at a substrate temperature of 200oC. Solder dips in lead free alloys at 274oC have shown no delamination of the copper foil. Gold ball shear test results demonstrate average shear strength of 62.4 grams with a standard deviation of 4.3 grams when bonded at 200oC. Optical fibers can be molded into the LCP substrate for optical connections and optical fibers can also be molded into the package sidewall for optical connections. Finally,hermetic packages have been fabricated and shown to pass fine and gross leak tests.

In today's world of electronics the keywords are smaller,faster and cheaper. With more and more circuitry going onto existing circuit boards,the designers are searching for ways to contain this additional functionality in the same,or smaller,space envelope. To accomplish this,the semiconductor die used in the circuit design must shed the traditional packaging enclosures. One solution is to create sub-systems as building blocks that can be assembled on a motherboard to provide a complete functional solution. Twenty years ago we called these sub-systems “Hybrids”. When the die became larger than the discretes,we called them MCM’s. While searching for a descriptor for MCM,it was suggested that “if you can’t afford it,it must be an MCM)”. Now “system in a package” is in vogue. Many of the issues faced twenty years ago are still issues today. However,more have been added. These of course include die quality and reliability including tradeoffs,assembly quality and reworkability and in some cases substrate quality and reliability. This paper primarily looks at die quality and reliability issues and discusses solutions or work-arounds.

X

With the advent of more flexible versions of pulse-reverse plating technologies,and with the ability to program more of the waveform parameters,comes an increased number of options facing the user. An impediment to the rapid determination of the optimum programming parameters in any via-plating system is the very large numbers of test runs this can generate,and the very time-consuming cross-section evaluations needed to assure that valid decisions are made. Similarly,this “cross-section proliferation” problem faces platers contemplating any other plating process options (eductor placement,vibration equipment,agitation changes,chemical changes,etc.) Building on an idea put forward by Yair Assaf at AESF SurFin 2002,this paper reports on experimentation using a test unit to allow programs to be pre-screened without cross-section verification,in comparison with conventional cross-section evaluation. The test unit is designed to be used by itself,or to accompany parts through the plating cycle,and consists of a tapered-gap,with a removable copper tape as plating substrate. All this is to permit better/faster/less burdensome realization of the benefits of complex wave form pulse reverse systems in via formation. It is our hope that others in the industry will expand on this idea to the point that it can be developed into a useful,reliable tool.

The multiple die chip-scale package technology (identified as the ?Z™) is a truly innovative,folded-flex stacked packaging technology. The concept has already been proven in a collaborative development effort between Tessera and two customer companies. A two-die package,developed for a leading medical electronics company,has been qualified and is currently in limited production. The three and five-die package developed for a leading IC manufacturer was targeted for the new generations of wireless electronics. The folded-flex stacked die package meets the lower height target defined by many OEM customers (a significantly lower height than many of the two die stacked wire-bond solutions available today). Implementations are now being requested by the industry that requires the inclusion of different types of silicon technologies (including memory and logic) into a single package footprint resulting in a solution that is in essence a system-in-package. However,due to differing wafer-level yield rates,multiple silicon sources and testing methodology,the packaging yield and logistics issues can be very difficult to resolve (at both the technical and the business levels). In order to meet this growing demand for further integration,an innovative solution is required that brings all of the benefits of more conventional chipscale packaging,including size,performance and reliability,while addressing testing,yield and logistics issues. This paper examines several alternative multiple-die package solutions that solve many of the problems identified above while delivering the expected benefits. The package technology adapts one and two metal layer,flexible substrate materials,allowing two,three,four or more die in a single die BGA outline. Most of the multi-die packages developed for memory applications use classic CSP processes for die interconnect,though,other conventional interface techniques can be employed as well. The enabling technology for this “fold-over” approach allows the different sub-structures to be electrically connected while still maintaining a small footprint. The individual die included in the stack can be packaged,tested,and marketed as individual sub-structures,allowing each die to be sourced separately by each silicon vendor. This “layered” approach to packaging is designed to improve yield,resolve test concerns and overcome the business issues hindering the wide-scale adoption of multi-die solutions.

With the advent of more flexible versions of pulse-reverse plating technologies,and with the ability to program more of the waveform parameters,comes an increased number of options facing the user. An impediment to the rapid determination of the optimum programming parameters in any via-plating system is the very large numbers of test runs this can generate,and the very time-consuming cross-section evaluations needed to assure that valid decisions are made. Similarly,this “cross-section proliferation” problem faces platers contemplating any other plating process options (eductor placement,vibration equipment,agitation changes,chemical changes,etc.) Building on an idea put forward by Yair Assaf at AESF SurFin 2002,this paper reports on experimentation using a test unit to allow programs to be pre-screened without cross-section verification,in comparison with conventional cross-section evaluation. The test unit is designed to be used by itself,or to accompany parts through the plating cycle,and consists of a tapered-gap,with a removable copper tape as plating substrate. All this is to permit better/faster/less burdensome realization of the benefits of complex wave form pulse reverse systems in via formation. It is our hope that others in the industry will expand on this idea to the point that it can be developed into a useful,reliable tool.