Optical connectors are used to connect optical devices to other optical devices or systems. The presence of these optical connectors makes it possible to switch conveniently from one device or system to another. However,each connection introduces a certain amount of insertion and return loss that can impact performance. Such losses are particularly critical at high-speed transmission. Many applications can only tolerate less than 0.1dB loss for a connection. This paper will examine the challenges that manufacturers and users face as they manufacture and/or use fiber optic connectors. This paper will also discuss the factors that influence the optical performance (insertion loss,return loss,etc.) of fiber optic connectors. The losses due to process problem,contamination,and the type of adapters used for connection will be considered.

Two new electrolytically plated lead-free surface finishes,satin bright tin on nickel and palladium-cobalt on nickel followed by gold flash coating,are evaluated for their wettability,bond strength,and voiding performance,and are compared with electrolytic nickel gold and OSP. Results indicate that Ni-Sn,although being sensitive to aging,and
reflow atmosphere,solder alloy type,and variation in flux chemistry,it is the highest in wettability,one of the highest in lap shear strength,and the lowest in voiding. It performs better under long profile. The high sensitivity may be attributed to the relatively high reactivity of tin. Under most instances,the soldering performance is comparable with or better than the references OSP and Ni-Au. Ni-PdCo-Au is poor in wettability,fairly low in lap shear strength,and high in voiding. However,it is fairly stable,and its soldering performance is not sensitive to profile length,reflow atmosphere,aging treatment,and flux chemistry. It does seem to be sensitive to Bi-containing alloy in terms of voiding and lap shear strength. OSP is the poorest in wettability,but one of the best in lap shear strength. It performs best under long profile. It is not sensitive to reflow atmosphere,slightly sensitive to alloy type,but is very sensitive to aging and flux chemistry. Ni-Au is good in wettability and voiding,medium in lap shear strength. It is not sensitive to aging,flux chemistry,reflow atmosphere,slightly sensitive to alloy type and profile length.

Lead-free soldering technology is still in its infancy with technical and cost issues posing major challenges for the industry. It is expected that soldering in a nitrogen atmosphere might overcome some of the technical barriers and provide soldered products comparable to those using conventional lead-containing materials processed in air. But quantitative data regarding the soldering behaviour of lead-free solders under various atmospheres are sparse. Hence this work was undertaken to build on the previous studies of the solderability of SnAgCu alloys under a range of residual oxygen levels between 10 ppm and 21%. The current work extends the study to other lead-free solders,SnCu,SnZn and SnAgBi,in atmospheres containing as little as 10 ppm oxygen
at superheats from 20 to 60 degrees. The results clearly demonstrate the benefit of inerting for these solders. Apart from widening the process window,it can reduce oxidation and improve solderability of lead-free systems to a level close to that of SnPb. In many cases the addition of an inert atmosphere during lead-free soldering can
allow a ~30ºC reduction in soldering temperature AND give the same solderability as using SnPb in air. Inerting is especially beneficial at low soldering temperatures or for challenging assemblies such as multi-layer boards. Whilst in the case of soldering with SnZn alloy inerting to < 100 ppm was essential,for SnCn and SnAgBi solders inerting only to <5,000 ppm oxygen offered significant benefits in wetting. For many of the challenging conditions and poor solderability associated with lead-free solders,nitrogen offers an attractive alternative to stronger fluxes and higher processing temperatures.

Conductive anodic filament (CAF) formation is a failure mode associated with electronic circuits which operate at high voltage gradients and which are stored under high humidity conditions. Certain soldering fluxes and hot air solder leveling (HASL) fluids enhance this failure mechanism. Research was conducted to examine the effect of three different conformal coatings in reducing the incidence of CAF associated with a variety of water-soluble flux formulations. The fluxes chosen contained a water-soluble vehicle as 20 wt% in isopropanol. Some formulations contained 2wt% HCl,HBr,and/or monoethanolamine. The conformal coatings tested were acrylic (Humiseal 1B73),silicone (Humiseal 1C55) and parylene C. IPC B-24 test boards were coated with the flux,reflowed to create the thermal cycle,and then cleaned. Some boards were conformally coated and others were not. All test boards were exposed to SIR testing at 85oC,85% RH and 100V bias for 28 days. This paper will report on the electrical results,as well as the number of CAF observed with and without conformal coating. It will also discuss visual observations of dendrites on boards with/without conformal coating.

The formation of underfill voids is an area of concern in the low cost,high throughput,or “no-flow” flip chip assembly process. This assembly process involves placement of a flip chip device directly onto the substrate pad site covered with pre-dispensed no-flow underfill. The forced motion of chip placement causes a convex flow front to
pass over pad and solder mask-opening features promoting void capture. This paper determines the effects of substrate design on the phenomena of underfill voiding using the no-flow process. A full-factorial design experiment analyzes several empirically determined factors that can affect void capture in no-flow processing. The substrate design parameters included pad height,solder mask opening height,pad/solder mask opening separation,and pad pitch. The process parameters include chip placement velocity and underfill viscosity. The process robustness is measured in terms of the number of voids created during chip placement,and is further analyzed for the location and any visible modes of void formation. The goal of the work is to determine improved substrate designs to minimize voiding in flip chip processing using no flow underfills.

Residue left behind from no-clean assembly is a visually obvious artifact of the manufacturing process that can
cause concern to those with RF circuit assemblies. This paper describes a test vehicle and test procedure,
independent of product design and function,that allows for a quick and relatively simple examination of the
electrical effects of residue frequencies up to 7.15 GHz and the determination of the capacitive parasitic associated
with it. Two test vehicles were compared,each comprising a bi-directional coupler. Flux medium was extracted from no clean paste using centrifuge,applied to the center of the bi-directional coupler and reflowed. It was found
empirically that for null frequencies in the range of 7 GHz,one of these bi-directional couplers was more sensitive
than the other to parasitic induced by residue. This finding was in accordance with linear circuit simulations performed on the electrical model equivalents of the couplers that were also developed during this project. The flux residues from extracted flux medium of five pastes were examined. The flux residue that induced the most amount of parasitic could be modeled as a capacitor of 25 fF +/- 15 fF. Any change in parasitic as a result of aging of the extracted flux medium to an equivalent of one-year floor life was determined to be negligible.

Group technology (GT) concepts can be applied in printed circuit board (PCB) assembly when determining a setup strategy for a single machine. In the group setup strategy,PCBs,which have similar component setups,are grouped together so that all the components required by a group can be loaded to the machine at one time. Thus,any board in the group can be produced without changing the component setup,which is only required when switching from one group to another. The benefits of the group setup strategy are fully realized in high-mix,
low-volume production environments.

Surface Insulation Resistance (SIR) Testing,has been used traditionally to characterise process materials,
particularly solder fluxes. Existing Surface Insulation resistance (SIR) test methods are outdated and unrepresentative of modern circuit technology1. A recent European research programme found that,using the existing international standards,the SIR value of a typical no-clean flux,could be over estimated by a factor of 10 when compared to a test using parameters representative of today’s technology. This new test method has,in addition,proved easier,cheaper and faster to perform; the equipment required is now readily available and a new IEC (Draft IEC 6-1189) process characterization specification is soon to be available. Here,in light of these European findings,an updated SIR test method is used to characterise a lead-free and VOC free electronic production process,including board surface finish,solder resist,paste,flux,wire and conformal coating – and using dummy components to more accurately determine their influence on the test protocol. The SIR test method is very simple in concept,and involves measuring the resistance across two inter-digitated comb patterns,whilst the sample is exposed to artificial ageing conditions of heat and high humidity. If a low SIR is seen on the test sample it is likely that the residues,if left on a PCA,will have a negative effect on the reliability of the circuit in the field. Whilst the principle is simple,the successful implementation of a test is not trivial. Historically the test was implemented simply with a single current metering instrument capable of measuring fractions of a micro-amp.
Modern test equipment allows frequent monitoring of a large number of samples at sensitivities of nano-amps or
better. This increased sensitivity has resulted in the European group’s ability to study the SIR values over a range of
track and pitch widths,using test patterns that are located underneath components. It was found that the coupons and voltage gradients defined by present standards,again lead to higher SIR values and fewer failure incidents,as compared to the results obtained for a coupon comprising a track width,pitch and voltage gradient combination representative of today’s technology. The Swedish research institute IVF and Delphi-Delco have shown that synergistic interactions with other process chemistries used in the manufacture of PCAs can affect the resulting SIR and hence the resultant reliability of the product. IPC J-STD-001B Appendix D does tackle the subject of process validation using SIR,but references the same SIR test methods for isolated flux qualification,that need updating.
Examples of the test results will be presented.

Vapor phase soldering is in discussion of the recent past. Some of the topics of our own work are presented in this paper,like the combination of vapor phase reflow soldering with wave soldering process. This combination makes it possible to solder printed circuit boards with SMT and THT components in one step. Additional the inert vapor atmosphere takes on the protection of liquid solder from oxidation. Another current development is an inline condensation soldering system. In a laboratory construction a lot of experiences were collected. The studies shows the importance of understanding the connection of partial pressure and temperature as well the mechanism of flow and heat transfer. First results were tested by soldering of true electronic assemblies and with lead free solders.

Manufacturers of consumer electronic products are continuously striving to confer greater functionality to smaller,lighter,and less expensive packages,and flip chip is an important enabling technology for these product trends. Underfill between the die and an organic substrate is necessary to compensate for the coefficient of thermal expansion mismatch. The underfill dispense step is not a typical process for an SMT factory,and demands additional capital equipment,floor space,cycle time and headcount. These additional investments,plus the inability to rework underfilled parts has limited wide scale implementation of flip chip technology. The National Institute of Standards and Technology Advanced Technology Program "Wafer Scale Applied Reworkable Fluxing Underfill for Direct Chip Attach" (NIST-ATP WARFU) was established to investigate the development of a flip chip underfill process that would be transparent to the SMT line. The program is supporting the successful development of fluxing,reworkable underfill materials and processes for direct application of the materials to die at the wafer level. While the application of underfill materials directly to the Wafer seems straight forward,many of the material requirements are incompatible with each other. For instance,the necessity of dicing the wafer using water is not compatible with the use of uncured epoxy materials. In addition,the incorporation of fluxing materials into the bulk underfill is known to degrade long-term stability at room temperature. This needs to be addressed,as the stated goal of the program is to provide at least 6 months of on part life prior to use. The methods and materials used to address these concerns are described in the paper.