Despite the strong increase in demand for high-density circuit boards,very few manufacturers are offering microvia architectures in high volume. Current microvia technologies require significant changes in multilayer manufacturing methods as well as new materials and new chemistries. The electroless plating chemistries most commonly used are costly and difficult to maintain,and the dimpled morphology of the resulting microvias is problematic. Transient liquid-phase-sintered (TLPS) paste-filled microvias are solid,planarize during processing and will alloy to all conventional circuit finishes during standard lamination cycles. Although TLPS microvias,like most other microvia technologies,do require laser-drilling capabilities,no other significant change to standard multilayer PCB fabrication is needed. Use of advanced laminates/prepregs or resin-coated-foil is optional. The TLPS microvia technology was proven in cutting-edge multilayerflex IC packages. It has since been adapted for use in multilayer PCB applications and can cost-effectively enable any multilayer board shop to offer HDI products.

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The evolution of interconnection systems for Printed Circuit Boards has been extremely interesting. The first connections were those generated in a copper foil on the surface of a single sided insulating substrate. The first method providing connectivity between circuit patterns on both sides of an insulating layer was the use of rivets. When crimped correctly,these units allowed the development of multi-layered circuit patterns. The introduction of electroless copper systems allowed this interconnection to be made chemically,and resulted in much more reliable electrical interconnects. The number of layers could be increased until the point was reached where reliability became a critical quality issue. It was not unusual to see finished product with 20,30,40,or more layers. The problem inherent in the use of through hole technology is that a large portion of the ‘real estate’ of the circuit planes was used for connectivity requirements,thus reducing the density potential for the product. Within the past decade,a new concept of interconnectivity has been introduced. The technology is called “Microvia Formation”. By IPC definition in document IPC/JPCA-2315,microvias are those interconnection vias less than 150??(0.006”) in diameter. This paper relates to problems inherent in the formation of microvias

The need for the high density provided by Build-up PWB installed in the mobile communication products requires the general trend towards a gradually smaller hole diameter. For the micro via drilling,it has been categorized by the process as shown in Figure 1 so far,and due to the technology development,further smaller holes are processed. This paper presents these up-dated technologies.

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For faster,smaller,and high performance integrated circuits the new concept of buried bump interconnect substrates is required. We have developed B2itTM (buried bump interconnection technology) for this technical trend. The fine phase of this interconnection technology carries out the build up of the fine wiring layer of Cu/BCB on all buried bump interconnection technology wiring boards for high-density and high performance. This paper reports the results that focus on the fine wiring layer formation process technology and the high frequency transmission characteristic of the fine phase as a result of a fine wiring formation process' adopting BCB as dielectric material and the sputter semi additives method. The limitation of the minimum pitch was 10µm (L/S=6 /4). Filled via process was possible for a 20µm via diameter. Electromagnetic simulation was performed to research the dependence of the signal transmission characteristic on the pitch of fine lines. When the pitch becomes small at 10µm or less,it turns out that transmission loss becomes large due to the influence of contiguity wiring. As high frequency correspondence aptitude,a result of the S parameter with micro strip line structure,it was –3dB in 16GHz. From this,as a design rule for fine wiring layers,a pitch of 15µm (L/S=7.5/ 7.5),and 20µm for filled via diameters are optimal designs. The fine wiring technology was developed and designed for a high density and high-speed substrate,utilizing this buried bump interconnection technology.

The last 10 years have seen the rise of lasers used in the interconnect industry to a point where their use is almost becoming ‘main stream’. As line width and spacing requirements become smaller,lasers will play an ever increasing role in the manufacture of interconnect devices. There is currently a gap between lithography processes on the small side and ‘traditional’ etch/mechanical methods on the large side which lasers fill quite nicely. Within these bounds,lasers are poised to be the dominant manufacturing technology for many processes.

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As CPUs increase in performance,the number of passive components on the surface of the boards are increasing dramatically. To reduce the number of components,as well as improve the electrical performance (i.e. reduce inductance),designers are increasingly embedding capacitive layers in the PCB. The majority of the products in use today utilize reinforced epoxy laminates. These products are relatively easy to handle,but the thickness and Dk limit the effectiveness of the layer to perform as a capacitor. Other materials are being developed that are thinner (and thus increase capacitance),but either have problems with dielectric breakdown strength,handling or only marginal improvement over the existing material. This paper will describe new non-reinforced substrates for use as embedded capacitance layers that address these issues. The material selection process,substrate processing and electrical performance will be reviewed.

Increasing component density and the requirements of higher performance electronic devices are driving the development of embedded passive devices in the printed circuit board (PCB). The benefits of embedded passives are that they free surface space for active devices,improve performance and signal quality by lowering inductance and reduce overall system cost. Embedded passives also yield a more reliable printed circuit board by reducing the number of solder joints. A resistor is an important passive device in an electric circuit. To enable high performance devices,an embedded resistor must achieve a tolerance that allows the PCB design to meet electrical timing and circuit signal quality requirements. The tolerance of embedded resistors is not only determined by the uniformity of the resistor material but also by the PCB manufacturing process which forms them,especially when the sizes of the embedded resistors are small. The stability of the material when subjected to typical printed circuit board processes will also affect the final tolerance of embedded resistors. Gould has developed a thin-film NiCr alloy resistive layer sputtered onto rolls of copper foil for embedded resistor applications. Nickel-chromium alloys possess high electrical resistivity,good electric performance and high thermal stability. The thin film is very uniform,and is capable of forming resistors with tolerances that meet the requirements of high performance PCBs. Merix Corporation is involved in the NIST Advanced Embedded Passives Technology (AEPT) consortium,and has built test vehicles for the consortium and customer prototypes using Gould's thin-film alloy resistor foil. This paper reviews data from the material manufacturer on the effects of specific processing factors on the overall tolerance of the resistor,and describes the board fabricator's process development for reducing resistor variation and improving yields.