Development of a Robust 03015 Process
Modern consumer electronics are driving the adoption of smaller featured SMT devices such as 0.4 mm or smaller pitch CSP,and 01005’’ / 0402 metric discrete devices. Already roadmaps have been suggested to explore the use of smaller pitch CSP and 03015discrete devices,which are only around 64% the size of 01005 devices. On their own these challenges can be met by using stencils with thinner materials allowing sufficient area ratios to maintain the established safe area ratio guideline of 0.6% or higher. However when having to process fine feature devices along with larger devices such as connectors and RF shields,which usually require higher paste volumes to overcome co-planarity issues,the area ratio factors encountered in real production are dropping significantly below the conventional rule of thumb of area ratios having to be above 0.6 and in some instances below 0.5 area ratios. With this forced compromise in area ratio guidelines comes a compromise in process window robustness and subsequent print and even placement process quality. In order to try and redress this issue,different technologies have emerged in stencil materials and treatments combined with the use of finer grades of solder paste,but the question remains: “In isolation or by adopting a combination of these technologies is it enough,to establish a robust 03015 process?” This paper will review major steps considered and taken for the development of a robust 03015 process which was successfully Demonstrated at the company in-house show during Productronica in November 2013,and it will focus on the activities for the solder paste print process