•Nano-electronics potential
•Barriers to entry – and opportunities
•Examples
–Nano-solder
–Capacitor materials
–Graphene
•Opportunities for rapid commercialization?

The use of copper foils laminated to polyimide (PI) as flexible printed circuit board precursor is a standard practice in the PCB industry. We have previously described [1] an approach to very thin copper laminates of coating uniform layers of nano copper inks and converting them into conductive foils via photonic sintering with a multibulb conveyor system,which is consistent with roll-to-roll manufacturing. The copper thickness of these foils can be augmented by electroplating. Very thin copper layers enable etching fine lines in the flexible circuit. These films must adhere tenaciously to the polyimide substrate. In this paper,we investigate the factors which improve and inhibit adhesion. It was found that the ink composition,photonic sintering conditions,substrate pretreatment,and the inclusion of layers (metal and organic) intermediate between the copper and the polyimide are important. Ink factors include the intensity of photonic sintering. Better sintering leads to better cohesive strength of the nano copper layer. The ink solvent and the dispersant used to suspend the nano particles are significant both for adhesion and the colloidal stability of the dispersion. Pretreatment of the substrate by plasma roughening did not improve adhesion. We describe the effects of chromium and nickel interlayers which are typically used in standard foil laminates. Finally,we describe the types of peel testing used to assess adhesion.

Flux consumption for wave soldering tends to decrease,mainly due to its gradual replacement by reflow soldering methods (i.e. pin-in-paste) in many electronics applications. However,in several cases,wave soldering still remains a must,with an increasing share of “selective” soldering processes,either using wave frames with dedicated apertures or solder fountains. Such processes are more challenging for the fluxes in terms of reliability under operation,since some chemistries remaining on the printed circuit boards after soldering may promote corrosion. Thus,flux manufacturers had to adapt their formulations to minimize such issues while keeping an efficient activation level,with several types of alloys (tin-lead,tin-silver-copper and low/no-silver) and associated with the numerous types of finishes encountered. The paper will cover the types of flux used in the electronic industry according to their chemistry and activation level (rosin-based,halides,alcohol-based or water-based flux...),and their characteristics with reference to standards. The limits of current standards will be discussed in regards to the last generation solder fluxes. Then,the development of two low-residue new generation fluxes,an alcohol-based flux and a true VOC-free flux,will be described,according to requirements: the lab tests results (surface tension,spread tests,wettability tests...) will be presented and discussed. Reliability will be especially investigated through surface insulation resistance,electro-chemical migration test,ionic contamination as well as Bono tests to determine the candidates able to provide high processability combined with chemical inertness of residues. Finally,the performance of flux will be assessed through customer tests,involving several types of boards,finishes and different solder alloys and wave equipment.

No-clean soldering processes continue to dominate the electronics manufacturing world,especially amongst consumer-type electronics. For many years,type 3 was pretty much the “standard” solder paste particle size with a distribution of 25 – 45 microns (-325/+500 mesh). However,the ongoing trend toward ever-increasing miniaturization is putting pressure on solder paste manufacturers to produce solder pastes that can reliably print through smaller and smaller stencil apertures. While great advances have been made in solder paste flux technology to accommodate very small apertures,those advances alone cannot meet all the challenges of miniaturization. There is a point at which reducing the solder particle size becomes necessary in order to create solder pastes which can provide adequate transfer efficiency for small stencil apertures. As a result,many modern solder pastes are available on the market with particle sizes smaller than type 3 such as type 4 (20 – 38 microns),type 5 (15 – 25 microns),type 6 (5 – 15 microns),as well as non-IPC particle size distributions like type 4.5 (20 – 32 microns). Reducing the solder particle size for a given volume or mass of solder powder increases the total surface area. Therefore,reducing the particle size increases the surface area that the flux component of the solder paste needs to clean to cause good coalescence and wetting of the solder. The ingredients in the flux responsible for cleaning the surfaces are generically called activators. Because activators are corrosive in nature,they are one of the flux ingredients that can have a substantial impact on the electrical reliability of the flux residue. With decreasing solder particle size,resulting in increasing surface area,the flux has to work harder to clean these surfaces,consuming more of the activators while increasing the amount of activator/metal oxide interaction by-products in the flux residue. Therefore,everything else being equal,changing (reducing) the particle size is likely changing the contents of the flux residue. With this in mind,one must ask: Does reducing the particle size of a no-clean solder paste have a measurable impact on the electrical reliability of the flux residue? If so,is it substantial enough to be a cause for concern? This paper uses IPC J-STD-004B SIR (Surface Insulation Resistance) testing to examine these questions. Two commercially available Pb-free no-clean solder pastes with varying particle sizes,one halogen- containing and the other halogen-free,were tested to see if and how different flux chemistries respond to reduced particle size. All of the solder pastes in this study were submitted to the same common air Pb-free reflow profile.

When designing PCBs,solder paste selection is critical. Once a specific paste type and supplier are identified,the manufacturing process is developed and refined. Critical to the quality of the solder joint is an effective thermal profile. All solder paste suppliers recommend an appropriate thermal profile for specific paste in accordance with J-STD-004/005 (IPC TM-650). At a minimum,solder paste suppliers confirm that the recommended thermal profile produced have passing results for corrosion,SIR and electrochemical migration tests. However,these tests are performed on bare boards. As PCB surface density and component mass increases,is the recommended thermal profile sufficient to produce quality solder bonds and fully volatilize flux residues? Flux residues remaining on a PCB surface and/or component may be benign. However,if the residues are ionic in nature,they can lead to failure mechanisms including leakage current,electrochemical migration and dendritic growth. For high reliable applications that include No Clean or RMA solder paste,it is likely the PCBs are cleaned. If water soluble (OA) solder paste is selected,the PCB is certainly cleaned. An optimized cleaning process cannot address poor solder bonding,but it can remove ionic flux residues minimizing possible failure mechanisms. This study was conducted to assess the effect of thermal profile variations on flux residue formation. It was limited to No Clean solder pastes as this paste may or may not be cleaned. Six (6) different pastes were considered. The IPC-B-52 test vehicle was used for this study. For each reflow profile variation,two identical test vehicles were processed; one was cleaned and one was not. Each was subjected to SIR analysis. Test vehicles that were cleaned were processed using a spray-in-air inline cleaner with an aqueous based cleaning agent.

The electronic industry is currently very interested in low temperature soldering processes,such as using Sn/Bi alloy,to improve process yield,eliminate the head-in-pillow effect,and enhance rework yield. However,Sn/Bi alloy is not strong enough to replace lead-free (SAC) and eutectic Sn/Pb alloys in most applications. In order to improve the strength of Sn/Bi solder joints,enhance mechanical performance,and improve reliability properties such as thermal cycling performance of soldered electronic devices,the company has developed a series of low temperature solderable adhesives using solder joint encapsulant,which can be used for Sn/Bi soldering applications. These low temperature solderable adhesives can be dipped,dispensed,or printed. Can these low temperature solderable adhesives replace SAC application? Pull test and drop test have been conducted for comparison. The pull strength of low temperature solderable adhesive is very comparable to that of SAC alloy,but the drop test of solderable adhesives is much better than SAC alloy. The reliability of low temperature solderable adhesive including the thermal cycling performance will be discussed in detail.

The dissipation of heat from a power die,such as those used to drive the increasingly popular LED arrays,has traditionally been achieved by use of a thermal interface material (TIM) and a metallic heat sink. The performance of this system is usually limited by the capability of the TIM portion of the layers. In circumstances where the unit may be open to the environment,an additional housing is required which can further degrade the thermal performance of the system. By replacing the TIM,heat sink and protective housing with a single thermally conductive,protective thermoplastic overmold material,system performance can be maintained and the assembly process streamlined. In this paper,the processing and performance of such materials will be discussed. The isotropic nature of these materials allows heat dissipation not only in the vertical direction as with a traditional system,but also laterally,thus reducing hot spots and enhancing overall performance. Thermal models show that even a modest thermal conductivity (0.5 W(mK)-1) can reduce hot spots by over 30ºC compared to a regular low pressure molding (LPM) material. These materials retain the low melt viscosities typical of LPM materials and can easily be molded into a wide variety of shapes,allowing flexibility in the final form of the product.

While a significant level of voiding can be tolerated in solder joints where electrical conductivity is the main requirement,voiding at any level severely compromises thermal conductivity. For example,in Light Emitting Diode (LED) lighting modules effective conduction of heat through the 1st level die attach to the substrate and then through the 2nd level attach to the heat sink is critical to performance so that voiding in the solder joints at both levels must be minimized. Voids in solder joints are the result of bubbles of gas that do not escape before the solder has solidified. While there is the possibility that air can be entrapped in the bond area during the reflow of solder paste the gases in the bubbles are generally considered to come mainly from the flux medium,by volatilization of solvents,as by-products of activator reactions with metal oxides,and from decomposition of resins and other constituents. Whether these gases escape from the solder joint or remain as voids depends on many factors including joint area and geometry. Since areas of non-wetted substrate provide points of attachment for bubbles the solderability of the substrates and the activity of the flux are other factors that affect the incidence of voiding in the solder joint. Volatiles released during the time when the solder powder particles are melting and coalescing are the main source of bubbles so that the shape of the reflow profile can have a major effect on the incidence of voiding. In this paper,the authors will review the factors that influence the incidence of voids in small and large area solder joints that simulate,respectively,the 1st and 2nd level joints in LED modules and discuss mitigation strategies appropriate to each level. They will also report the results of a study on the effect on the incidence of voids of flux medium formulation and the optimization of the thermal profile to ensure that most of the volatiles are released early in the reflow process.

Due to the ongoing trend towards miniaturization of power components,the need for increased thermal conductivity of solder joints in SMT processes gains more and more importance. Therefore,the role of void free solder joints in power electronics becomes more central. Voids developed during soldering reduce the actual thermal transfer and can cause thermal damage of the power components up to their failure. For this reason,the company has developed a new technique to minimize the formation of these voids during the soldering process. The result of this development is a universal technique to reduce voids in the liquid solder between component and PCB by applying a mechanic sinusoidal actuation. Primarily the PCB is stimulated by a longitudinal wave with an amplitude of less than 10 µm on the PCB level. During this sinusoidal actuation of the PCB in a defined frequency range,the self-resonances of this area are stimulated regardless of the PCB layout. The low starting frequency of the sweep stimulation ensures a gentle,homogeneous propagation of the vibrations in the PCB without damaging the molecule chains (e.g. in FR-4). The intensification of the frequency causes a stiffening of the PCB substrate,an increase in the elastic modulus,and,because of the reduced damping factor,an improved energy transmission of the liquid solder. Thereby areas with low density,so-called voids are moved out of the solder joint by the vibration. Since a sinusoidal actuation of the PCB in a defined frequency range is actuated over the complete spectrum of this range,all the self-resonances of the PCB in this frequency range are stimulated,too. By this,the liquid solder is stimulated repeatedly by the vibration propagation in a relative shearing motion leading to a reduction of voids in the solder joint. The sweep stimulation onto the components is absorbed mostly by the liquid solder,which protects the components from damage caused by vibration transfer. Positive side effects of the sweep stimulation are the centering of the components on the pad and an optimized spreading of the solder on the pad. The process of void minimization takes place within seconds without causing any significant increase in cycle time.

PCB manufacturers use a wide variety of solder pastes and fluxes including No-Clean,RMA and OA,both leaded and lead-free within their processes. As part of the manufacturing process,components are soldered using reflow ovens and/or wave solder systems. Burnt-in flux residues may result on the PCB surface as well as in and around components. It has been well documented that flux residues can lead to failure mechanisms such as leakage current,electrochemical migration and dendritic growth and these can negatively impact the reliability of the PCB. If OA paste and flux is used,cleaning is required using either a DI-water or chemically assisted aqueous cleaning process. Depending on the degree of reliability required,RMA and No-Clean residues may need to be cleaned as well. Once a manufacturer decides to implement a cleaning process,how does one assess its effectiveness? Based on IPC TM-650 guidelines,there are numerous tests that can be implemented to assess PCB cleanliness. These include ionic contamination,ion chromatography and SIR to name a few. The procedures are well documented and the results can be interpreted through industry developed standards. Ionic Conductivity analysis measures conductivity related to amounts of ionic materials (extracted from the PCB) present in solution and is usually expressed as equivalents of sodium chloride in micrograms per unit surface area (µg NaCl Eq./cm2) of the sample. Ion Chromatography analysis measures individual ionic species (type and level of residue). However,each test is based on total board extraction. As there may be a high contamination area within the PCB that may not be detected with standard ion chromatography analysis,a manufacturer may elect to analyze a specific component or part of a PCB by using a localized extraction method coupled with Ion Chromatography. This study was conducted to assess PCB Cleanliness Assessment Methodologies including visual inspection,Ion Chromatography (IC) and SIR analyses resulting from a spray-in-air cleaning process with benchmark parameters. Seven lead-free No-Clean,RMA and OA paste types were considered. The test vehicle used was the IPC-B-52. Additionally,the authors chose several PCB areas for IC analysis via localized extraction and compared all results for overall cleanliness assessment.