Imbalanced weakly and strongly edge-coupled differential pairs on printed circuit boards (PCBs),both microstrip (MS) and stripline (SL),are studied under different conditions using mixed-mode S-parameters. The r ate of coupling between the lines influences both signal integrity (SI) and electromagnetic compatibility (EMC) of the PCB design. Weakly coupled lines are preferable for SI,but this is not always the case for EMI. Common-mode and mode conversion that negatively affect EMC are typically higher in the weakly coupled cases than in the corresponding strongly-coupled. This is due to technological factors such as the difference in lengths of lines in a differential pair; trapezoid cross-section of signal traces; copper foil roughness; solder mask over microstrip lines; and presence of an epoxy-resin pocket between the stripline traces. In this work,results of 3D full-wave numerical electromagnetic modeling,taking into account these various technological features,are compared with the measured results on the designed test fixtures.

It is common for PCBs used for high frequency RF or high speed digital applications,to be tested for an impedance value prior to shipping the board. The controlled impedance board is typically specified to a nominal impedance value with a given tolerance. Some time ago a tolerance of ± 10% was considered acceptable however recently and with more demanding applications,the impedance tolerance is often much narrower. Understanding the many aspects of impedance is beneficial to the PCB fabricator and designer,who are often required to make a judgment for product shipment based on the impedance measurement. There are several different types of impedance however characteristic impedance is normally specified for a controlled impedance PCB. This circuit property has many variables and some variables are related to the PCB manufacturing process,some are associated with material properties and some variables are due to measurement techniques. Additionally,some of these variables are more or less dominate for a particular type of circuit design and / or construction. This paper will give an overview of the basic theory for impedance,with an emphasis on characteristic impedance for circuits of different design types. Microstrip,grounded coplanar waveguide (GCPW) and stripline structures will be discussed with their unique impedance attributes. PCB fabrication related variables,as well as material variables,will be illustrated using modeling software and verified with measured results. The variables associated with impedance measurement are many and details will be given for several related issues. One variable,often not recognized,is masking and that is how the impedance value of a circuit can be altered due to an impedance spike which is located prior to the body of the circuit. Masking can cause inaccuracies for impedance measurements and there are ways to minimize this concern,which will be illustrated. The impact on impedance resolution and accuracy due to rise time will also be demonstrated with measured examples.

A novel lead-free solder alloy 90.6Sn3.2Ag0.7Cu5.5Sb (SACSb),was developed targeted for high reliability with a wide service temperature capability. The alloy exhibited a melting temperature range of 223 to 232?C,reflowable at profile with peak temperature 245?C and 255?C,with ambient temperature Yield Stress 60MPa,UTS 77 MPa,and ductility 28%,and a higher stress than both SAC305 and 90.9Sn3.8Ag0.7Cu3Bi1.45Sb0.15Ni (SACBSbN),the latter two alloys were used as controls. When tested at 140?C and 165?C,the die shear stress of SACSb was comparable with SACBSbN but higher than SAC305,and the ductility was higher than both SACBSbN and SAC305,with SACBSbN exhibiting distinct brittle behavior. When aged at 125?C and 175?C,the die shear strength of SACSb was comparable or higher than both controls. When pretreated with a harsh condition,a temperature-shock test (-55?C/155?C) for 3000 cycles,the die shear strength of SACSb was 8 times of that of SACBSbN and SAC305. When pre-conditioned using a temperature-cycling test (-40?C/175?C) for 3000 cycles,the die shear strength of SACSb was 11 to 20 times higher than that of SACBSbN and SAC305,depending on the flux type used. Both SACSb and SACBSbN are alloys based on SnAgCu,but reinforced with precipitate hardening and solution hardening,with the use of additives including Sb,Ni,and Bi. SACSb exhibited a finer microstructure with less particles dispersed,while SACBSbN exhibited more particles with some blocky Ag3Sn plates or rods. SACSb is rigid and ductile,while SACBSbN is rigid but brittle. Under the harsh test condition where ?T was high,the dimension mismatch between parts and substrate became very significant due to CTE mismatch. This significant dimension mismatch would cause a brittle joint to crack quickly,as seen on SACBSbN. The challenge was more tolerable for a ductile joint,as shown by SACSb. Accordingly SACSb showed a much better reliability than SACBSbN under harsh conditions,including high testing temperature and large ?T. Overall,to achieve high reliability under a wide service temperature environment,a balanced ductility and rigidity for solder alloy is critical for success.

Electronics manufacturers are searching for new lead-free solders that can improve upon SAC305 voiding performance and that exceed the current thermal cycle performance of this solder in harsh environments,all the while being processed at or near current typical SAC305 peak temperatures. This paper compares -40ºC to 125ºC,thermal cycle test (TCT) results of boards built with SAC305 and a newSAC347+Bi/Sb/Ni/Co solder paste,which were assembled to intentionally contain three levels of voiding,ranging from 0%to 0.5%,5% to 20% and higher than 20%,in order to not only observe variation in TCT performance but find any correlation between voiding levels of up to 30% and the corresponding thermal cycle reliability of the solder joint.

Creep corrosion on printed circuit boards (PCBs) is the corrosion of copper metallization and the creeping of the copper corrosion products across the PCB surfaces to the extent that they may electrically short circuit neighboring features on the PCBs. The paper will report the results of a round robin evaluation of the modified iNEMI creep corrosion qualification test. The earlier versions of the test involved testing in a specially designed flower of sulfur (FoS) chamber for 10 days at nominally 81% humidity level provided by KCl saturated salt solution. The modification to the iNEMI test was the change to three 5-day test runs,the first 5 days at 31% relative humidity provided by MgCl2saturated salt solution,the 2nd5 days at 47% relative humidity provided by NH4NO3saturated salt solution and the 3rd5 days at 81% relative humidity provided by KCl saturated salt solution. The rest of the test procedure remained unchanged,with the iNEMI designed setup providing somewhat controlled and reproducible concentration of chlorine gas and a tray of sulfur for providing sulfur vapors. As usual the test was run at a constant 50oC. The paper will compare the round robin test results from three companies on immersion silver (ImAg),electroless nickel immersion gold (ENIG) and organic solderability preservative (OSP) finished PCBs soldered using organic acid (OR) and rosin (RO) fluxes. As expected,the ENIG finished PCBs suffered the most creep corrosion while the OSP finished PCBs suffered the least creep corrosion. The paper will also list the copper and silver corrosion rates experienced during the test runs and discuss means of better control of these corrosion rates.

The European Union RoHS directive took effect in 2006,and of the 6 restricted materials,the elimination of lead from electronic devices took the most development effort and had the worst degrading effect on hardware reliability. One negative impact was the brittleness of the lead-free solder alloys that replaced the industry favorite,ductile Sn-Pb eutectic alloy. Another was the unexpected occurrence of creep corrosion on printed circuit boards using alternative PCB surface finishes. Along with the implementation of RoHS,the miniaturization of circuits,the expansion of IT markets in developing countries with high-levels of sulfur-bearing gaseous pollution,and the trend towards energy saving by resorting to free-air cooling,have all led to increased rates of corrosion-related hardware failures associated with particulate and gaseous contamination. The IT industry has taken a two-pronged approach to mitigating these failures: (1) by making the products more robust against contamination and high humidity levels; and (2) by gaining better understanding of the allowable levels of contamination,temperature and humidity under which IT equipment can operate reliably. Additionally,many points along the supply chain have been identified where corrosion can form,and the additive effects may or may not be detected by testing or manifest themselves before delivery to the end-user. Failures at this point may be due to the cumulative effect of numerous “micro-failures” generated throughout the supply chain. However,what remains most frequent are product failures resulting from exposure to elevated pollutant levels and inadequate environmental controls at manufacturing locations. The result is an operating environment that does not meet current manufacturers’ warranty requirements – requirements that have been put into place since the implementation of RoHS. This paper will describe the common modes of corrosion-related hardware failures in the past 10 years,the actions taken to make the products more robust,the understanding of the role played by contamination,and the means of negating their detrimental effects. The case will also be presented for environmental monitoring at various points along the supply chain and the addition of enhanced air cleaning for those locations that do not meet the air quality requirements of the finished devices. Data will be presented that highlight the need for air quality assessments of manufacturing facilities,where enhanced air cleaning is indicated,and the benefit of establishing an ongoing real-time air monitoring program to assure compliance with air quality specifications and warranty requirements.

Over the past few years,studies have shown that Nano-coatings can improve solder paste release and reduce underside cleaning in the print process. Many of these studies have focused on print volume and the improvement of transfer efficiency in small component printing. This paper investigates whether Nano-coated stencils improve repeatability and uniformity in the print process for a range of components sizes. Repeatability and uniformity were defined as how tightly controlled print deposits were from print to print over time. Solder paste inspection (SPI) data was collected and analyzed for the following component types: 01005 up to 1206 Imperial chip components; 0.5mm pitch micro BGA components; 0.4mm pitch up to 1.25mm pitch QFP components and 0.4mm pitch up to 0.6mm pitch QFN components.

The mobile and consumer market is the driving force of the electronics assembly sector,this sector historically has been associated with early adopters of leading edge surface mount technology (SMT). The main driver for adopting state of art SMT is the consumers demand for greater user functionality. Meeting this demand requires integrating more into less,or to give its correct term –Miniaturization. The assembly community has become used to the introduction of new smaller feature sized devices. The next device that will drive this next round of miniaturization is the Metric 0201(M0201). This passive device will measure 250um x 125um and offer a 60% reduction in real-estate to its predecessor. The M0201 will be used in both Systems in Package (S.I.P) and consumer electronic applications. The implementation of the M0201 within the S.I.P application will result in a homogeneous solder paste solution,as a consequence the stencil thickness can be chosen to ensure aperture area ratios are well within the IPC recommendations. However,the implementation of the M0201 device within the mobile and consumer sector will result in a heterogeneous solder paste solution. Within this heterogeneous environment the stencil thickness will be comprised due to the volumetric requirements presented by the mixed technology application. The combination of sub 150um apertures and standard stencil thickness will lead to area ratios falling below the IPC recommendations. Previous research into printing challenging area ratios has focused on an improved method of filling the apertures through the utilization of ultrasonic squeegees and novel stencil coatings. Although the filling process is a major element to the printing process,the release of the aperture is equally as important to delivering a repeatable solder paste deposit. From a release point of view,an aperture is the structure that forms and molds the solder paste deposit. It is also from this aperture that the deposit has to release from. The incumbent aperture design for passive chip devices has been a regular polygon (rectangle) design,one that traces the outline of the device land. Within this study the inclusion of a radius within rectangular aperture geometries will be investigated. The influence of a radius will be measured against the resultant volumetric Cp/Cpk values. The study will include three aperture designs that are compatible with the next generation devices,each aperture design will include six radii profiles. The findings from this investigation will show if any process improvements can be associated with the inclusion of a radius within a regular rectangular aperture design.

Most manufacturers of electronics grade glass fiber reinforcement used in today’s laminates apply treatments to enhance the bonding strength between the inorganic e-glass and the epoxy matrix which surrounds it in the laminate structure. These treatments,when properly formulated and applied on the glass fibers help to prevent glass-resin delamination due to mechanical stresses or due to thermal excursions during the laminate lifecycle. The thermal excursions can include multiple reflow cycles followed by wave soldering and in some common circumstances a cycle or two of rework. However,such laminates continue to develop glass-resin delamination that promotes a form of electro-chemical migration that leads to a loss of electrical insulation resistance between opposing biased conductors. This phenomenon is commonly known as conductive anodic filament (CAF). The glass-resin delamination can also contribute to a reduction in the mechanical flexural strength,which is not the focus of the present paper. The probability of CAF failure is a function of temperature,moisture content,the voltage bias,manufacturing quality and processes,materials and other environmental conditions and physical factors. The present paper discusses the glass treatments and examines the effects of thermal and combined thermal/moisture exposure on the glass-resin interface. Atomic force microscopy is used for examination of sites to track the state of degradation and changes in the mechanical properties. Micro-Fourier transform infrared spectroscopy is used to track the progression and diffusion of the inter-penetrating network formed as a result of inter-diffusion between the glass-treatments and epoxy laminate material. The results of the studies are expected to show the progression of damage and provide unique quality assurance and failure analysis insights into this less reported contributor to printed circuit board quality.

Internet of Things (IoT) adoption pushes the boundaries of Printed Circuit Board (PCB) miniaturization and speed employing more hybrid stack-ups. The complexity of PCB stack up designs,material selection,advanced processing,and subsequent assembly requirements are driving novel approaches to accelerate engineered solutions. To support the aggressive PCB product development cycle times,the accuracy of physics-based predictive modeling must improve,and the number of lengthy Design of Experiments (DoE) minimized. To facilitate this,effective material characterization techniques and modeling capabilities of these complex systems have been developed,with the goal to mitigate risk,increase reliability and reduce engineering time while ensuring a manufacturable solution. In general,the stress induced on interconnects increases as the interconnect size decreases. However,to accurately model the physical behavior (stress and strain) of PCB interconnects in design stack ups during a reflow or lamination processes requires material property information which necessarily is not present on a typical materials’ supplier datasheet. Some parameters are also not readily available using standard measurement techniques. Additionally,typical numbers in a laminate datasheet only apply to a standard glass style and resin content. Glass style and resin content have a dramatic influence on the end product mechanical properties. Also,the composite nature of PCBs not only result in its thermomechanical behavior to differ along the X,Y,and Z directions,but also relax over time due to the viscoelastic nature of the epoxy resin. Therefore,the anisotropic and viscoelastic properties of PCB materials must be measured. The measurement techniques discussed here are not part of any formal IPC testing protocol currently. However,they capture properties of PCB materials at the small scale very effectively. They rely on using a Dynamic Mechanical Analyzer (DMA)instrument for measurement purposes. These advancements in material characterization and modeling provide insights into micro-via reliability for next generation PCB miniaturization and high-speed signals.