The electronics markets place widely varying demands on products,thus necessitating a great deal of complexity with regard to board design and connector technology. A nearly inexhaustible multiplicity of electronic components is available to this end for implementing the respective product concepts. There is of course no universal soldering process which fulfills the requirements of all of these different products at the same time. However,the capability demonstrator board has provided us with the opportunity of exploring the limits of what is feasible and what is not,additionally pointing out the difficulties associated with the reflow soldering process of complex PCBs. In the following pages we will discuss target goals for reflow soldering derived from generally recognized rules and standards,as well as the temperature-time curves (reflow profiles) obtained with the demonstrator board. Our examinations focused primarily on convection reflow soldering,but various results obtained with vapor phase reflow soldering will be discussed comparatively as well.

Whilst many companies invest time,effort and cost into up front work to fix snags which would lead to issues with yield during production,this paper shows the efforts of the company who looks to take things further. With increasing pressure on cost reduction within our industry,companies are looking ever more closely at their manufacturing process. In order to remain globally competitive and even to succeed in their local market every dollar saved here helps the bottom line. However,in many areas there is a danger that lower price equals lower quality and therefore actually results in higher costs in the end. The approach here involves spending a little more money than normal at the start of a project but less than hundreds of dollars and the results show savings of many times more than this outlay. However,it is acknowledged that this does take a little more time to get the job onto the shop floor. The key to this methodology is that it needs the time and effort of a skilled team and time on a production line before the job is started. But as the paper shows it really does improve yield,reduce cost,save the potential issues around repair and gives better reliability. In essence the results of the solder paste printing process are analyzed,after the components are placed,using X-ray and these results compared to the results after reflow soldering. The resultant pre-reflow solder paste shapes are impossible to see with the naked eye or by lifting the components,as the paste would not release evenly. This allows the engineer to determine how differences in printed paste shape and volume react when components are placed on them and how ultimately this affects product quality. Post reflow problems including mid-chip solder balls were found to be common faults,as were issues under BGAs including insufficient solder and shorts. The product is run on a “real line” and the results evaluated. Improvements are then made to the stencil design and other key process parameters to ensure that when in production the board is producing acceptable yields.

Plated Though Hole (PTH) vias are common in the PCB industry,however their impact on electrical performance can sometimes be unclear. The confusion can be due to several different issues. Some PTH related circuit affects are due to frequency dependency,circuit thickness,circuit construction,PTH structure and PTH function. This paper will give summaries of several different studies regarding PTH via influence regarding high frequency RF performance. The typical PTH via functions are signal transition,grounding vias and power transitions. For this work the signal transition and grounding vias will be evaluated. There are several PTH structures and some are through-circuit-via,buried-via,micro-via,etc. Evaluations were done considering through-circuit-vias and buried-vias. The varieties of circuit thickness and construction can be nearly endless,however studies will be done using 2 copper layer circuits (Grounded Coplanar Waveguide) of different thickness using different repetitive grounding via pitch which will show the effectiveness of propagation mode suppression as it relates to different frequencies. Another circuit construction will be considered for evaluating signal vias by using buried vias and through-circuit-vias in a 4 copper layer circuit design. This multilayer construction will evaluate the different PTH vias in regards to frequency dependencies. Additionally,the impact of back-drilling through-circuit-via signal vias will be considered as well.

Currently there is no industry standard test method for measuring dielectric properties of circuit board materials at frequencies greater than about 10 GHz. Various materials vendors and test labs take different approaches to determine these properties. It is common for these different approaches to yield varying values of key properties like permittivity and loss tangent. The D-24C Task Group of IPC has developed this round robin program to assess these various methods from the “bottom up” to determine if standardized methods can be agreed upon to provide the industry with more accurate and valid characteristics of dielectrics used in high-frequency and high-speed applications.

Determining the root cause of a failure in a complex system is a demanding task that requires a structured and disciplined approach. From engaging the appropriate subject-matter experts,to verifying the failure in a particular subsystem,to determining the analytical techniques used,this process can be an overwhelming task. The objective of this paper is to describe the approaches and techniques used in a recent case history,and to provide a summary of methods engaged in analyzing the printed wiring assemblies (PWAs) that were involved in the failure. One of the initial steps taken was to assemble a team of subject-matter experts (SMEs) from the various subsystems that comprise the complex system,prior to verifying the failure. During verification of the failure,it was critical that what caused the failure was not disturbed,otherwise critical information leading to the direct cause could be compromised. SME-developed tests were outlined and executed to perform the verification. Once the failure was verified,techniques such as fishbone diagrams were used for causal analysis. The use of root cause tools led the team from a systemic failure,down to a set of PWAs. Once the suspected root cause was determined to be within a particular PWA,a formidable list of analysis techniques were used to narrow down the precise cause. These included,but were not limited to: Bench-top electrical testing,visual examinations,real-time X-ray,Computed Tomography (CT) scans,Printed Circuit Board (PCB) cross-section analysis,scanning electronic microscope (SEM) evaluation,and data package pedigree review. This paper provides a structured,methodical approach to failure analysis and root cause determination for a very complex system. It can be utilized as a guideline for other highly complex systems,or other systems where the cause is suspected to be within a PWA.

Thermo-electric coolers (TEC's) are becoming increasingly popular in the medical device industry,where design space is limited and high heat transfer capacity is needed. For a Computed Tomography (CT) reference module application,an integrated TEC + copper heat pipe assembly was used to regulate temperature of a precision photodiode sensor array. Due to the extended service life of a CT scanner,10 year reliability of all components is required. Through accelerated testing of the TEC assembly using rapid switching of the TEC in both heating and cooling modes,it was determined that the existing design only met one year of life. Failure analysis was performed on the TEC units and dice cracking as well as burned dice due to thermal hotspots were observed. Through discussions with the TEC vendor,a higher temperature TEC solder material was evaluated on future assemblies,allowing for higher thermal excursions and also better CTE matching to the TEC ceramic. Subsequent reliability testing on the higher temperature solder assemblies showed more than 3x performance improvement,thereby exceeding the 10 year life requirement. In addition high temperature/humidity/biased (85C/85%RH) was tested for 500hr. At the end of the test a small drift in performance was observed,failure analysis will be presented. In addition to the design improvement and learnings,the reliability experimental setup showcased an effective method for acquiring quick cycling data on TEC while evaluating the assemblies over a wide thermal range. This setup utilized the self-heating/cooling of the TEC and mounted the assembly on a fixed temperature plate. Finally,specifics as to boundary condition testing of a TEC assembly and also the PID control implementation of the TEC via an FPGA based design will be discussed.

The selective soldering application requires a combination of performance attributes that traditional liquid fluxes designed for wave soldering applications cannot fulfill. First,the flux deposition on the board needs to be carefully controlled. Proper fine tuning of the flux physicochemical characteristics combined with a process optimization are mandatory to strike the right balance between solderability and reliability. However,localization of the flux residue through the drop jet process is not enough to guarantee the expected performance level. The flux needs to be designed to minimize the impact of unavoidable spreading and splashing events. From this perspective a fundamental understanding of the relationships between formulation and reliability is critical. In this application,thermal history of the flux residues (from room temperature to solder liquidus) is a key performance driver. Finally,it is necessary to conduct statistically designed experiments on industrial selective soldering machines in order to map the relationships between flux characteristics and selective process friendliness. In this area,multiple performance attributes will be considered: compatibility with drop jet dispensing (clogging effects,cleaning frequency,and satellite formation),spreading (in actual processing conditions,with multiple solder resist types) and soldering performance as measured by barrel filling and defect production in challenging thermal conditions. Therefore,a strong partnership between the flux designer and the equipment manufacturer is a key component of a robust flux design for selective soldering.

Selective soldering,along with pin-in-paste reflow and press fit,is the primary assembly method for through-hole components. The reflow process is limited by component dimensions and heat resistance. Press fit becomes expensive when defects occur that cannot be repaired. Electronic manufacturing services realize that surface mount technology (SMT)cannot replace the through-hole technology completely. The selective soldering process offers opportunities to make solder connections on different levels,connecting housings,junction boxes,aluminum parts,stacking PCBs and more. Designers of new board assemblies can benefit from the specialized soldering nozzles and robotics capabilities that modern selective soldering machines offer. Selective soldering can be achieved under an angle (tilt) as in wave soldering or horizontally with different shaped nozzles and nozzle materials. All have different properties and can be applied to successfully soldering the most complex assemblies. In order to optimize production and soldering efficiency,assembly engineers should be involved in the design for assembly process. Knowledge of the selective soldering process and nozzle technology may offer competitive advantages when implemented in new design and assembly processes. Studies have been done to determine minimum distances to adjacent components,especially surface mount devices (SMD). Questions asked include,“What pin to hole ratio provides the best hole filling?” and “How much influence has flux selection on soldering results,and which nozzles should be used?” Historical data is combined with several design of experiments looking for soldering defects,such as bridging,but also seeking process optimization to achieve the best hole filling. Hole filling is critical for high thermal mass boards. The thick copper layers absorb a great deal of heat from the preheating and liquid solder. Special design modifications will result in more heat in the solder barrel,which will guide the solder to the solder destination side of the board. Combining the right nozzle selection with correct solder acceleration and deceleration will ensure that even the most difficult to create joints will meet the IPC-A-610 requirements.

Wave soldering of pin through hole devices has been around for a very long time. It is a process that everyone says will go away and each year it is still being used. In the industry,wave solder is to this day considered more art than science,although there is much more effort to characterize the process as much as possible. Pin through hole devices tend to be lower cost than surface mount technology components and through hole soldering tend to have robust solder joints that,in most cases,will outlast surface mount components. The wave solder process has many variables that an engineer need to manage to meet the hole fill requirements on complex board designs: board design,component design,flux types and application methods,pre-heating,solder alloy,dross formation,wave types,etc. This paper will explore the alternatives to wave solder,such as paste in hole,selective solder,and robotic soldering processes. The advantages and disadvantages will be discussed for each process type,in addition to how each process works. The paper will explore some of the key items in making a decision on which process is most suitable for the application being considered.

High Power Transistors contain materials and structure that pose unique challenges to AXI technologies. The work discusses traditional AXI imaging and processing techniques and their limitations in very heavily shaded,and non-uniformly shaded situations. The work further discusses methods for voiding detection and presents a novel technique developed to overcome challenges presented by Copper Coin Power Transistors. Lastly the work presents considerations for optimal region size and data presentation to support testing to component-level voiding specifications.