Creep corrosion testing of printed circuit boards (PCBs) using a specially designed flowers of sulfur chamber has been developed by an iNEMI technical committee. The iNEMI test is based on a chamber that is 300-mm cube acrylic box with 8-paddle wheels rotating at 20 RPM that can accommodate 8 PCBs. In one embodiment of the test setup,the sulfur vapor with controlled concentration is provided by two 100-mm diameter petri dishes containing beds of sulfur and by maintaining the chamber temperature at 50oC. The relative humidity is maintained at 81% using two 80-mm diameter petri dishes containing KCl saturated solution. The source of chlorine,while repeatable though time varying in concentration,is provided by 40-ml household bleach in a 100-ml beaker. The creep corrosion qualification test has successfully predicted creep corrosion on specially designed and manufactured unpopulated printed circuit boards of various finishes,soldered with rosin or with organic acid flux. Creep corrosion similar in morphology to that observed in the field has been reproduced in the iNEMI tests. This paper describes the iNEMI creep corrosion testing of a number of fully populated PCBs of various technologies and vintages of known field reliability. The results confirm the finding that prebaking the PCBs is a necessary condition for creep corrosion to occur in the iNEMI flowers of sulfur chamber. The creep corrosion results on prebaked PCBs of 7 different technologies agreed with the field reliability experiences. The PCBs from lots that suffered creep corrosion in the highly polluted geographies showed creep corrosion of similar morphology in the flowers of sulfur creep corrosion test; whereas,the PCBs from lots that did not suffer creep corrosion in the field,survived the flowers of sulfur test with little or no creep corrosion. The iNEMI PCB creep corrosion qualification test is now sufficiently well developed to be adopted as an industry standard test. The paper will also show some evidence that long-term storage before usage may eliminate creep corrosion.

Millimeter-wave (mmWave) frequency applications are becoming more common. There are applications utilizing PCB technology at 60 GHz,77 GHz and many other mmWave frequencies. When designing a PCB for mmWave frequency,the properties of the circuit materials need to be considered since they can be critical to the success of the application. Understanding the properties of circuit materials at these frequencies is very important. This paper will give an overview of which circuit material properties are important to mmWave frequency applications using PCBs. There will be data supplied which demonstrates why these properties are essential to the circuit material selection for mmWave applications. Some properties discussed will be dielectric constant (Dk) control,dissipation factor,moisture absorption,thickness control and TCDk (Temperature Coefficient of Dk). Measured comparisons will be shown for insertion loss and Dk versus frequency for different types of circuit materials up to 110 GHz. As part of the test data,the impact on circuit performance due to TCDk and moisture absorption will be shown at mmWave frequencies.

Higher functionality,higher performance and higher reliability with smaller real estate are the mantras of any electronic device and the future guarantees more of the same. In order to achieve the requirements of these devices,designs must incorporate fine line and via pitch while maintain good circuitry adhesion at a smooth plating-resin interface to improve signal integrity. The Semi-Additive Process (SAP) is a production-proven method used on low dielectric loss tangent (Df) build-up materials that enables the manufacture of ultra-fine circuitry. The standard SAP process utilizes some roughening or texturing of the dielectric substrate in order to achieve sufficient adhesion; however,the rough surface at the plating-resin interface potentially increases transmission loss at high signal speeds. To promote signal integrity at high-frequency signal transmission,the next SAP process should provide high plating-resin adhesion as well as very smooth interface in between. The next build-up material in demand should present high thermal and dimension stability,good chemical resistance to survive many cure and reflow processes in circuitry manufacture. It should also deliver excellent electric properties including high insulation reliability,low Df and low dielectric constant (Dk) to guarantee good signal integrity in high frequency signal transmission. Meanwhile,the good properties above bring challenges to the SAP process. This paper will discuss a new SAP process for low loss build-up materials with low desmear roughness (Ra= 40-100 nm) and excellent adhesion (610-680gf/cm) at various processing conditions. Along with the process flow,the current work will also present results and a discussion regarding characterization on the morphology and composition of resin and/or metal plating surfaces using scanning electron microscopy (SEM) and energy dispersive X-ray spectroscopy (EDX),surface roughness analysis,plating-resin adhesion evaluation from 90o peel tests.

Six decades of legacy experience makes the specification and production of screens and masks to produce repeatable precision results mostly an exercise in matching engineering needs with known ink and substrate performance to specify screen and stencil characteristics. New types of functional and electronic devices,flex circuits and medical sensors,industrial printing,ever finer circuit pitch,downstream additive manufacturing processes coupled with new substrates and inks that are not optimized for the rheological,mechanical and chemical characteristics for the screen printing process are becoming a customer driven norm. Many of these materials do not work within legacy screen making,curing or press set-up parameters. Many new materials and end uses require new screen specifications. This case study presents a DOE based method to pre-test new materials to categorize ink and substrate rheology,compatibility and printed feature requirement to allow more accurate screen recipes and on-press setting expectations before the project enters the production environment where time and materials are most costly and on-press adjustment methods may be constrained by locked,documented or regulatory processes,equipment limitations and employee experience.

One of the major concerns with screen printing of low temperature curing polymer thick film (PTF) pastes onto common flexible PET substrate materials is the overwhelming spread of the paste beyond the design line width after printing. Industry observation and controlled testing have shown this spread can be as much as 80% over the circuit design's intended line width. This issue prevents designers from increasing circuit density and/or reducing circuit real estate without incorporating other,more involved and more costly patterning methods. In many cases,flexible circuit fabricators desiring finer more accurate circuit elements may have to subcontract parts out of house in order to incorporate other patterning methods and in-turn lose control of both cost and lead time to the hands of their subcontracting partners. This paper will provide results of numerous in-house and field testing,comparing printed line width control,edge definition,and improved conductivity of printed polymer Ag conductors on different flexible PET substrates with testing done on a company developed screen emulsion stencil material and substrate material.

This study investigates the scooping effect during solder paste printing as a function of aperture width,aperture length and squeegee pressure. The percent of the theoretical volume deposited depends on the PWB topography. A typical bimodal percent volume distribution is attributed to poor release apertures and large apertures,where scooping takes place,yielding percent volumes <100%,while SMD apertures and apertures near PWB features that raise the stencil yield percent volumes >100%. This printing experiment is done with a concomitant validation of the printing process using standard 3D Solder Paste Inspection (SPI) equipment. The data collected from the SPI equipment included the solder paste volume,printed area,solder paste height and x-y offset printing. The volume data for each aperture width exhibits a Gaussian distribution,with the mean and standard deviation changing as a function of aperture width. For small apertures poor release is observed,while the reduction of the solder paste volume for large apertures is attributed to the appearance of the scooping effect at 0.070” aperture width. The Gaussian distributions,when analyzed separately,indicate that the printing process for each aperture width is under control yielding C-pk greater than 1.33 (DPMO <63),with USL and LSL set at ±20% from the mean volume. We also investigated the release of apertures with and without round corners. The former exhibited better solder paste release.

Solder paste printing is the first step in the surface mount manufacturing process for PCBA assembly. When the solder paste printing process is uncontrolled,defects can be produced,which may not become apparent until the PCBA is downstream. Even though defects are present,the PCBAs may not be scrapped because rework can fix the defects. This can make the cost of poor quality appear low because the scrap rate is low. These rework loops are also called the hidden factory. The hidden factory means that these rework loops hide the cost of poor quality associated with fixing the defects because the PCBA was not produced right the first time. Rework also reduces efficiency because of the time required to fix the defect. From a lean perspective,rework is the waste of defect,which is one of the eight wastes. The surface mount solder paste printing process has a solder paste inspection process immediately afterwards. This inspection process measures certain characteristics of the solder paste,such as volume,height,area and offset. The inspection process will alert the operator to a potential defect. When an alert happens,the operator will look at the PCBA to determine whether or not there is a true defect. If the operator determines that there is no defect,or the alert was a false failure,the operator will manually override the solder paste inspection machine and label the PCBA as a pass. The PCBA then proceeds to the parts placement machines. The risk present in the manual override is that it relies on operator judgement. There is also the risk that if too many false failures present themselves,the operator may be led to believe that every alert is a false failure and immediately override the alert even though a defect is present. This can be a very high risk scenario,especially with PCBAs that go into medical devices. Some manufacturers are looking into turning off the override function,which will stop the line if the automated inspection system sees a potential defect. This will prevent defective PCBAs from getting to the customer but will cause efficiency loss,and increased cost,when the line stops. There is also the risk of not getting the customer the product on time. This makes it real important to identify the critical inputs to the solder paste printing process and ensure they are controlled so that manufacturers are able to optimize the output of the process. This paper will discuss how Lean Six Sigma techniques were used to optimize the solder paste printing process. It will highlight how a cross-functional team used the structured Define,Measure,Analyze,Improve and Control (DMAIC) methodology to identify and control the critical inputs. The advantage of the Lean Six Sigma methodology is that it guides the team through the rigorous structured process so that all possible inputs are considered and the critical ones can be identified. The cross-functional team is led by a Master Black Belt or Black Belt,who is skilled in both the technical aspects of the Lean Six Sigma methodology along with the soft skills needed for team management. The paper will demonstrate the use of tools such as the IPO (Input-Process-Output) diagram,Cause and Effect Diagram,Fractional Factorial Experiments and Full Factorial Experiments. It will then show how pilot runs were made in order to confirm the model,which was drawn from the designed experiments.

Existing coated microstrip trace impedance estimation usually uses the dielectric constant (Dk) of solder mask ink measured at 1 MHz from its datasheet. Or,some printed circuit board (PCB) manufacturers tend to first calculate the impedance of surface microstrip line and multiply this value by an empirical coefficient such as 0.94 or 0.96 to get the impedance of coated microstrip line. In addition,PCB engineers always underestimate the loss caused by solder mask upon microstrip line (conductor-backed coplanar wave guide in this paper) of flexible printed circuit (FPC)or server PCB. However,as signal speeds move into the 10 Gbps range,standard FR-4 is gradually being replaced by low dissipation factor (Df) material like modified FR4 or PPO and the Df gap between laminate and solder mask is huge. Thus,it is significant to evaluate the effects of solder mask in 3D modeling and EM simulation. This paper describes a set of methods to extract the permittivity and dissipation factor of a standard and a low-loss solder mask ink. The measured S parameters have been de-embedded by AFR (Automotive Fixture Removed) calibration method. When modeling,copper surface roughness has been considered.

Conformal coatings are applied to protect electronic assemblies from adventitious environmental factors,which include,for example,corrosive gases,corrosive fluids and high humidity. Whenever there is a significant level of humidity,there is always the opportunity for parts of the assembly to drop beneath the dew point,thus resulting in the formation of condensed water on the surface of the assembly,which can significantly reduce the insulation resistance of the boards surface,resulting in malfunctioning electronics. While the characterization of coating performance under high humidity conditions is detailed,in well accepted IPC and IEC standards,the performance and testing under condensing conditions is not so well developed. This situation largely reflects the hardware challenge. Most humidity chambers are designed to achieve stable,well controlled humidity and temperature conditions,but none of these offer condensing options. Therefore the user has to improvise. A common approach to attempt to achieve condensing conditions is to ramp at a fast enough rate to cause condensation,a feature the humidity chamber designers have by and large,successfully managed to remove. Alternatively chambers run very close to 100% relative humidity and hence at this condition condensation will occur in various parts of the chamber. An immediate drawback of these approaches is that chambers of different designs will perform differently,and will be sensitive to small drops in cooling performance. There are many alternative approaches to achieving condensation,and these are described in ISO,IEC,ASTM and others,and commonly attempt to drive a chamber into producing condensation,against the anticipated use condition,and hence sensors in the chamber detect the additional moisture and will work to reduce the humidity level to the required set-point. Thus,the level of experimental control will be very dependent on the chamber performance,and variability across chamber manufacturers can be expected. A new approach has been developed where the test board is mounted on a substrate whose temperature can be independently controlled without changing the ambient condition. Thus,the temperature of the test board can be depressed below ambient to any desired point and hence,produce condensation at different levels. It is then,therefore,straightforward to cycle between condensing and non-condensing conditions on the test board in a constant ambient environment. The technique has been demonstrated to be repeatable and controllable,with the user able to select a temperature differential that matches their worst in-use conditions,or to understand the performance of their system under a range of condensing conditions. The data for a range of conformal coatings are presented,and correlated back to the conformal coating material type,and coverage and thickness by cross-sectioning.

Pitting/Crevice corrosion on printed circuit boards has not been well studied in the industry. This mechanism has been seen at small solder mask openings near circuit traces on printed circuit boards when stored or shipped in a humid environment with no-clean soldering fluxes that passed all standard tests. Failure modes are theorized to be driven by openings or defects in solder masks and humidity levels that mobilized surface contamination. Harsh environments,that can bring in outside contaminates,can be one of the factors that causes pitting corrosion to initiate and grow. In many of the applications employing high density assemblies processed with mixed technology,the quality of the laminate construction,the assembly process and quality of design are critical. Solder mask type (glossy or matte) curing and application process have been known to cause corrosion issues. Often the solder mask employed (manufacturer,chemical structure,Tg,filler type and thickness) can be factors that lead to pitting corrosion and should be understood. In some cases,the thickness,quality and roughness of the copper at the surface can contribute to corrosion. The High Density Packaging User Group Consortium (HDP User Group) Electro-Chemical Migration (ECM) team is investigating pitting / crevice corrosion failure mechanism and the factors that cause the defect to occur. The purpose of the research is to report current findings and the experimental description for qualifying soldering materials and to determine conditions needed to mitigate this failure mechanism.