Evaluation of Under-Stencil-Cleaning-Papers

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Solder paste screen printing is known to be one of the most difficult processes to quality assure in Printed Board Assembly (PBA) manufacturing. An important process step in solder paste screenprinting is the under stencil cleaning process and one of the key materials in this process is the cleaning paper. This,often neglected,material affects the cleaning process and thereby also the print quality. It is therefore important to perform tests of different cleaning papers before one could be chosen. This article describes how cleaning papers can be tested and it also tells how big differences it can be between different materials.

Author(s)
Lars Bruno
Resource Type
Technical Paper
Event
IPC APEX EXPO 2015

The Effects of PCB Fabrication on High-Frequency Electrical Performance

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Achieving optimum high-frequency printed-circuit-board (PCB) performance is not simply a matter of specifying the best possible PCB material,but can be significantly impacted by PCB fabrication practices. In addition to appropriate circuit materials and circuit design configurations to meet target performance goals,a number of PCB material-related issues can affect final performance,including the use of solder mask,the PCB copper plating thickness,the conductor trapezoidal effect,and plating finish; understanding the effects of these material issues can help when fabricating high-frequency circuits for the best possible electrical performance.

Author(s)
John Coonrod
Resource Type
Technical Paper
Event
IPC APEX EXPO 2015

Characterization of Printed Circuit Board Material & Manufacturing Technology for High Frequency

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Today's Electronic Industry is changing at a high pace. The root causes are manifold. So world population is growing up to eight billions and gives new challenges in terms of urbanization,mobility and connectivity. Consequently,there will raise up a lot of new business models for the electronic industry. Connectivity will take a large influence on our lives. Concepts like Industry 4.0,internet of things,M2M communication,smart homes or communication in or to cars are growing up. All these applications are based on the same demanding requirement – a high amount of data and increased data transfer rate. These arguments bring up large challenges to the Printed Circuit Board (PCB) design and manufacturing. This paper investigates the impact of different PCB manufacturing technologies and their relation to their high frequency behavior. In the course of the paper a brief overview of PCB manufacturing capabilities is be presented. Moreover,signal losses in terms of frequency,design,manufacturing processes,and substrate materials are investigated. The aim of this paper is,to develop a concept to use materials in combination with optimized PCB manufacturing processes,which allows a significant reduction of losses and increased signal quality. First analysis demonstrate,that for increased signal frequency,demanded by growing data transfer rate,the capabilities to manufacture high frequency PCBs become a key factor in terms of losses. Base materials with particularly high speed properties like very low dielectric constants are used for efficient design of high speed data link lines. Furthermore,copper foils with very low treatment are to be used to minimize loss caused by the skin effect. In addition to the materials composition,the design of high speed circuits is optimized with the help of comprehensive simulations studies. The work on this paper focuses on requirements and main questions arising during the PCB manufacturing process in order to improve the system in terms of losses. For that matter,there are several approaches that can be used. For example,the optimization of the structuring process,the use of efficient interconnection capabilities,and dedicated surface finishing can be used to reduce losses and preserve signal integrity. In this study,a comparison of different PCB manufacturing processes by using measurement results of demonstrators that imitate real PCB applications will be discussed. Special attention has be drawn to the manufacturing capabilities which are optimized for high frequency requirements and focused to avoid signal loss. Different line structures like microstrip lines,coplanar waveguides,and surface integrated waveguides are used for this assessment. This research was carried out by Austria Technologie & Systemtechnik AG (AT&S AG),in cooperation with Vienna University of Technology,Institute of Electrodynamics,Microwave and Circuit Engineering.

Author(s)
Oliver Huber,Erich Schlaffer,Thomas Faseth,Holger Arthaber
Resource Type
Technical Paper
Event
IPC APEX EXPO 2015

High Frequency Dk and Df Test Methods Comparison High Density User Group (HDP) Project

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The High Density Packaging (HDP) user group has completed a project to evaluate the majority of viable Dk (Dielectric Constant)/Df (Dissipation Factor) and delay/loss electrical test methods,with a focus on the methods used for speeds above 2 GHz. A comparison of test methods from 1 to 2 GHz through to higher test frequencies was desired,testing a variety of laminate materials (standard volume production with UL approval,low loss,and "halogen-free" laminate materials). Variations in the test board material resin content/construction and copper foil surface roughness/type were minimized. Problems with Dk/Df and loss test methods and discrepancies in results are identified,as well as possible correlations or relationships among these higher speed test methods.

Author(s)
Karl Sauter,Joe Smetana
Resource Type
Technical Paper
Event
IPC APEX EXPO 2015

Dissolution of Metal Foils in Common Beverages

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How susceptible are the metals used in modern electronics manufacturing to corrosion by common beverages? This is a question of interest,especially to manufacturers,retailers and to a certain extent end customers. In this study the dissolution of aluminum,copper,gold,iron,lead,nickel,SAC305 solder,silver,tin and zinc was examined. Individual foils of these materials were fully immersed in one of sixteen chosen beverages and heated for 3 days at 40°C. The resulting solutions were analyzed using ICP-OES. The data were examined in light of the known pH,conductivity and ionic contents of the beverages,determined in previous work. Conclusions about the relative susceptibility to corrosion of the various metals and the corrosive power of the different beverages are made.

Author(s)
Bev Christian,Nancy Wang,Mark Pritzker,Daniella Gillanders,Gyubok Baik,Weiyi Zhang,Joanna Litingtun,Brian Kim
Resource Type
Technical Paper
Event
IPC APEX EXPO 2015

Characterization,Prevention and Removal of Particulate Matter on Printed Circuit Boards

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Particulate matter contamination is known to become wet and therefore ionically conductive and corrosive if the humidity in the environment rises above the deliquescence relative humidity (DRH) of the particulate matter. In wet condition,particulate matter can electrically bridge closely spaced features on printed circuit boards (PCBs),leading to their electrical failure. Failures attributed to particulate matter have even been observed in data centers where the gaseous contamination levels are low enough to meet the ANSI/ISA-71.04-2013 G1 severity level. The combination of miniaturization of electronic components,the reduction of feature spacing on PCBs and the loosening of the data center temperature and humidity envelope to save energy is making electronic hardware more prone to failure due to particulate matter. The characterization of particulate matter on PCBs is challenging because of the small amount of particulate matter available for analysis. The objective of this paper is to develop and describe a practical,routine means of measuring the DRH of minute quantities of particulate matter (1mg or less) found on PCBs. Data center particle filtration schemes and means of removing the particulate matter from PCBs will also be presented.

Author(s)
Prabjit Singh,Patrick Ruch,Sarmenio Saliba,Christopher Muller
Resource Type
Technical Paper
Event
IPC APEX EXPO 2015

Corrosion Resistant Servers for Free-Air Cooling Data Centers

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The demand for compute capability is growing rapidly fueling the ever rising consumption of power by data centers the worldwide. This growth in power consumption presents a challenge to data center total cost of ownership. Free-air cooling is one of the industrial trends in reducing power consumption,the power usage effectiveness (PUE) ratio,and the total cost of ownership (TCO). Free-air cooling is a viable approach in many parts of the world where the air is reasonably clean. In Eastern China,the poor quality of air,high in particle and gaseous contamination,is a major obstacle to free-air cooling. Servers exposed to outside air blowing in to data centers will corrode and fail at high rate. The poor reliability of hardware increase TCO dramatically. This paper describes a corrosion resistant server design suitable for reliable operation in a free-air cooling data center located in Eastern China where the indoor air quality can be as poor as ASHRAE (American Society of Heating,Refrigerating and Air-Conditioning Engineers) severity level G3. An accelerated corrosion test method of verifying hardware reliability in the ASHRAE severity level G3 environment is also described.

Author(s)
Qiujiang Liu,Tianyu Zhou,Zihua Wang,Chao Ren,Jiajun Zhang,Yongzhan He,Guofeng Chen,Pinyin Zhu,Yongzhong Zhu,Chao Liu,Prabjit Singh
Resource Type
Technical Paper
Event
IPC APEX EXPO 2015

CVS Control of a Via Fill Acid Copper Electroplating Baths

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Due to the increasing demands placed on acid copper plating solutions to perform via fill plating of blind micro vias it is critical that the plating additives be monitored precisely. This paper presents electrochemical techniques for analyzing additives commonly used in via fill plating baths. The additives,commonly referred to as suppressor,brightener and leveler,all need to be precisely monitored during the production process in order to achieve optimum via fill. Utilizing cyclic voltametric stripping (CVS),these additive types can be monitored with a single analytical instrument when the proper techniques are employed and the measurement procedures are optimized for each additive.

Author(s)
Roger Bernards,Mike Carano,Al Kucera,Thao Pham
Resource Type
Technical Paper
Event
IPC APEX EXPO 2015

Electroplated Copper Filling of Through Holes on Varying Substrate Thickness

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This paper discusses a through hole copper filling process for application to high density interconnects constructions and IC substrates. The process consists two acid copper plating cycles. The first cycle uses periodic pulse reverse electroplating to form a bridge in the middle of the hole,followed by direct current electroplating to fill the resultant vias formed during the bridge cycle. This process can provide defect-free filled holes with total plated copper on the surface below 25 µm,with dimple less than 5 µm for boards with core thickness of 0.2 mm and 0.25 mm. This process was designed to be deployed in specially constructed vertical continuous platers (VCP),thus reducing capital equipment compared to horizontal conveyorized electroplaters. The chemical components,copper,acid and additive,for periodic pulse reverse plating cycle,are optimized via experimental conditions selected from DOE (design of experiments) software. Critical parameters are identified and the impact on cavity formation during the bridging step is quantified. The additive and copper concentrations play key roles in reducing defects during bridge formation and on the resultant via formation. A high performance via-filling process is used to fill the formed vias,with less than 5 micron dimple depth,while depositing approximately 12 microns on the surface. The thin surface copper enables fine line resolution without the need for planarization or grinding. The mechanical properties of the plated deposit meet or exceed all IPC standards. This process is applicable to both laser-drilled X shape through holes and mechanically drilled straight holes. Laser-drilled through holes are bridged faster than mechanically drilled holes. However,mechanically drilled holes show a lower tendency for drilling induced defects,especially at the smaller hole diameters of 0.1mm. This process has shown capability to fill through-holes in thicker cores of 0.4 mm to 0.8 mm,where further investigation continues.

Author(s)
Kesheng Feng,Bill DeCesare,Mike Yu,Don DeSalvo,Jim Watkowski
Resource Type
Technical Paper
Event
IPC APEX EXPO 2015

Assembly Cleanliness and Whisker Formation

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This paper describes the results of a whisker formation study on SAC305 assemblies,evaluating the effects of cleanliness and lead-frame materials in room temperature/high humidity (25°C/85%RH). Cleaned and contaminated small outline transistors were soldered to custom designed test boards using Sn3Ag0.5Cu (SAC305) solder. Before assembly components were divided into two groups. The first group was cleaned using the method developed in this study. The level of contamination was 10 times below typical acceptable industry level and did not exceed 0.062 µg/cm2 (0.4 µg/in2) Cl. The second group was contaminated with NaCl. The piece part level of chlorine contamination 0.465 µg/cm2 (3 µg/in2) was selected to be within the industry levels encountered (no standards exist). After assembly,all the boards were cleaned,and half of them were re-contaminated to a level of at least 1.56 µg/cm2 Cl (10.1 µg/in2). Whisker length,diameter,and density were measured. Detailed metallurgical analysis on components before assembly and on solder joints before and after testing was performed. It was found that whiskers grow from solder joint fillets,where the thickness is less than 25 µm. The influence of lead-frame material,cleanliness,and environment on whisker characteristics is discussed. Assembly contamination is an important consideration for whisker growth in harsh service environments.

Author(s)
Polina Snugovski,Eva Kosiba,Stephan Meschter,Zohreh Bageri,Jeffrey Kennedy
Resource Type
Technical Paper
Event
IPC APEX EXPO 2015