The electronics industry is experiencing a renaissance in semiconductor package technology. A growing number of innovative 3D package assembly methodologies have evolved to enable the electronics industry to maximize their products functionality. By integrating multiple die elements within a single package outline,product boards can be made significantly smaller than their forerunners and the shorter interconnect resulting from this effort has contributed to improving both electrical performance and functional capability. Multiple die packaging commonly utilizes some form of substrate interposer as a base. Assembly of semiconductor die onto a substrate is essentially the same as those used for standard I/C packaging in lead frames; however,substrate based IC packaging for 3D applications can adopt a wider range of materials and there are several alternative processes that may be used in their assembly. Companies that have already implemented some form of 3D package technology have found success in both stacked die and stacked package technology but these package methodologies cannot always meet the complexities of the newer generation of large-scale multiple function processors. A number of new semiconductor families are emerging that demand greater interconnect densities than possible with traditional organic substrate fabrication technology. Two alternative base materials have already evolved as more suitable for both current and future,very high-density package interposer applications; silicon and glass. Both materials,however,require adopting unique via formation and metallization methodologies. While the infrastructure for supplying the glass-based interposer is currently in development by a number of organizations,the silicon-based interposer supply infrastructure is already well established. This paper outlines both positive and negative aspects of current 3D package innovations and addresses the challenges facing adopters of silicon and glass based interposer fabrication. The material presented will also reference 3D packaging standards and recognize innovative technologies from a number of industry sources,roadmaps and market forecasts.

Traceability has grown from being a specialized need for certain safety critical segments of the industry,to now being a recognized value-add tool for the industry as a whole. The perception of traceability data collection however persists as being a burden that may provide value only when the most rare and disastrous of events take place. Disparate standards have evolved in the industry,mainly dictated by large OEM companies in the market create confusion,as a multitude of requirements and definitions proliferate. The intent of the IPC-1782 project is to bring the whole principle and perception of traceability up to date. Traceability,as defined in this standard will represent the most effective quality tool available,becoming an intrinsic part of best practice operations,with the encouragement of automated data collection from existing manufacturing systems,integrating quality,reliability,predictive (routine,preventative,and corrective) maintenance,throughput,manufacturing,engineering and supply-chain data,reducing cost of ownership as well as ensuring timeliness and accuracy all the way from a finished product back through to the initial materials and granular attributes about the processes along the way. Having the proper level of traceability will also help ensure counterfeit components do not end up in a product. Through effective policing in the use of any and all components,any material found to be counterfeit will be immediately traceable to source,and hence responsibility is assigned. IPC 1782 will work hand in glove with the U.S. Department of Defense’s current counterfeit component effort. The goal of this project is to create a single flexible data structure that can be adopted for all levels of traceability that are required across the industry. The scope includes support for the most demanding instances for detail and integrity such as those required by critical safety systems,all the way through to situations where only basic traceability,such as for simple consumer products. A key driver for the adoption of the standard is the ability to find a relevant and achievable level of traceability that exactly meets the requirement following risk assessment of the business. The wealth of data accessible from traceability for analysis can yield information that can raise expectations of very significant quality and performance improvements,as well as providing the necessary protection against the costs of issues in the market. Taking a graduated approach will enable this standard to succeed where other efforts have failed.

With technology these days,we often find solutions without a problem,rather than the other way around. The concept of the “Internet of Manufacturing” (IoM),combined with the evolution toward automated and computerized factories,is an exciting subject for engineers. However,managers who are responsible for the business side of manufacturing,need a solid business case for change that is driven either by need from the customer or by a compelling internal performance enhancement. The decision to purchase new equipment today is a catch-22 — with requirements to be “future-proof” just in case the factory will become a computerized operation as put forward by the proponents of Industry 4.0,but without really knowing the full implication of what that might be. Let us take a look at these two potential business cases. First,we will look at the likely reasons that would compel customers to change their demands and requirements from factories,whether OEM or EMS. Second,we will look at what is the “state of the art” today for automated factories that have a controlling layer of computerization,understand the challenges and potential costs,as well as direct operational benefits. We will see if we can find the balance point between the two. Lastly,we will look forward at what needs to be done to provide a practical and economical way to address the various challenges to implementing an Internet of Manufacturing,with solutions and benefits for both manufacturers and customers. If these areas are addressed,the adoption of computerization and the creation of more automated factories could then become mainstream.

The highly-automated and connection-driven methods in Electronics Manufacturing is a more and more important topic in the industry today. Advances in modern manufacturing technologies make factories smarter,safer and more environmentally sustainable. Get Manufacturing Functions connected with Real Time Information Systems to enable a predictive approach in all functions to serve Higher Reliability and HMLV (high-mix low-volume) services solutions. In this paper,we will share our experience with a current project called “Smart Factory”,especially for Phase I of the project. Our objective is that Get Manufacturing Functions connected with real time information systems enable predictive approaches in all functions to serve Higher Reliability and High-Mix Low-Volume (HMLV) services solutions. Through establishment of a KOI (Key Operation Indicator) structure with visualization eDashboard,we have realized the alarming abnormalities in real time and failure analysis mining from top symptoms to bottom root cause with processes correlation. Collecting the parameters of machine and process data in real time automatically makes the connection between machines and processes to get higher efficiency for quality and production monitoring and control. Color coding for different level abnormalities gives visualization control. The real time data captured from machines and process is loaded into a central factory SPC (Statistical Process Control) system that makes predictions for taking action before failures. Real time data was sent to mobile phones to improve communication between operators and machines which has increased production efficiency. We have seen significant achievements for the Phase I: Average yield (Final Pass Yield) increased from 99.1%to 99.44%,NDF (No Defect Found) decreased from 2% to 0.9%,and also have SPC to be more predictive. Prevention is always better than detection [2].

While flex and rigid flex (IPC-6013 Types 1 through 4i[1]) have always been important in 3D packaging to help resolve space constraints and meet other design requirements,the continued push for denser packaging and higher performance has only increased the demand for more complex interconnects. Often we forget that a flex is more than a mechanical solution but that it is a critical part in controlling signal integrity and meeting other electrical performance requirements. Any design must be manufacturable,reliable and meet cost constraints. We will be examining a packaging solution for a server application that met all requirements thru a combination of key design points including:
-Rigid Flex (IPC-6013 type 4)
-15 layer cross section-Unbonded/loose leaf construction
-Bookbinder construction
-Backdrill
-LGA (Land Grid Array) interconnect
Cost,manufacturability,reliability,signal integrity,thermal and mechanical requirements were all considered during development. The collaborative efforts of mechanical development,signal integrity modeling and input,qualification engineering,production engineering,cost engineering,sourcing team support and manufacturability and cost feedback from the fabricator were key to creating a final design that was an optimum balance considering various trade-offs. More than a simple stack of circuit materials,the unbonded/looseleaf,bookbinder cross section and LGA interconnect was able to meet the tight rigid flex mechanical bend radius requirements and the small interconnect footprint requirements. The flexibility of the rigid flex met the system mechanical requirements related to tolerances between the two mating LGA interconnect areas. Critical signal integrity requirements were met thru the selected cross section,backdrill and the utilizing an LGA interconnect solution. This paper includes details as to how we went from concept to initial development,to design iterations and prototyping,thru qualification into a final product in volume production. While this product may look very much like a technology test vehicle,it successfully and elegantly solved a real world challenge.

With the rapid development of the information industry,increasing attention is being paid to the dielectric performance of base materials including copper-clad laminates (CCL) and prepregs. In addition to the increasingly high performance requirements of CCL’s,the present global attention to less toxic products is leading to an increase in the use of halogen-free flame retardants in electronics. The main flame retardants used in halogen-free CCL’s are phosphorus-containing phenolic resins,phosphonitriles,phosphorus containing epoxy resins,and several additive type compounds. Flame retardant additives like phosphates have low or no reactivity with epoxy resins,which typically results in lower glass transition temperature (Tg),higher moisture absorption,reduced dielectric performance and lower heat resistance. This paper introduces a new phosphonate oligomer which can be used as a reactive flame retardant in epoxy based resin systems. Suitable conditions for the complete reaction between the phosphonate oligomer and epoxy resin are described and the resulting halogen-free laminates with improved properties such as low Df,low coefficient of thermal expansion (CTE),high peel strength,and good toughness are presented. The significance of this paper is not only to introduce a new halogen-free,mid-Tg,low loss CCL,but also to highlight a novel kind of halogen free reactive flame retardant for CCL. Comparison performance data to other commercial halogen-free base materials will be presented.

The miniaturization trend is driving industry to adopting low standoff components or components in cavity. The cost reduction pressure is pushing telecommunication industry to combine assembly of components and electromagnetic shield in one single reflow process. As a result,the flux outgassing/drying is getting very difficult for devices due to poor venting channel. This resulted in insufficiently dried/burnt-off flux residue. For a properly formulated flux,the remaining flux activity posed no issue in a dried flux residue for no-clean process. However,when venting channel is blocked,not only solvents remain,but also activators could not be burnt off. The presence of solvents allows mobility of active ingredients and the associated corrosion,thus poses a major threat to the reliability. In this work,a new halogen-free no-clean SnAgCu solder paste,Paste F,has been developed. This solder paste exhibited SIR value above the IPC spec 100 MO without any dendrite formation,even with a wet flux residue on the comb pattern. The wet flux residue was caused by covering the comb pattern with 10 mm × 10 mm glass slide during reflow and SIR testing in order to mimic the poorly vented low standoff components. The Paste F also showed very good SMT assembly performance,including voiding of QFN and HIP resistance. The wetting ability of Paste F was very good under nitrogen. For air reflow,Paste F wetted well on all surface finishes,and is better than paste C which is widely accepted by industry for air reflow process. The above good performance on both non-corrosivity with wet flux residue and robust SMT process can only be accomplished through a breakthrough in flux technology.

Controlled humidity and temperature controlled surface insulation resistance (SIR) measurements of flux covered test vehicles,subject to a direct current (D.C.) bias voltage are recognized by a number of global standards organizations as the preferred method to determine if no clean solder paste and wave soldering flux residues are suitable for reliable electronic assemblies. The Association Connecting Electronics Industries (IPC),Japanese Industry Standard (JIS),Deutsches Institut fur Normung (DIN) and International Electrical Commission (IEC) all have industry reviewed standards using similar variations of this measurement. Ionic contamination testing is recognized by the IPC as a standard for evaluating the cleanliness of assemblies that have subjected to a cleaning process. IPC J-STD001F standard calls for a cleanliness level of < 1.56 µg/cm² NaCl equivalent after the cleaning processes. Historically,this threshold originated from the cleanliness specifications of military and aerospace original equipment manufacturers (OEMs). These applications used rosin-based wave soldering fluxes,such as RMAs,and cleaned with now presently banned fluorocarbon solvents. Many of these applications have subsequently implemented water soluble soldering processes. Several automotive and consumer electronic OEMs still use this standard,to qualifying assemblies built with no-clean materials using mixed SMT and PTH assembly technologies. IPC-TM-650 Method 2.3.25 contains standard test methods for extracting contaminants from circuit boards using heated isopropanol (IPA) / water mixtures. Test method 2.3.25 is commonly referred to as the ROSE (Resistivity of Solvent Extract) test. Previous work [1,2] has shown poor correlation between the presence of extractable,corrosive weak organic acids and results from IPC-TM-650 2.3.25 test results,partially due to the lack of solubility of materials found in no-clean fluxes,and the higher SIR values imparted by rosins and resins in modern no-clean soldering materials. This study will compare the results from testing two solder pastes using the IPC-J-STD-004B,IPC TM-650 2.6.3.7 surface insulation resistance test,and IPC TM-650 2.3.25 in an attempt to investigate the correlation of ROSE methods as predictors of electronic assembly electrical reliability.

The selection of a liquid flux for use in wave soldering operations is extremely critical to both the manufacturing assembly process and the long term reliability of electronic assemblies. As in the case of VOC-free fluxes,suppliers have developed products that minimize their impact on the environment and meet IPC-JSTD004 Revision A requirements. Just over 4 years ago Revision B was released[1]with significant changes to the Surface Insulation Resistance testing including thermal profile,humidity targets,bias voltages,and measuring frequency requirements. These changes along with tighter halide limits have significantly restricted the VOC-free flux offerings,due to concerns of reliability test failures. Though harsh environments may have seen improvements in the field of reliability,correlation to field failure rate improvements has not been seen on typical environments since the option of Revision B release. Smaller flux formulators are not always aware of the changes nor have re-classified their products. Testing has uncovered numerous VOC-Free products,which do not meet stated specifications. Even for fluxes claiming to pass the current standard,the lack of adequate method detail on how to execute the test and reporting of parameters used,introduces variation in results and interpretational errors. In order to meet the IPC J-STD-004 standard Revision B requirements and design materials that can meet the thermal challenges of today’s products,most liquid flux formulators increased or re-introduced rosin in the formulations. As a result,moving back to the use of alcohol fluxes is the primary option. This transition back to VOC containing materials conflicts with the majority of the environmental initiatives within manufacturing. This paper details the challenges to be encountered by comparing results provided by flux manufacturers to that obtained in-house during verification testing. Comparison will also be made between laboratory testing and production results. Gaps and opportunities will be presented in the industry’s current approach to flux development and selection.

In this rapidly moving electronics market,fast to market with new products is what separates top performing companies from average companies. A survey conducted by Arthur D. Little (ADL) [1] revealed that “New-Product Development (NPD) productivity in atop performing company is five times what it is in the average company. The top performer gets five times as much new product output for the same investment.” What do they know that the rest of us do not? One winning factor is the use of the Robert Cooper process [2]. Since its introduction in the early 1980’s,it has gone through many modifications to make it more lean and effective for today’s business climate. Many larger organizations already practice this method. However,for small to medium size organizations,a dedicated New Product Development (NPD) process may appear to be a daunting task. This is due to the perception of the complexity of the Stage Gate process. This paper will present a Lean Six Sigma approach to “right sizing” the Stage Gate process to be efficient,practical,and easy to manage. Various tools of Stage Gate,along with proven best practice,will be covered. In addition,a reduced Stage Gate model will be discussed for simple,low risk projects.