This paper will discuss the expanded use of boundary-scan testing beyond the typical manufacturing test to capture structural defects on a component/devices in a printed circuit board assembly (PCBA). The following topics will be discussed to demonstrate the capability of boundary-scantest system on how we can extend beyond typical manufacturing test:
1.Boundary-scanas a complete manufacturing test system –A boundary-scantest system should be able to cover all the needs of a manufacturing test to be an effective solution.
2.Boundary-scanimplementation during PCBA design stage –This topic will discuss the importance of design for test (DFT) at the early stage of PCBA design to maximize the use of boundary-scan to lower the cost of test while increasing the test coverage.
3.Implementation of boundary-scan beyond typical structural testing –While capturing structural defects are important during manufacturing test,the need for boundary-scan to include other areas beyond PCBA structural testing is now necessary.

Manufacturers test to ensure that the product is built correctly. Shorts,opens,wrong or incorrectly inserted components,even catastrophically faulty components need to be flagged,found and repaired. When all such faults are removed,however,functional faults may still exist at normal operating speed,or even at lower speeds. Functional board test (FBT) is still required,a process that still relies on test engineers’ understanding of circuit functionality and manually developed test procedures. While functional automatic test equipment (ATE) has been reduced considerably in price,FBT test costs have not been arrested. In fact,FBT is a huge undertaking that can take several weeks or months of test engineering development,unacceptably stretching time to market. The alternative,of selling products that have not undergone comprehensive FBT is equally,if not more,intolerable. Design for Testability (DFT) techniques are effective ways to reduce FBT test programming complexity. This is accomplished by improving Observability and Controllability attributes. This often implies adding test points,but access improvements can be gained from many design activities. These include JTAG/IEEE-1149.1 boundary scan access wherever they happen to be present. We examine some failure modes and show that many of them need to be tested with FBT. Still others require DFT to enable FBT to detect them. We suggest a more pro-active approach that purposely places boundary scan access to internal circuit locations necessary or instrumental for better tests. This approach requires test and design collaboration during the design process. Designers must understand the test requirements early enough to add the necessary access points so that path sensitization and diagnostic attributes are also improved. When complex measurements are needed to ensure functionality,increased cost of both test equipment price and lack of availability may be limiting factors. Designs can usually accommodate existing ATEs and test set ups,provided this is done during the design process. We propose a parallel design and test engineering activity. We argue that while the potential benefits are great,the added costs are insignificantly small.

To answer the high functionality expected of mobile device terminals,such as smartphones and wearable devices,panels need to be created even smaller while increasing the quantity of parts and maintaining a large-capacity battery space. To be able to meet these needs,the miniaturization of passive parts such as capacitors,resistors,and inductors is progressing rapidly. Each of these parts have a singular function and are simple in design,but they are also parts which are indispensable in mobile devices which use high frequency power. Capacitors and inductors are particularly important for IC peripherals used for configuring communication modules,and thus the miniaturization of parts is even more important for the goal of making modules smaller overall. One major feature of using 0201 parts is the reduction of the placement area. The below shows the shrinking of the space between placed parts. 0402 (01005”) parts with a space between each part of 0.17 mm in the X direction and 0.13 mm in the Y direction. And in comparison,0201(008004”) parts with a space of 0.13 mm in the X direction and 0.09 mm in the Y direction. The placement area is reduced from 10.30 mm2down to4.61 mm2. This means a reduction of 55% in the placement area. Based on these results,it is reasonable to presume that establishing a placing process for 0201(008004”) parts will contribute to the miniaturization and higher functionality of electronic devices.

The art of screen printing solder paste for the surface mount community has been discussed and presented for several decades. However,the impending introduction of passive Metric 0201 devices has reopened the need to re-evaluate the printing process and the influence of stencil architecture. The impact of introducing apertures with architectural dimensions’ sub 150um whilst accommodating the requirements of the standard suite of surface mount connectors,passives and integrated circuits will require a greater knowledge of the solder paste printing process. The dilemma of including the next generation of surface mount devices into this new heterogeneous environment will create area ratio challenges that fall below todays 0.5 threshold. Within this paper the issues of printing challenging area ratio and their associated aspect ratio will be investigated. The findings will be considered against the next generation of surface mount devices.

Reduction of first pass defects in the SMT assembly process minimizes cost,assembly time and improves reliability. These three areas,cost,delivery and reliability determine manufacturing yields and are key in maintaining a successful and profitable assembly process. Itis commonly accepted that the solder paste printing process causes the highest percentage of yield challenges in the SMT assembly process. As form factor continues to get smaller,the challenge to obtain 100% yield becomes more difficult. This paper will identify defects affecting SMT yields in the printing process and discuss their Root Cause. Outer layer copper weight and surface treatment will also be addressed as to their effect on printability. Experiments using leadless and emerging components will be studied and root cause analysis will be presented on the following common SMT defects:
•Poor Solder Paste Release: Focus will be placed on small components
•Solder-balls (Mid Chip Solder Beads): Stencil design to minimize solder balls
•Tombstoning: Improving tombstoning with stencil design
•Bridging at Print: Simple guidelines to eliminate bridging
•Bridging at SMT Reflow: What causes bridging after reflow when it is not present after print
•Insufficient Solder Volume at SMT Reflow: Look at the correlation of stencil design to solder volume after reflow
•Voiding: Design ideas to reduce voiding through stencil design
Root causes of these challenges will be identified and practical stencil design recommendations will be made with the intent of eliminating defects and improving yields during the printing process.

For a demanding automotive electronics assembly,a highly thermal fatigue resistant solder alloy is required,which makes the lead-free Sn-Ag-Cu type solder alloy unusable. Sn-Ag-Bi-In solder alloy is considered as a high reliability solder alloy due to significant improvement in thermal fatigue resistance as compared to a standard Sn-Ag-Cu alloy. The alloy has not only good thermal fatigue properties but it also has superior ductility and tensile strength by appropriate addition of In; however,initial results indicated a sub-par performance in joint reliability when it is soldered on a printed circuit board (PCB) with Electroless Nickel Immersion Gold (ENIG) surface finish. Numerous experiments were performed to find out appropriate alloying element which would help improve the performance on ENIG PCBs. Sn-Ag-Bi-In solder alloys with and without Cu additions were prepared and then tests were carried out to see the performance in a thermal fatigue test and a drop resistance test.to investigate the impact of Cu addition towards the improvement of joint reliability on ENIG finish PCB. Also,the mechanism of such improvement is documented.

Driven by miniaturization,cost reduction and tighter requirements for electrical and thermal performance,the use of lead-frame based bottom-termination components (LF-BTC) as small-outline no-leads (SON),quad-flat no leads (QFN) packages etc.,is increasing. However,a major distractor for the use of such packages in high-reliability applications has been the lack of a visible solder (toe) fillet on the edge surface of the pins: because the post-package assembly singulation process typically leaves bare copper lead frame at the singulation edge,which is not protected against oxidation and thus does not easily solder-wet,a solder fillet (toe fillet) does not generally develop. Solder-joint robustness is also increased by the presence of a robustly wettable singulation edge,but this is not the primary benefit (the number of cycles to failure under thermal cycling is typically decreased by up to about 25% in the absence of an outer,visible fillet). Users,primarily those involved in the mass production of high-reliability mission-critical (e.g. automotive) applications,have insisted that a solder fillet be visible at the outer edge of each contact to enable a robust inspection for wetting failures by automatic optical inspection (AOI). The possibility to inspect the integrity of the solder joints by AOI avoids the need to employ X-ray inspection methods,which involve additional costs and layout restrictions,as certain keep-out zones for traces and components are necessary for avoiding disturbing effects in the solder joints X-ray images. Package suppliers have responded to these needs with various pin modifications that enable a portion of the terminal-edge surface to remain plated after singulation,as two-step sawing or dedicated etching processes. However,for such pin modifications to be useful in the context of AOI under series production conditions,the pin modifications must meet certain geometrical requirements,in order to robustly distinguish a wetted pin (‘good solder joint) from a non-wetted pin (‘defective solder joint’) in AOI. These geometrical requirements will be investigated in this work considering also typical assembly-related process variations. The geometrical requirements enabling robust AOI of LF-BTCs in mass production will be derived.

The miniaturization trend is driving industry to adopting low standoff components. The cost reduction pressure is pushing telecommunication industry to combine assembly of components and electromagnetic shield in one single reflow process. As a result,the flux outgassing is getting very difficult for devices. This resulted in more large voids. For a properly formulated flux,there is less outgassing at temperature above melting temperature of solder or the flux can be expelled out from interior of solder joints due to good wetting ability. Either approach will reduce the voids. In this work,a new halogen-free no-clean flux chemistry,F,has been developed. The solder paste using 96.5Sn3.0Ag0.5Cu and Alloy A exhibited ultra-low voiding and virtually zero solder beading performance. The low voiding performance on Alloy A solder paste is particularly crucial since the automotive industry has been ailing by the poor voiding performance of this 6-element solder alloy system. The halogen-free F virtually enables the automotive to migrate toward full adoption of high reliability 6-element alloy system. Furthermore,the hot slump,wetting,solder balling,and graping performance are all acceptable. The printing performance of F showed excellent transfer efficiency under various printer setup and pad design conditions,indicating this flux system is a very robust system for SMT fine-pitch applications.

Creep corrosion on printed circuit boards (PCBs) is the corrosion of copper metallization and the spreading of the copper corrosion products across the PCB surfaces to the extent that they may electrically short circuit neighboring features on the PCB. The iNEMI technical subcommittee on creep corrosion has developed a flowers-of-sulfur (FOS) based test that is sufficiently well developed for consideration as an industry standard qualification test for creep corrosion. This paper will address the important question of how relative humidity affects creep corrosion. A creep corrosion tendency that is inversely proportional to relative humidity may allow data center administrators to eliminate creep corrosion simply by controlling the relative humidity in the data center,thus,avoiding the high cost of gas-phase filtration of gaseous contamination. The creep corrosion relative humidity dependence will be studied using a modified version of the iNEMI FOS test chamber. The design modification allows the achievement of relative humidity as low as 15% in the presence of the chlorine-releasing bleach aqueous solution. The paper will report on the dependence of creep corrosion on humidity in the 15 to 80% relative humidity range by testing ENIG (gold on electroless nickel),ImAg (immersion silver) and OSP (organic surface preservative) finished PCBs,soldered with organic acid flux.

Reliability Expectations of Highly Dense Electronic Assemblies is commonly validated using Ion Chromatography and Surface Insulation Resistance. Surface Insulation Resistance tests resistance drops on both cleaned and non-cleaned circuit assemblies. It is well documented in the literature that SIR detects ionic residue and the potential of this residue to cause leakage currents in the presence of humidity and bias. Residues under leadless components are hard to inspect for and to ensure flux residue is totally removed. The question many assemblers consider is the risk of residues that may still be present under the body of components. A recent research study10 of both flux activator systems and cleaning under bottom terminated components found that different no-clean flux packages have chemical properties that induce failure at different rates. The study also found that residues that were not fully cleaned under leadless components could be a reliability risk. Electrochemical methods (EIS) provide insight into the corrosion potential of a residue,in this case,flux residue. Electrochemical methods have not been commonly used for assessing corrosion potential on electronic devices. The purpose of this research study is to run Electrochemical Methods on the four flux systems used in the SIR study to determine if EIS data findings have commonality on the SIR data findings.