It is well known that structures at fine pitches with flux residues are more susceptible to corrosion issues and electrochemical migration (ECM) problems. Characterization of flux residues in terms of ECM are commonly characterized using SIR testing. A key parameter of the SIR test is the comb pattern used and gap between the electrodes. The current B24 and B25 with their 500 and 318µm gap patterns are not representative of fine pitch. It has been proposed to use a 200µm gap pattern,and this paper describes an intercomparison that validates the introduction of the 200µm gap pattern. A new test board was used that included the B24 and B25 patterns with an additional 200µm pattern,with each pattern duplicated,giving six in all. This work was motivated by an update to the current IEC 61189-5-501[1]. A protocol for the testing was developed that took a standard test rosin flux and defined the flux loading and thermal conditioning. Seven laboratories took part from five countries. The test boards were prepared centrally and then tested in the seven laboratories,and the results analyzed to validate the usage of the 200µm pattern. The paper describes the intercomparison and the data analysis.

No-clean solder pastes are widely used in a number of applications that are exposed to wide variations in temperature during the life of the assembled electronics device. Some have observed that cracks can and do form in flux residue and have postulated that this is the result of or exacerbated by temperature cycling. Furthermore,the potential exists for the flux residue to soften or liquefy at elevated temperatures,and even flow if orientated parallel to gravity. In situations,such as in automotive electronics,where significant temperature cycling is a reality and high reliability is a must,concern sometimes exists that the cracking and possible softening or liquefying of the residue may have a deleterious effect on the electrical reliability of the flux residue. This paper will attempt to address this concern. For this work,two commercially availableSAC305Type 4no-clean solder pastes,one halogen-free (ROL0) and the other halogen-containing (ROL1),will be examined. In accordance with IPC J-STD-004B,these solder pastes will be printed and reflowed,using the same common air reflow profile,on to IPC-B-24 SIR test boards. After reflow,each solder paste will have boards set aside for constant room temperature exposure,-40°C to +125°C temperature cycling and -55°C to +175°C temperature cycling. For the two temperature cycling scenarios,boards will be orientated both perpendicular and parallel to gravity in the temperature cycling chamber. Upon completion of the temperature cycling,the boards will be submitted to Surface Insulation Resistance (SIR) testing per IPC-TM-650 2.6.3.7. The SIR readings will be plotted for each scenario and compared.

Smartphones and tablets require very high flexible and sever bending performance to the Flexible Printed Circuits (FPCs) to fit into their thinner and smaller body designs. In these FPCs the extraordinary highly flexible treated rolled annealed (RA) copper foils are recently used instead of regular RA foil and electro deposited (ED) foils. It is very important to measure the Young’s moduli of these foils predicting the mechanical properties of FPCs such as capabilities of fatigue endurance,folding and so on. Even though the manufacturers use IPC TM-650 2.4.18.3 test method for measuring Young’s modulus of copper foils over many years,where Young’s modulus is calculated from stress-strain curve,it is quite difficult to obtain the accurate Young’s modulus of metal foils by this test method. The S-S curves of copper foils always exhibit a large degree of scattering. In order to cope with the issue,‘Resonance method’ using the resonance frequency of a specimen is proposed to measure the much accurate Young’s modulus. The comparison is made between IPC TM-650 2.4.18.3 and the resonance method in view of calculation of Young’s modulus,accuracy. It is found that Young’s modulus values measured by the resonance method were close to theoretical values than those measured by the conventional method. In addition,the experimental data of fatigue life are utilized to support the accuracy of Young’s modulus values measured by the resonance method.

As a result of the continuous industrial trend towards high density packaging there is a growing demand for highly thermally-stable laminate materials. Although the epoxy resin defines the thermal stability,often the flame retardant used becomes the limiting factor in achieving a higher stability. Recognizing this industrial need,the company has developed a new flame-retardant curing agent,Material A. This is a phosphorus-based polymer which cures epoxy via a very specific mechanism. Common Novolac epoxy resins cured with Material A and a phenol-formaldehyde resin show a Tg>180°C and Td >400°C. In addition to a high thermal stability,Material A also shows a dielectric loss factor lower than commercial phosphorus-based flame retardants.

With complexities of PCB design scaling and manufacturing processes adopting to environmentally friendly practices raise challenges in ensuring structural quality of PCBs. This makes it essential to have a good ‘Design for Test’ (DFT) to ensure a robust structural test. A good structural test implementation starts right at the design of an ASIC wherein,the system application and,the ASIC design itself should be kept in mind for implementing the features to enable testability. Answers to the below four questions are the essence of the first part of this paper.
•What are the aspects to be considered for enhancing ‘DFT’?
•How effectively can the ‘DFT’ be reviewed?
•Is there an intelligent and automated way of doing this?
•At which phase of Product Life Cycle should the DFT review be done,to obtain best value for structural test?
During the course of the DFT review,can we realize a good test strategy for the PCBA? How can the test strategy of the PCBA be partitioned as to what portions of the design can be covered structurally and what is covered functionally,in a way that provides best diagnostics to discover faults? Answers to the above two questions will be addressed in the second part of this paper.

This paper will discuss the expanded use of boundary-scan testing beyond the typical manufacturing test to capture structural defects on a component/devices in a printed circuit board assembly (PCBA). The following topics will be discussed to demonstrate the capability of boundary-scantest system on how we can extend beyond typical manufacturing test:
1.Boundary-scanas a complete manufacturing test system –A boundary-scantest system should be able to cover all the needs of a manufacturing test to be an effective solution.
2.Boundary-scanimplementation during PCBA design stage –This topic will discuss the importance of design for test (DFT) at the early stage of PCBA design to maximize the use of boundary-scan to lower the cost of test while increasing the test coverage.
3.Implementation of boundary-scan beyond typical structural testing –While capturing structural defects are important during manufacturing test,the need for boundary-scan to include other areas beyond PCBA structural testing is now necessary.

Manufacturers test to ensure that the product is built correctly. Shorts,opens,wrong or incorrectly inserted components,even catastrophically faulty components need to be flagged,found and repaired. When all such faults are removed,however,functional faults may still exist at normal operating speed,or even at lower speeds. Functional board test (FBT) is still required,a process that still relies on test engineers’ understanding of circuit functionality and manually developed test procedures. While functional automatic test equipment (ATE) has been reduced considerably in price,FBT test costs have not been arrested. In fact,FBT is a huge undertaking that can take several weeks or months of test engineering development,unacceptably stretching time to market. The alternative,of selling products that have not undergone comprehensive FBT is equally,if not more,intolerable. Design for Testability (DFT) techniques are effective ways to reduce FBT test programming complexity. This is accomplished by improving Observability and Controllability attributes. This often implies adding test points,but access improvements can be gained from many design activities. These include JTAG/IEEE-1149.1 boundary scan access wherever they happen to be present. We examine some failure modes and show that many of them need to be tested with FBT. Still others require DFT to enable FBT to detect them. We suggest a more pro-active approach that purposely places boundary scan access to internal circuit locations necessary or instrumental for better tests. This approach requires test and design collaboration during the design process. Designers must understand the test requirements early enough to add the necessary access points so that path sensitization and diagnostic attributes are also improved. When complex measurements are needed to ensure functionality,increased cost of both test equipment price and lack of availability may be limiting factors. Designs can usually accommodate existing ATEs and test set ups,provided this is done during the design process. We propose a parallel design and test engineering activity. We argue that while the potential benefits are great,the added costs are insignificantly small.

To answer the high functionality expected of mobile device terminals,such as smartphones and wearable devices,panels need to be created even smaller while increasing the quantity of parts and maintaining a large-capacity battery space. To be able to meet these needs,the miniaturization of passive parts such as capacitors,resistors,and inductors is progressing rapidly. Each of these parts have a singular function and are simple in design,but they are also parts which are indispensable in mobile devices which use high frequency power. Capacitors and inductors are particularly important for IC peripherals used for configuring communication modules,and thus the miniaturization of parts is even more important for the goal of making modules smaller overall. One major feature of using 0201 parts is the reduction of the placement area. The below shows the shrinking of the space between placed parts. 0402 (01005”) parts with a space between each part of 0.17 mm in the X direction and 0.13 mm in the Y direction. And in comparison,0201(008004”) parts with a space of 0.13 mm in the X direction and 0.09 mm in the Y direction. The placement area is reduced from 10.30 mm2down to4.61 mm2. This means a reduction of 55% in the placement area. Based on these results,it is reasonable to presume that establishing a placing process for 0201(008004”) parts will contribute to the miniaturization and higher functionality of electronic devices.

The art of screen printing solder paste for the surface mount community has been discussed and presented for several decades. However,the impending introduction of passive Metric 0201 devices has reopened the need to re-evaluate the printing process and the influence of stencil architecture. The impact of introducing apertures with architectural dimensions’ sub 150um whilst accommodating the requirements of the standard suite of surface mount connectors,passives and integrated circuits will require a greater knowledge of the solder paste printing process. The dilemma of including the next generation of surface mount devices into this new heterogeneous environment will create area ratio challenges that fall below todays 0.5 threshold. Within this paper the issues of printing challenging area ratio and their associated aspect ratio will be investigated. The findings will be considered against the next generation of surface mount devices.

Reduction of first pass defects in the SMT assembly process minimizes cost,assembly time and improves reliability. These three areas,cost,delivery and reliability determine manufacturing yields and are key in maintaining a successful and profitable assembly process. Itis commonly accepted that the solder paste printing process causes the highest percentage of yield challenges in the SMT assembly process. As form factor continues to get smaller,the challenge to obtain 100% yield becomes more difficult. This paper will identify defects affecting SMT yields in the printing process and discuss their Root Cause. Outer layer copper weight and surface treatment will also be addressed as to their effect on printability. Experiments using leadless and emerging components will be studied and root cause analysis will be presented on the following common SMT defects:
•Poor Solder Paste Release: Focus will be placed on small components
•Solder-balls (Mid Chip Solder Beads): Stencil design to minimize solder balls
•Tombstoning: Improving tombstoning with stencil design
•Bridging at Print: Simple guidelines to eliminate bridging
•Bridging at SMT Reflow: What causes bridging after reflow when it is not present after print
•Insufficient Solder Volume at SMT Reflow: Look at the correlation of stencil design to solder volume after reflow
•Voiding: Design ideas to reduce voiding through stencil design
Root causes of these challenges will be identified and practical stencil design recommendations will be made with the intent of eliminating defects and improving yields during the printing process.