The electronics industry trend continues to be to continually increase capability and performance within an existing or smaller footprint. Shoehorning all of the required components onto the exterior surface of the PCB has become an increasingly difficult puzzle. The use of stacked microvias instead of plated through holes and stacked ICs in various configurations has freed up some real estate. The use of ever smaller passive devices also saves space,but reintroduces old issues such as tombstoning. The ideal solution would be to provide ‘surface’ real estate within the architecture of the circuit board –like moving items from a desk to a bookshelf –by embedding components into the board. Leveraging the established buried TLPS (Transient Liquid Phase Sintering)paste microvia technology for z-axis interconnection,“via layers” with TLPS paste inserted into lamination adhesive at the desired interconnect points to the component terminals could be used to connect to embedded components. Ideally,components could be buried at any layer to maximize topside real estate and minimize wiring lengths. The concept of using TLPS-filled via layers to make both connections to buried components and any other z-axis interconnections required on any layer will be explored. The combination of the sintering paste interconnect and an interposer element is the key to enabling this architecture. This manufacturing strategy presents a number of advantages. The board may be broken down into logical substructures such as high density,core or RF portions. Each of the sub-PCBs can be fabricated according to best manufacturing practices for that portion of the circuit board rather than trying to fabricate a single complicated board. Yield losses from sequential process steps and multiple laminations may be reduced. The component placement can facilitate point-of-source architecture for high electrical performance. The process flow and laboratory demonstrations of this technique will be presented in this paper.

More and more people and things are using electronic devices to communicate. Subsequently,many electronic products,in particular mobile base stations and core network nodes,need to handle enormous amounts of data per second. One important link in this communication chain is high speed press fit connectors that are often used to connect mother boards and back planes in core network nodes. These new high speed press fit connectors have several hundreds of thin,short and weak pins that are prone to damage. Small variations in via hole dimensions or hole plating thickness affect the connections; if the holes are too small,the pins may be bent or permanently deformed and if the holes are too large they will not form gas tight connections. The goal of this project was to understand how rework of these new high speed press fit connectors affects connection strengths,hole wall deformations and plating cracks.

There are times when a PCB prototype needs to be built quickly to test out a design. In such cases where it is known early on that there will be multiple iterations or that a “one and done” assembly will be made that there will be some SMT assemblers who choose to hand print solder paste onto the board using a “frameless” stencil. In such cases where hand printing is used,the consistency of the printing technique has typically been in question. Furthermore,the effectiveness of both the nanocoatings as well as the higher end stainless steel materials,which have been heretofore studied in controlled printing environments,will be evaluated for their impact on the hand printing process.

Rising customer demands in the field of PCB repair are a daily occurrence as the rapid electronic industry follows new trends in a blink of an eye. New strategies and technologies are required to fulfill those demands. Out of the long list of today’s customer demands for efficient BTC and SMT PCB repair some subjects show up on a daily basis and are agreed to be relevant for the coming years:
• BTC types with new effects -> voidless treatment
• Smaller components -> miniaturization (01005 capability)
• Large board handling -> dynamic preheating for large board repair
• Repeatable processes -> flux and paste application (Dip and Print),residual solder removal (scavenging),dispensing,multiple component handling,and traceability
• Operator support -> higher automation,software guidance (Human Computer Interface)
• Cost effectiveness -> Rework Systems for different budgets and ROI situations

Automating electronics assembly is complex because many devices are not manufactured on a scale that justifies the cost of setting up robotic systems,which need frequent readjustments as models change. Moreover,robots are only appropriate for a limited part of assembly because small,intricate devices are particularly difficult for them to assemble. Therefore,assembly line designers must minimize operational and readjustment costs by determining the optimal assignment of tasks and resources for workstations. Several research studies address task assignment issues,most of them dealing with robot costs as fixed amount,ignoring operational costs. In real factories,the cost of human resources is constant,whereas robot costs increase with uptime. Thus,human workload must be as large and robot workload as small as possible for the given number of humans and robots. We propose a new task assignment method that establishes a workload balancing that meet precedence and further constraints. The following must be determined before using our method: which tasks robots can perform,and which workstations robots are assigned to. We assume that humans can perform every task and consider the constraints that restrict the tasks robots can perform. By applying our method to several case studies,problems involving 20humans were solved within 1minute and 1% dispersion. These results indicate that our method can be used in actual factories where a short-term planning period corresponding to frequent production fluctuations is required. We also applied our method to real assembly data for laptops manufactured by our company and obtained task assignment that reduces the operational costs by 30%. This suggests that our method can contribute to promoting the automation of electronics assembly by demonstrating its cost reduction potential.

Choosing an outsourced manufacturing partner that is perfect for a new product and close to your design team is quite different to choosing a partner that can manufacture that same product in volume in lower cost locations and fulfil globally. This is where the Gateway model comes into its own. Most large EMS have structured their organizations to leverage proximity to OEM design teams in high cost regions while providing the benefits of low cost regions for volume manufacturing. The “Gateway” facility in higher cost regions provides design engineering,supply chain design,prototype,and NPI services. The goal of the Gateway is to develop an effective build recipe that can then be effectively and seamlessly transferred to one or more volume manufacturing facility that offers lower costs and direct fulfillment to consumers. We will present a case study that highlights the value of this model and that shows some of the key elements that allow for seamless transitions from plant to plant. The Gateway model is an essential element to a successful global manufacturing model and helps ensure that products are made in the right geography.

As the demand for higher routing density and transfer speed increases,Via-In-Pad Plated Over (VIPPO)has become more common on high-end telecommunications products. The interactions of VIPPO with other features used on a PCB such as the traditional dog-bone pad design could induce solder joints to separate during the second and thereafter reflows. The failure has been successfully reproduced,and the typical failure signature of a joint separation has been summarized [1].To better understand the solder separation mechanism,this study focuses on designing a test vehicle to address the following three perspectives: PCB material properties,specifically the Z-direction or out-of-plane Coefficient of Thermal Expansion (CTE); PCB thickness and back drill depth; and quantification of the driving force magnitude beyond which the separation is due to occur. The test vehicle is designed such that each VIPPO pad is surrounded by dog-bone via pads and each of the VIPPO joints has independent daisy chain for in-situ monitoring during the second reflow cycle. There are four different pad designs: all VIPPO design; VIPPO and dog-bone mixed pad design; VIPPO and skip via mixed pad design; and back-drilled VIPPO mixed pad design. The all VIPPO design is the baseline benchmark. The VIPPO and dog-bone mixed pad design is expected to be the worst case scenario. The VIPPO and skip via mixed pad design together with the VIPPO and back-drilled VIPPO mixed design are included to narrow the magnitude of inherent build-in stress induced by the CTE mismatch which causes the VIPPO joints to separate during the second reflow. The test vehicles are fabricated with two different PCB materials. Material A is a traditional high-end PCB material with high Z-direction (out-of-plane) CTE; while Material B has approximately one third of the Z-direction CTE of Material A.A Design of Experiment(DoE)with two PCB materials (Material A and Material B) and two PCB thicknesses(93mil and 125mil) has been performed. With the designed single-ball daisy chain test vehicle and installed thermocouples,the correlation between electrical continuity (daisy chain resistance) and solder joint temperature (thermocouple) can be derived. A video was taken of two cross-sectioned samples during the second reflow cycle using a reflow simulator. The observation is consistent with the findings of the test vehicle (TV)for in-situ monitoring. The results also provide more accurate and broader information for the investigation on why,how,and when the solder separation occurred during the second reflow cycle.

Cold ball pull testing is used to validate the resistance of PCB pad cratering for the different ultra-low loss dielectrics materials (Dk=3~4.2 and Df <= 0.005 @ 1GHz) in the study. The materials were fabricated in multiple PCB shops using a common test board design utilizing a coupon to result in a 16 mil nominal pad size for the pulls. After fabrication,a 20 mil SAC305ball is SMT attached to the 16 mil nominal pads for pulling. Each material had3 coupons with 50 pull locations on each to generate 150 data points for statistical analysis. The peak pull force differences of the material builds can be compared to differentiate the results. As a result,the different ultra-low loss dielectric material’s performance to withstand PCB pad cratering can be compared comprehensively with the cold ball pull test.

Electroless nickel electroless palladium immersion gold (ENEPIG) surface finish for printed circuit board (PCB) has now become a key surface finish that is used for both tin-lead and lead-free solder assemblies. This paper presents the reliability of land grid array (LGA) component packages with 1156 pads assembled with tin-lead solder onto PCBs with an ENEPIG finish and then subjected to thermal cycling and then isothermal aging. To determine thermal cycle reliability,daisy-chain LGA1156 packages were used to enable the monitoring of solder joint failures. The assemblies,were built with a vapor phase reflow machine or using a rework station. Then,they were subjected to thermal cycling ranging from –55°Cto 125°C. Subsequent to the completion of two hundred thermal cycles,the assemblies were isothermally aged for 324hours at 125°C to determine the effect of isothermal aging on intermetallic formation and growth,which is one of the concerns for tin-lead solder assemblies. To determine the effect of exposure at temperatures higher than 125°C,the aged samples were subjected to 100 thermal shock cycles between –65°Cand150°C.A number of characterization methods were used to ensure the integrity of solder joints. These included nondestructive evaluation by X-ray,daisy-chain monitoring at thermal cycle/aging intervals,and destructive characterization by cross-sectioning. The cycled/aged samples were cross-sectioned and characterized by optical and scanning electron microscopy (SEM). Assembly processes and SEM photomicrographs showing damage progression and IMC/microstructural changes,as well as elemental analyses by x-ray energy dispersive spectroscopy (EDS),were also presented.

The stimulating impact of the automotive industry has sharpened focus on immersion tin (i-Sn) more than ever before. Immersion tin with its associated attributes,is well placed to fulfill the requirements of such a demanding application. In an environment dominated by reliability,the automotive market not only has very stringent specifications but also demands thorough qualification protocols. Qualification is ultimately a costly exercise. The good news is that i-Sn is already qualified by many tier one OSATs. The focus of this paper is to generate awareness of the key factors attributed to soldering i-Sn. Immersion tin is not suitable for wire bonding but ultimately suited for multiple soldering applications. The dominant topics of this paper will be IMC formations in relation to reflow cycles and the associated solderability performance. Under contamination free conditions,i-Sn can provide a solderable finish even after multiple reflow cycles. The reflow conditions employed in this paper are typical for lead free soldering environments and the i-Sn thicknesses are approximately 1 µm.