Circuit complexity and density requirements continue to push PCB fabrication capability limits. Component pitch and routing requirements are continually becoming more aggressive and difficult to achieve in good yield with current fabrication strategies. The trend is to bring the PCB closer to the density requirements currently required for semiconductor packaging. The ability to place interconnecting vias in any location on any layer is crucial to PCB fabricators in meeting this high density interconnect (HDI) trend.
The two fundamental elements in any type of PCB,conductors and dielectrics,both have to be considered when building “any layer” HDI. These PCB’s have specific challenges for processing while maintaining thermal and electrical performance. Careful consideration of the interplay of the fundamental elements is critical to fulfilling all of these requirements.
New methods and materials designed specifically with these challenges in mind are becoming available for building HDI
Using materials specifically designed for HDI PCBs can significantly reduce the challenges producing these boards. However,along with easing the challenges of fabrication,these materials must also demonstrate the right combination of properties to meet electrical and thermal requirements while also being reliable. Validation of these new technologies is currently underway.

Eutectic god-tin (Au80Sn20) is widely used as the die-attach material for making radio-frequency (RF) and microwave devices. The metallic bonding is typically achieved by soldering using a gold-tin preform in a forming gas containing hydrogen (H2) and nitrogen (N2) to a peak temperature at 300°C. The performance and reliability of the devices are strongly dependent on the quality of the die-attach layers. It is always expected to make the die-attach layers as free of voids as possible since the voids are poor thermal and electrical conductors and also are stress concentration centers. There are three major causes for void formation,which include poor solder wetting due to surface oxides,vapor out-gassing by flux decomposition,and gas entrapment from preform melting. It is known that the gas entrapment is more significant for larger dies and can be managed by gas evacuation before the melting of the solder. However,a good fluxless and oxide-free technology for metal die attach is still lacking. The organic fluxes used in conventional soldering not only induce void formation but also leave residues,which contaminate the dies and are corrosive. In addition to being costly and inconvenient to clean,the residues at the bonding interfaces of the die-attach layer are trapped,thus degrading interfacial bonding over time. The current study introduces a novel technology of using electron attachment (EA) to activate H2 diluted with N2 for fluxless die attach. EA is a new concept for ambient-pressure gas activation,which brings several advantages compared with plasma-based gas activation. Results obtained in this study demonstrate that solder oxides and organic contaminations on the surfaces to be bonded can be effectively removed by EA-activated forming gas,which leads to better solder wetting compared to flux-based process. The EA technology also shows a feasibility of reducing peak temperature of die attach from 300°C to 290°C,thus minimizing high-temperature induced damages. These advantages are believed to be attributed to the higher surface tension of the oxide-free molten solder compared with that of an organic flux,thus leading to a larger wetting force. As demonstrated in the study,the fluxless and oxide-free technology using EA has made it possible to achieve a high quality die attach with zero or near-zero (= 5%) voids.

•Voiding of QFN a concern due to large thermal pad,low standoff,and many thermal via
•Divided thermal pad preferred,with SMD better than NSMD
•This work focus on systematic study on effect of SMD divided pad on voiding

In this work we report results of the fracture toughness of a high thermal stability resin system toughened by The Dow Chemical Company proprietary particulate-type toughening material. Results show a significant improvement in the fracture toughness with minimum impact on other thermomechanical properties such as Tg and Td. Because delamination in electrical laminates is a critical failure mechanism observed in such systems,we also investigated the potential synergistic impact of the toughening material (FORTEGRA™ 351) and glass sizing on adhesive properties of the laminate board. Results showed improvements in both shear and tensile strengths of the test vehicles with the addition of the toughener for two different glass finishes. A drilling test showed significant delamination failure for a non-toughened board as observed by a large halo around the drill-hole,and a punch test yielded similar results. Further,it was shown that copper peel strength improved with the addition of the toughener for the two different glass finish types studied. These results are important because they show that use of the toughener and appropriate choice of glass-finish will significantly improve the thermomechanical integrity of high thermal stability test vehicles during downstream part fabrication processes.

Micro Trace Resistor Technology allows thin film resistors to be built within a printed circuit trace that is less than 100 microns wide. Using standard subtractive printed circuit board processes,it is ideal for high density interconnect (HDI) designs where passive component placement is difficult or impossible. By utilizing the differential processes unique to the OhmegaPly® nickel phosphorous (NiP) resistive material,copper traces can be imaged and etched to define resistor widths that are precise and sharply defined,resulting in the creation of miniature resistors with consistent ohmic values. With low inductance and good tolerances,Micro Trace Resistors are ideal for line termination and pull-up/down applications.

•Two primary failure modes from trapped moisture:
•Premature resin decomposition from incomplete resin cross-linking.
•Explosive vaporization during high temperature thermal exposure.

The next generation of smart phones will demand very thin multi-layer boards to reduce the product thickness again. This paper shows three different manufacturing approaches,which can be used for very thin any-layer build-ups. The
technological approaches are compared on reliability level – the any-layer copper filled micro-via technology which is to be
considered as state of the art technology for high end phones and the ALIVH-C/G technology that is well established in Japan. A test vehicle design featuring test coupons for comprehensive reliability test series has been defined as target application for investigation. The applied test vehicle build-ups comprise an 8 layers build-up with total board thickness below 500 µm. The first test vehicle is based on an any-layer HDI build-up including copper filled stacked micro via
structures,the second test vehicle features an 1+6+1 ALIVH-C build-up comprising an outer HDI prepreg layer while the
third test vehicle is built in ALIVH-G technology featuring a full ALIVH build-up.
The influence of the applied manufacturing technology on the reliability performance of thin PCBs is evaluated based on these three test vehicle build-ups. To cover the behavior during SMD component assembly the produced samples are subjected to reflow sensitivity testing applying a lead free reflow profile with a peak temperature of +260ºC. Failure occurrence and the observed failure modes are
evaluated and compared. In parallel a temperature cycling test is conducted on the test vehicles in a temperature range between -40 ºC and +125 ºC in order to evaluate the thermo mechanical reliability of the test vehicles with regard to the manufacturing technology. In order to characterize the reliability aspects influenced by electrochemical migration phenomenon the different samples are subjected to a HAST test at +130 ºC with 85 % humidity level. The results obtained from reliability testing are summarized and compared within this paper. The identified relations between manufacturing technology and the reliability performance of the test vehicles are shown; strengths as well as weaknesses of the applied any-layer technologies are identified and summarized.

Although QFN devices present a challenge to the SMT assembly process with proper stencil design,proper stencil technology selection (Laser,Electroform,Nano-Coat),and proper PCB solder mask layout these challenges can be overcome. The most popular QFN repair seems to be to print solder paste directly onto the QFN leads and ground plane.

Paste release characteristics are driven by the Area Ratio formula,which is based upon conventional stencil foil materials such as a variety of stainless steel alloys,nickel,etc. The surface energy or “phobic” characteristics of these materials are significantly greater than the newer chemistries used to coat stencils and therefore effectively limits the conventional Area Ratio formula in its ability to predict transfer efficiency in ultra-fine pitch devices.

The next generation miniaturised SMT devices waiting to make their mark will require the assembly community to re think their processes and toolsets. The feature sizes that are involved in this new wave of miniaturisation are sub 200 micron,to put this into context,only a decade ago this would have been considered as Semicon domain.
Of all the process involved within the Surface Mount Assembly process the printer is certainly the most sensitive to these changes. But it’s not only about printing miniaturised features – the process engineer has to balance miniaturisation with the requirements of “standard” technology,thus we are experiencing the age of heterogeneous assembly.
Therefore the miniaturisation program is causing the print process to be challenged in new ways especially the impact on the available process window available to achieve high yield heterogeneous assembly
This paper will investigate the impact of miniaturisation and heterogeneous assembly on the print process and strategies to keep one generation ahead.In latest research work,actual paste deposit volumes and transfer efficiency have been monitored and compared for both square and round apertures with area ratio’s ranging from 0.20 thru to 1.35. This covers apertures sizes of between 100 and 550 microns in a nominal 100 micron thick stencil foil. In addition,the effect of ultrasonically activated squeegees (ProActiv) has been assessed as part of the same experiment. A further comparison has also been made between type 4 and type 4.5 solder paste aswell.
The data presented here will help provide guidelines for stencil aperture designs and strategies for ultra-fine pitch components such as 0.3CSP’s.