Higher-speed signal transmission is increasingly required on a printed circuit board to handle massive data in electronic systems. So,signal transmission loss of copper wiring on a printed circuit board has been studied. First,total signal loss was divided into dielectric loss and conductor loss quantitatively based on electromagnetic theory. In particular,the scattering loss due to surface roughness of copper foil has been examined in detail and the usefulness of the copper foil with low surface roughness has been demonstrated.

An IPC specification is a consensus document that specifies attributes relevant to the plated surface. Plating specifications are designed to be applicable to a wide range of products types. As product continues to evolve and new product types are needed,it is necessary for the committee to periodically revise its documents. Between revisions it may be necessary for designers to take exception with one or more of the provision in the specification.

The IPC 4-14 Plating subcommittee has issued a series of specifications starting with ENIG Specification 4552 in 2002 to ENEPIG Specification 4556 in 2013. In between it has issued specification for Immersion Silver 4553 and for Immersion Tin 4554. The committee has made a sincere effort to issue an OSP specification 4555. This effort did not produce results for various reasons.

The committee has completed a revision of the immersion silver specification 4553-A and is presently working on revising the ENIG specification 4552-A.

As new surface finishes come to the forefront the committee will attempt to add new specifications. Examples are palladium on copper,ENIS electroless nickel immersion silver,and plasma nano coatings.

Although traditional plating like electrolytic acid copper and electrolytic tin have been in use since the 1980s,it may be necessary to specify plated attributes as the demands for controlled impedance for high frequency,harsh use environments like automotive,as well as very high reliability like aerospace and medical,put new demands on these plated surfaces.

This paper will give an update of the completed and present activities of the plating committee. It will also attempt to layout a roadmap for future specifications.

In order to provide the functionality in today’s electronics,printed circuit boards are approaching the complexity of semiconductors. For flexible circuits with 1 mil lines and spaces,this means no nodules,no pits,and excellent ductility with thinner deposits. One of the areas that has to change to get to this plateau of technology is acid copper plating. Acid copper systems have changed in minor increments since their introduction decades ago. However,the basic cell design using soluble anodes in slabs or baskets has for the most part remained the same. Soluble,phosphorized,copper anodes introduce particulate and limits the ability to control plating distribution.
The companies worked together to evaluate a new approach using insoluble anodes that are isolated from the main plating bath. Insoluble anodes are known to eliminate the particulate,provide consistent anode area and shape the anode to match the plated part. But isolating the insoluble anode dramatically reduces high consumption of organic additives typical with insoluble anodes. This new approach limits additive breakdown and & consumption normally seen at the soluble anode surface. The end result is a surface free of nodules,pits,and precise control of copper thickness distribution minimizing the impact of breakdown products.
This paper is to document the results from prototype testing through implementation into production. The system was first tested in pilot tanks at the companies to determine the impact on nodules and surface distribution. Data was generated looking at impact of anode design on plating distribution and surface for any defects. This data was utilized to design a full scale production line that is being used to quantify process improvement over existing production equipment. The goal for the work being done is a perfect copper surface.

Copper Via-Fill application in acid copper plating of PWB is experiencing a significant growth due to the booming of smartphone and tablet PC. With this growth,the PC board demand of HDI complexity has also increased. The "any-layer" design is widely adopted in layer count reduction whereas the circuit density is increased due to more freedom in designing the circuitry. This kind of build-up process required 100% blind microvia fill up in every single layer and stack up for interconnect. The challenge of this design is the zero tolerance of dimple/void as well as minimal copper build up for ultra fineline circuit formation. The latest development of via-fill has set the new standard of zero dimple/void with copper build up less than 10 ?m. No copper reduction is required,even for the ultra fineline etching process in which the circuitry goes down from 20/20 ?m L/S to 15/15 ?m L/S. Another challenge of the process is prolonged plating cycle time. This paper will illustrate an advanced super-filling technology which was developed in the combination with green PTH alternative - conductive polymer direct metallization. The direct via-filling on conductive polymer becomes possible which could minimize the use of copper as well as shorten the total process cycle time by more than 50%. The extraordinary coverage of conductive polymer over glass and resin surpass the traditional electroless copper performance; thus enhance the current flow for via-filling. The mechanism of the specialized additive system over the conductive polymer was investigated. Today's equipment for copper via-fill in PWB industry is dominated by either vertical or horizontal conveyorized system. The hydrodynamic impact to super via-fill performance will also be discussed.

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In the area of Printed Electronics,there are a number of functional materials that can include conductors,Semi-conductors,dielectrics,barriers,and adhesives. There are also a smaller subset of functional materials for specialized purposes that are known as Ferroelectric,Piezoelectric,and Pyroelectric materials. The purpose of this presentation is to become acquainted with this group of special functional materials and some examples of where they are being utilized in today’s technology.

The number of failures caused by electrostatic discharges (ESD) has been increasing for some time now. So,it is necessary for everyone,who handles electrostatic sensitive devices (ESDS),to know the reasons of such failures. The paper will give an overview about possible causes for ESD. Particularly automated production lines have some processing steps,where electrostatic charges are increasingly generated. So far one has been focused on the human being. This is controllable. Measurements in production lines show electrostatic charges at the following processing steps: application of soldering paste (printer),assembling (automated and manual (pick and place)),and labeling as well as electric tests (ICT). The electronic components are always assembled directly and without any covering on the PCBs. Thus,the wire bonding process leads to damage of the electronic components. The processing steps,where the PCBs are covered with chassis must be inspected also. Such chassis are mostly made of isolating materials,like plastics. Thus,those can be highly electrostatic charged,while assembling. In summary an optimized ESD Control System for ESD working areas and machines with the emphasis on cost-effectiveness will be compared. Topics: An optimized ESD control system,with an emphasis on cost-effectiveness,Introduction of an optimized ESD Control System for ESD working areas,Solutions for machines and automated processes,Measurement methods in SMT production line and ESD audits,Product quality.

With the push for ever improving performance on semiconductor component I/O interfaces,semiconductor components are being driven into a realm which makes them more sensitive to electrostatic discharge,potentially increasing in sensitivity by 50% every 3-5 years. Today,the majority of modern day semiconductor components are being designed to meet 250Volts of charge device model sensitivity,and that could decrease to 125Volts in the next 3-5 years,and could again decrease to 50Volts-70Volts in the following 3-5 years. The entire electronics industry must prepare for this challenge.
In preparation for this upcoming challenge,we along with some other semiconductor companies are embarking on an educational awareness and preparedness initiative with ODM’s/OEM’s. This includes awareness of the industry technology roadmap,and educating them on what they need to do to prepare for this challenge. As part of the preparedness initiative,we request that they start considering real time electrostatic discharge (ESD) detection within their “high-risk” modules; such as automated surface mount equipment,where direct measurements have confirmed semiconductor components are directly exposed to ESD events.
The call to action for automated surface mount equipment manufacturers is to start to evaluate,and implement,real-time ESD detection technologies in areas where direct contact with the component (i.e.. pick and place) occurs,and incorporating this real-time detection into their new equipment designs,as well as preparing retrofit kits for existing equipment sets. This is not a trivial task and will require time to develop and implement,so we urge the equipment manufacturing community to begin the process now in preparation for the increase in device sensitivity. In this paper,we will share what has learned about real-time ESD event detection in hopes it aids the equipment manufacturer’s preparedness.

Substrates have become more critical with regard to pitch and density in today’s designs with challenges for passive components in terms of surface placement. This negates the opportunity for high speed,high cost components to be placed on the surfaces of the PCB. With this the capacitance and resistive components have to be embedded into the design. This has been accomplished with the advent of buried capacitance cores and buried resistors. Unfortunately this has caused some challenges to the ET Test Centers/Labs in the ability to effectively test these buried passive components. Processes have had to change and adapt to these new technologies. The paper will discuss what these new technologies are and how the Electrical Test arena has adapted to provide accurate testing of the buried resistors and accommodate the buried capacitive cores to not receive false errors from the Grid Testers and Flying Probes.