As feature sizes are driven to be smaller,the cost of PCB fabrication is driven higher. In particular,sequential lamination of complex circuit boards is a time consuming and expensive process. However,industry expectations
are for smaller,faster,and cheaper products. In this paper,we present an alternative to sequential lamination for fabricating complex PCBs,where conductive paste is used as interconnect between cores. All costs associated with traditional methods and interconnect using conductive paste will be analyzed.

Fine pitch/fine feature solder paste printing in PCB assembly has become increasingly difficult as board geometries have become ever more compact. The printing process itself,traditionally the source of 70% of all assembly defects,finds its process window narrowing. The technology of metal blade squeegees,with the aid of new materials,understanding,and settings such as blade angle,has kept pace with all but the smallest applications,e.g.,200µ - .50 AR and 150µ - .375 AR,which have been pushing blade printing technology to its limits.
Enclosed media print head technology has existed,and has been under increasing development,as an alternative to metal squeegee blade printing. Until recently,the performance of enclosed print heads had been comparable to the very best metal squeegees,but advances in enclosed print media technology have now made it a superior alternative to squeegee blades in virtually all applications.

The electronics market is divided into many segments each having its own challenges; but one theme that connects the electronics community together is a need for higher yield with lower costs. Or simply the manufacturing process needs to become ever efficient.
Within the consumer sector miniaturisation is the watch-word and all eyes are on the 0.3mm CSP and metric 03015 components. Both of these devices will pose serious heterogeneous questions for High Volume Manufactures,especially if the current stencil thickness of 100 microns is required for standard technology.
The Automotive and Industrial electronics sector which are not normally brushed with the challenges of miniaturisation have started to become connected to this demanding world. The reason for this is not through the consumer driver of increased functionality,but one of pure supply and demand economics. The demands for large foot print devices are decreasing therefore the unit price and scarcity is increasing; whereas smaller foot print devices are increasing in demand and availability and as a consequence the unit price and scarcity is reducing. For this reason Automotive and Industrial electronic manufacturers are now faced with implementing fine pitch devices due to availability and cost.
The Automotive and Industrial electronics sector have several large obstructions when engaging with miniaturised devices: - the addition of large devices on the same product,harsh environmental concerns and safety/reliability demands. All of these issues require a highly capable heterogeneous solder paste printing process.
This paper investigates a solution the Automotive and Industrial electronics community can implement to ensure a high yield print process in which fine pitch footprint devices can be printed alongside traditional larger footprint devices.

A novel epoxy flux was developed with good compatibility with no-clean solder pastes,which imparts high reliability for BGA assembly at a low cost. This compatibility with solder pastes is achieved by a well-engineered miscibility between epoxy and no-clean solder paste flux systems,and is further assured with the introduction of a venting channel. The compatibility enables a single bonding step for BGAs or CSPs,which exhibit high thermal warpage,to form a high-reliability assembly. Requirements in drop test,thermal cycling test (TCT),and SIR were all met. The high viscosity stability at ambient temperature is another critical element in building a robust and user-friendly epoxy flux system. The material was found to able to be deposited with dipping,dispensing,and jetting. Its 75°C Tg facilitated good reworkability and minimizes the adverse impact of unfilled underfill material on TCT of BGA assemblies.

An estimated 80% of all SMT assembly in the world is performed with a no-clean soldering process,largely due to the
predominance of consumer-type electronics. The continuing trend of increasing miniaturization that dominates modern electronics devices requires no-clean flux residues to be as benign and electrically resistive as possible. Solder pastes with a IPC J-STD-004 [1] classification of ROL0 or ROL1 rely heavily on two basic mechanisms to render the flux residue as “noclean”: (1) the encapsulating properties that the rosin provides and (2) the heat activation/decomposition of the chemicals in
the flux,commonly known as “activators.” The latter is generally known in the industry,but is rarely taken into consideration for reflow profiling in SMT assembly. Optimization of a reflow profile often focuses on mitigating defects such as voiding,tombstoning,graping,slumping/bridging,etc. However,little thought is given to the reflow profile’s effect on the electrical
reliability of the no-clean flux residue. Because of the wide variation in size and thermal density of SMT components and PCBs,achieving a reflow profile that equally heats the entire assembly can be challenging and often impossible. The temperature under a large component,such as a BGA,is often markedly cooler than a smaller component,such as a passive resistor or capacitor. This paper will discuss an experiment that studied the effect of reflow profiling on the electrical reliability of no-clean flux residues that can be measured using IPC J-STD-004[1] surface insulation resistance (SIR) testing. Both a
halogen-free (ROL0) and a halogen-containing (ROL1) Pb-free no-clean solder paste,exposed to various reflow profiles,were
used in this study.

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Looking back twenty-five years ago,the solder pastes residues had to be cleaned after reflow due to their corrosive nature; two ways of cleaning were possible,either with solvent or by using water,with or without detergent. Now the assembly world is mainly no-clean: paste formulation is safer in terms of chemical reliability and process costs are reduced without cleaning. However,some applications,i.e. military,aerospace,high frequency,semiconductor require a perfect elimination of the residue after reflow. There are several options to achieve this result: the use of a no-clean paste which residue can be removed with the most suitable cleaning method or use the paste desiged to be cleaned,as a water soluble solder paste.
The water-soluble solder pastes generally show great wettability because of tehir strong activation but they are also known to have shorter stencil life and to be more sensitive to working conditions as temperature and humidity,compared to the no-clean pastes. Additionaly,with the components stad-off getting smaller and smaller,washing residues with water only is more and more challenging due to its high surface tension; the addition of detergent becomes often necessary.
The purpose of this paper is to highlight the differences between these two families of solder pastes to guide users in their choice. This will be achieved through the comparison of several recent water-soluble and no-clean formulations as far as reliability is concerned. First the printing quality will be evaluated (viscosity,tack,cold slump,printing speed according to pressure,stemcil life,idle time,printing consistency). Then the reflow properties will be compared (hot slump,solderballing,refow process window,wetting ability on different finishes). Finally the residue cleanibility will be assessed. The IPC SIR will be also done to conclude the study. Bth standardized tests and production tests will be used to evaluate the performance on these two kinds of solder pastes.

Looking back twenty-five years ago,the solder pastes residues had to be cleaned after reflow due to their corrosive nature; two ways of cleaning were possible,either with solvent or by using water,with or without detergent. Now the assembly world is mainly no-clean: paste formulation is safer in terms of chemical reliability and process costs are reduced without cleaning. However,some applications,i.e. military,aerospace,high frequency,semiconductor require a perfect elimination of the residue after reflow. There are several options to achieve this result: the use of a no-clean paste which residue can be removed with the most suitable cleaning method or use the paste desiged to be cleaned,as a water soluble solder paste.
The water-soluble solder pastes generally show great wettability because of tehir strong activation but they are also known to have shorter stencil life and to be more sensitive to working conditions as temperature and humidity,compared to the no-clean pastes. Additionaly,with the components stad-off getting smaller and smaller,washing residues with water only is more and more challenging due to its high surface tension; the addition of detergent becomes often necessary.
The purpose of this paper is to highlight the differences between these two families of solder pastes to guide users in their choice. This will be achieved through the comparison of several recent water-soluble and no-clean formulations as far as reliability is concerned. First the printing quality will be evaluated (viscosity,tack,cold slump,printing speed according to pressure,stemcil life,idle time,printing consistency). Then the reflow properties will be compared (hot slump,solderballing,refow process window,wetting ability on different finishes). Finally the residue cleanibility will be assessed. The IPC SIR will be also done to conclude the study. Bth standardized tests and production tests will be used to evaluate the performance on these two kinds of solder pastes.

During the last period of newly assembled electrical devices (pcbs),new component types like LGA and QFN were also qualified as well as smaller passive components with reliability requirements based on the automotive and industrial industry. In the narrow gaps under components,residues can accumulate more by the capillary forces. This is not that much a surface resistance than an interface issue. Also that the flux residues under such types of components creates interaction with the solder resists from the pcb,as well as the component body was not completely described in the standard SIR measurement. On the other hand also,electrical influence with higher voltage creates new terms and conditions,in particular the combination of power and logic in such devices. The standard SIR measurement cannot analyze those combinations. The paper will discuss the requirements for a measurement process,and will give results. The influences of the pcb and component quality will also be discussed. Furthermore it will describe requirements for nc solder paste to increase the chemical/thermical/electrical reliability for whole devices.

Conductive filament formation or CAF typically occurs in two steps: degradation of the resin/glass fiber bond followed by an electrochemical reaction. Bond degradation provides a path along which electro-deposition occurs due to electrochemical reaction. The path results from poor glass treatment,from the hydrolysis of the silane glass finish,or from mechanical stresses. Once a path is formed,an aqueous layer can develop through the adsorption,absorption,and capillary action of moisture at the resin/fiber interface. The path can be modeled as an electrochemical cell,in which the metal conductors are the electrodes,the driving potential for the electrochemistry is the operating potential of the circuit,and the electrolyte is the absorbed moisture.
Microscopic examinations of failure sites have shown that conductive filaments can be formed along debonded or delaminated fiber glass/epoxy resin interfaces due to breaking of the organosilane bonds. The organosilane bonds can be chemically degraded by hydrolysis (adsorption of water at the fiber glass/epoxy resin interface) or by repeated thermal cycling,which induces stresses at the interface due to coefficient of thermal expansion mismatches. This paper discusses the formation of pathways due to the degradation of organosilanes.